[ARM] Add a SelectTAddrModeImm7 for MVE narrow loads and stores

[dmgreen]

Summary

We were previously using the SelectT2AddrModeImm7 for both normal and narrowing MVE loads/stores. As the narrowing ones do not accept sp as a register, it makes little sense to optimise a FrameIndex into the load, only to have to recover that later on. This adds a SelectTAddrModeImm7 which does not do that folding and uses it for narrowing load/store patterns.

[samparker]

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

1159 ↗

(On Diff #219878)

What happens if N == ISD::ADD?

[dmgreen]

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

1159 ↗

(On Diff #219878)

Oh, i forgot to mention that this is just a copy of SelectT2AddrModeImm7, with the part about FrameIndex's removed. The other code is the same, so I hope will work as well as it did before.

I think isBaseWithConstantOffset will handle adds (and or's where we know the alignment). We just don't negate the RHSC.

1285 ↗

(On Diff #219878)

This one.

[samparker]

LGTM

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

1159 ↗

(On Diff #219878)

Ah, ok then.

llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
                                 SDValue &OffImm);
   bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
                                  SDValue &OffImm);
   bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
                                  SDValue &OffImm);
   bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
                                  SDValue &OffImm);
   bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
+  template <unsigned Shift>
+  bool SelectTAddrModeImm7(SDValue N, SDValue &Base, SDValue &OffImm);
 
   // Thumb 2 Addressing Modes:
   bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
   bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
                             SDValue &OffImm);
   bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
                                  SDValue &OffImm);
   template <unsigned Shift>
if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
         }
       }
     }
   }
 
   return false;
 }
 
+template <unsigned Shift>
+bool ARMDAGToDAGISel::SelectTAddrModeImm7(SDValue N, SDValue &Base,
+                                          SDValue &OffImm) {
+  if (N.getOpcode() == ISD::SUB || CurDAG->isBaseWithConstantOffset(N)) {
+    int RHSC;
+    if (isScaledConstantInRange(N.getOperand(1), 1 << Shift, -0x7f, 0x80,
+                                RHSC)) {
+      Base = N.getOperand(0);
+      if (N.getOpcode() == ISD::SUB)
+        RHSC = -RHSC;
+      OffImm =
+          CurDAG->getTargetConstant(RHSC * (1 << Shift), SDLoc(N), MVT::i32);
+      return true;
+    }
+  }
+
+  // Base only.
+  Base = N;
+  OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
+  return true;
+}
+
 
 //===----------------------------------------------------------------------===//
 //                        Thumb 2 Addressing Modes
 //===----------------------------------------------------------------------===//
 
 
 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
                                             SDValue &Base, SDValue &OffImm) {

llvm/trunk/lib/Target/ARM/ARMInstrMVE.td

 
 // taddrmode_imm7  := reg[r0-r7] +/- (imm7 << shift)
 class TMemImm7ShiftOffsetAsmOperand<int shift> : AsmOperandClass {
   let Name = "TMemImm7Shift"#shift#"Offset";
   let PredicateMethod = "isMemImm7ShiftedOffset<"#shift#",ARM::tGPRRegClassID>";
   let RenderMethod = "addMemImmOffsetOperands";
 }
 
-class taddrmode_imm7<int shift> : MemOperand {
+class taddrmode_imm7<int shift> : MemOperand,
+    ComplexPattern<i32, 2, "SelectTAddrModeImm7<"#shift#">", []>  {
   let ParserMatchClass = TMemImm7ShiftOffsetAsmOperand<shift>;
   // They are printed the same way as the T2 imm8 version
   let PrintMethod = "printT2AddrModeImm8Operand<false>";
   // This can also be the same as the T2 version.
   let EncoderMethod = "getT2AddrModeImmOpValue<7,"#shift#">";
   let DecoderMethod = "DecodeTAddrModeImm7<"#shift#">";
   let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
 }
def truncstorevi16_align2 : PatFrag<(ops node:$val, node:$ptr),
                                       (truncstorevi16 node:$val, node:$ptr)>;
   def post_truncstvi16_align2 : PatFrag<(ops node:$val, node:$base, node:$offset),
                                         (post_truncstvi16 node:$val, node:$base, node:$offset)>;
   def pre_truncstvi16_align2 : PatFrag<(ops node:$val, node:$base, node:$offset),
                                        (pre_truncstvi16 node:$val, node:$base, node:$offset)>;
 }
 
 let Predicates = [HasMVEInt] in {
-  def : Pat<(truncstorevi8 (v8i16 MQPR:$val), t2addrmode_imm7<0>:$addr),
-            (MVE_VSTRB16 MQPR:$val, t2addrmode_imm7<0>:$addr)>;
-  def : Pat<(truncstorevi8 (v4i32 MQPR:$val), t2addrmode_imm7<0>:$addr),
-            (MVE_VSTRB32 MQPR:$val, t2addrmode_imm7<0>:$addr)>;
-  def : Pat<(truncstorevi16_align2 (v4i32 MQPR:$val), t2addrmode_imm7<1>:$addr),
-            (MVE_VSTRH32 MQPR:$val, t2addrmode_imm7<1>:$addr)>;
+  def : Pat<(truncstorevi8 (v8i16 MQPR:$val), taddrmode_imm7<0>:$addr),
+            (MVE_VSTRB16 MQPR:$val, taddrmode_imm7<0>:$addr)>;
+  def : Pat<(truncstorevi8 (v4i32 MQPR:$val), taddrmode_imm7<0>:$addr),
+            (MVE_VSTRB32 MQPR:$val, taddrmode_imm7<0>:$addr)>;
+  def : Pat<(truncstorevi16_align2 (v4i32 MQPR:$val), taddrmode_imm7<1>:$addr),
+            (MVE_VSTRH32 MQPR:$val, taddrmode_imm7<1>:$addr)>;
 
   def : Pat<(post_truncstvi8 (v8i16 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<0>:$addr),
             (MVE_VSTRB16_post MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
   def : Pat<(post_truncstvi8 (v4i32 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<0>:$addr),
             (MVE_VSTRB32_post MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
   def : Pat<(post_truncstvi16_align2 (v4i32 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<1>:$addr),
             (MVE_VSTRH32_post MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<1>:$addr)>;
 
def _Z   : Pat<(!cast<ValueType>("v" # DestLanes # "i" # DestElemBits)
                    am:$addr)>;
   def _S   : Pat<(!cast<ValueType>("v" # DestLanes # "i" # DestElemBits)
                    (!cast<PatFrag>("sextloadvi"  # SrcElemBits # Align) am:$addr)),
                  (!cast<Instruction>("MVE_VLDR" # SrcElemType # "S" # DestElemBits)
                    am:$addr)>;
 }
 
 let Predicates = [HasMVEInt] in {
-  defm : MVEExtLoad<"4", "32", "8",  "B", "", t2addrmode_imm7<0>>;
-  defm : MVEExtLoad<"8", "16", "8",  "B", "", t2addrmode_imm7<0>>;
-  defm : MVEExtLoad<"4", "32", "16", "H", "_align2", t2addrmode_imm7<1>>;
+  defm : MVEExtLoad<"4", "32", "8",  "B", "", taddrmode_imm7<0>>;
+  defm : MVEExtLoad<"8", "16", "8",  "B", "", taddrmode_imm7<0>>;
+  defm : MVEExtLoad<"4", "32", "16", "H", "_align2", taddrmode_imm7<1>>;
 }
 
 
 // Bit convert patterns
 
 let Predicates = [HasMVEInt] in {
   def : Pat<(v2f64 (bitconvert (v2i64 MQPR:$src))), (v2f64 MQPR:$src)>;
   def : Pat<(v2i64 (bitconvert (v2f64 MQPR:$src))), (v2i64 MQPR:$src)>;

llvm/trunk/test/CodeGen/Thumb2/mve-stack.ll

 
 define arm_aapcs_vfpcc void @vstrh32() {
 ; CHECK-LABEL: vstrh32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
-; CHECK-NEXT:    vmov.i32 q0, #0x6
 ; CHECK-NEXT:    mov r0, sp
+; CHECK-NEXT:    vmov.i32 q0, #0x6
 ; CHECK-NEXT:    vstrh.32 q0, [r0, #4]
-; CHECK-NEXT:    mov r0, sp
 ; CHECK-NEXT:    bl func
 ; CHECK-NEXT:    add sp, #8
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %d = alloca [4 x i16], align 2
   %g = getelementptr inbounds [4 x i16], [4 x i16]* %d, i32 0, i32 2
   %b = bitcast i16* %g to <4 x i16>*
   store <4 x i16> <i16 6, i16 6, i16 6, i16 6>, <4 x i16>* %b, align 2
   %arraydecay = getelementptr inbounds [4 x i16], [4 x i16]* %d, i32 0, i32 0
   call arm_aapcs_vfpcc void bitcast (void (...)* @func to void (i16*)*)(i16* %arraydecay)
   ret void
 }
 
 define arm_aapcs_vfpcc void @vstrb32() {
 ; CHECK-LABEL: vstrb32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
-; CHECK-NEXT:    vmov.i32 q0, #0x6
-; CHECK-NEXT:    mov r0, sp
-; CHECK-NEXT:    vstrb.32 q0, [r0, #6]
 ; CHECK-NEXT:    add r0, sp, #4
+; CHECK-NEXT:    vmov.i32 q0, #0x6
+; CHECK-NEXT:    vstrb.32 q0, [r0, #2]
 ; CHECK-NEXT:    bl func
 ; CHECK-NEXT:    add sp, #8
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %d = alloca [4 x i8], align 2
   %g = getelementptr inbounds [4 x i8], [4 x i8]* %d, i32 0, i32 2
   %b = bitcast i8* %g to <4 x i8>*
   store <4 x i8> <i8 6, i8 6, i8 6, i8 6>, <4 x i8>* %b, align 2
   %arraydecay = getelementptr inbounds [4 x i8], [4 x i8]* %d, i32 0, i32 0
   call arm_aapcs_vfpcc void bitcast (void (...)* @func to void (i8*)*)(i8* %arraydecay)
   ret void
 }
 
 define arm_aapcs_vfpcc void @vstrb16() {
 ; CHECK-LABEL: vstrb16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
-; CHECK-NEXT:    vmov.i32 q0, #0x0
 ; CHECK-NEXT:    mov r0, sp
+; CHECK-NEXT:    vmov.i32 q0, #0x0
 ; CHECK-NEXT:    vstrb.16 q0, [r0, #2]
-; CHECK-NEXT:    mov r0, sp
 ; CHECK-NEXT:    bl func
 ; CHECK-NEXT:    add sp, #8
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %d = alloca [8 x i8], align 2
   %g = getelementptr inbounds [8 x i8], [8 x i8]* %d, i32 0, i32 2
   %b = bitcast i8* %g to <8 x i8>*
   store <8 x i8> zeroinitializer, <8 x i8>* %b, align 2
entry:
   %b = bitcast i8* %g to <16 x i8>*
   %l = load <16 x i8>, <16 x i8>* %b, align 2
   ret <16 x i8> %l
 }
 
 define arm_aapcs_vfpcc <4 x i16> @vldrh32() {
 ; CHECK-LABEL: vldrh32:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    .save {r7, lr}
-; CHECK-NEXT:    push {r7, lr}
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
-; CHECK-NEXT:    mov r0, sp
+; CHECK-NEXT:    mov r4, sp
+; CHECK-NEXT:    mov r0, r4
 ; CHECK-NEXT:    bl func
-; CHECK-NEXT:    mov r0, sp
-; CHECK-NEXT:    vldrh.u32 q0, [r0, #4]
+; CHECK-NEXT:    vldrh.u32 q0, [r4, #4]
 ; CHECK-NEXT:    add sp, #8
-; CHECK-NEXT:    pop {r7, pc}
+; CHECK-NEXT:    pop {r4, pc}
 entry:
   %d = alloca [4 x i16], align 2
   %arraydecay = getelementptr inbounds [4 x i16], [4 x i16]* %d, i32 0, i32 0
   call arm_aapcs_vfpcc void bitcast (void (...)* @func to void (i16*)*)(i16* %arraydecay)
   %g = getelementptr inbounds [4 x i16], [4 x i16]* %d, i32 0, i32 2
   %b = bitcast i16* %g to <4 x i16>*
   %l = load <4 x i16>, <4 x i16>* %b, align 2
   ret <4 x i16> %l
 }
 
 define arm_aapcs_vfpcc <4 x i8> @vldrb32() {
 ; CHECK-LABEL: vldrb32:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    .save {r7, lr}
-; CHECK-NEXT:    push {r7, lr}
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
-; CHECK-NEXT:    add r0, sp, #4
+; CHECK-NEXT:    add r4, sp, #4
+; CHECK-NEXT:    mov r0, r4
 ; CHECK-NEXT:    bl func
-; CHECK-NEXT:    mov r0, sp
-; CHECK-NEXT:    vldrb.u32 q0, [r0, #6]
+; CHECK-NEXT:    vldrb.u32 q0, [r4, #2]
 ; CHECK-NEXT:    add sp, #8
-; CHECK-NEXT:    pop {r7, pc}
+; CHECK-NEXT:    pop {r4, pc}
 entry:
   %d = alloca [4 x i8], align 2
   %arraydecay = getelementptr inbounds [4 x i8], [4 x i8]* %d, i32 0, i32 0
   call arm_aapcs_vfpcc void bitcast (void (...)* @func to void (i8*)*)(i8* %arraydecay)
   %g = getelementptr inbounds [4 x i8], [4 x i8]* %d, i32 0, i32 2
   %b = bitcast i8* %g to <4 x i8>*
   %l = load <4 x i8>, <4 x i8>* %b, align 2
   ret <4 x i8> %l
 }
 
 define arm_aapcs_vfpcc <8 x i8> @vldrb16() {
 ; CHECK-LABEL: vldrb16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    .save {r7, lr}
-; CHECK-NEXT:    push {r7, lr}
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
-; CHECK-NEXT:    mov r0, sp
+; CHECK-NEXT:    mov r4, sp
+; CHECK-NEXT:    mov r0, r4
 ; CHECK-NEXT:    bl func
-; CHECK-NEXT:    mov r0, sp
-; CHECK-NEXT:    vldrb.u16 q0, [r0, #2]
+; CHECK-NEXT:    vldrb.u16 q0, [r4, #2]
 ; CHECK-NEXT:    add sp, #8
-; CHECK-NEXT:    pop {r7, pc}
+; CHECK-NEXT:    pop {r4, pc}
 entry:
   %d = alloca [8 x i8], align 2
   %arraydecay = getelementptr inbounds [8 x i8], [8 x i8]* %d, i32 0, i32 0
   call arm_aapcs_vfpcc void bitcast (void (...)* @func to void (i8*)*)(i8* %arraydecay)
   %g = getelementptr inbounds [8 x i8], [8 x i8]* %d, i32 0, i32 2
   %b = bitcast i8* %g to <8 x i8>*
   %l = load <8 x i8>, <8 x i8>* %b, align 2
   ret <8 x i8> %l
 }
 
 declare dso_local arm_aapcs_vfpcc void @func(...)