We were previously using the SelectT2AddrModeImm7 for both normal and narrowing MVE loads/stores. As the narrowing ones do not accept sp as a register, it makes little sense to optimise a FrameIndex into the load, only to have to recover that later on. This adds a SelectTAddrModeImm7 which does not do that folding and uses it for narrowing load/store patterns.
Details
Details
Diff Detail
Diff Detail
- Repository
- rL LLVM
Event Timeline
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | ||
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1159 ↗ | (On Diff #219878) | What happens if N == ISD::ADD? |
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | ||
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1159 ↗ | (On Diff #219878) | Oh, i forgot to mention that this is just a copy of SelectT2AddrModeImm7, with the part about FrameIndex's removed. The other code is the same, so I hope will work as well as it did before. I think isBaseWithConstantOffset will handle adds (and or's where we know the alignment). We just don't negate the RHSC. |
1285 ↗ | (On Diff #219878) | This one. |