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[ARM] Add a SelectTAddrModeImm7 for MVE narrow loads and stores
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Authored by dmgreen on Sep 12 2019, 3:51 AM.

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Summary

We were previously using the SelectT2AddrModeImm7 for both normal and narrowing MVE loads/stores. As the narrowing ones do not accept sp as a register, it makes little sense to optimise a FrameIndex into the load, only to have to recover that later on. This adds a SelectTAddrModeImm7 which does not do that folding and uses it for narrowing load/store patterns.

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Event Timeline

dmgreen created this revision.Sep 12 2019, 3:51 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 12 2019, 3:51 AM
samparker added inline comments.Sep 17 2019, 2:19 AM
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
1159 ↗(On Diff #219878)

What happens if N == ISD::ADD?

dmgreen marked 3 inline comments as done.Sep 17 2019, 2:28 AM
dmgreen added inline comments.
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
1159 ↗(On Diff #219878)

Oh, i forgot to mention that this is just a copy of SelectT2AddrModeImm7, with the part about FrameIndex's removed. The other code is the same, so I hope will work as well as it did before.

I think isBaseWithConstantOffset will handle adds (and or's where we know the alignment). We just don't negate the RHSC.

1285 ↗(On Diff #219878)

This one.

samparker accepted this revision.Sep 17 2019, 2:43 AM

LGTM

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
1159 ↗(On Diff #219878)

Ah, ok then.

This revision is now accepted and ready to land.Sep 17 2019, 2:43 AM
This revision was automatically updated to reflect the committed changes.