[AMDGPU] Enable constant offset promotion to immediate operand for VMEM stores

[vpykhtin]

Summary

This was left disabled for some reason, let's enable.

[arsenm]

Needs tests

[vpykhtin]

Added test. There're some failures in GlobalISel tests need to check if its connected.

[vpykhtin]

llvm-check is now passing, previous failures were irrelevant to this patch.

[vpykhtin]

ping

[rampitec]

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

1326

nullptr or !TII->getNamedOperand()

1326

Stores also have vdata, aren't they?

test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir

194

Needs test where stores are actually combined.

[vpykhtin]

test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir

194

I'm not sure what do you mean, this is about address offset promotion, in this sence it is combined.

[vpykhtin]

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

1326

this was done to save the original semantic for mayLoad checks, I'm not sure why it is used.

[rampitec]

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

1326

What will happen it you remove mayLoad() from this condition? I think it will still work as expected.

test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir

194

I see, that is constant promotion, not the combining.

[vpykhtin]

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

1326

Looks like this check is related to RMW atomics, which are supposed to be added later, but they are now skipped by the first check.

If I remove mayLoad check then it would skip stores.

[rampitec]

LGTM

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base,
   Addr.Offset = (*Offset0P & 0x00000000ffffffff) | (Offset1 << 32);
 }
 
 bool SILoadStoreOptimizer::promoteConstantOffsetToImm(
     MachineInstr &MI,
     MemInfoMap &Visited,
     SmallPtrSet<MachineInstr *, 4> &AnchorList) {
 
+  if (!(MI.mayLoad() ^ MI.mayStore()))
+    return false;
+
   // TODO: Support flat and scratch.
-  if (AMDGPU::getGlobalSaddrOp(MI.getOpcode()) < 0 ||
-      TII->getNamedOperand(MI, AMDGPU::OpName::vdata) != NULL)
+  if (AMDGPU::getGlobalSaddrOp(MI.getOpcode()) < 0)
     return false;
 
-  // TODO: Support Store.
-  if (!MI.mayLoad())
+  if (MI.mayLoad() && TII->getNamedOperand(MI, AMDGPU::OpName::vdata) != NULL)
     return false;
 
   if (AnchorList.count(&MI))
     return false;
 
   LLVM_DEBUG(dbgs() << "\nTryToPromoteConstantOffsetToImmFor "; MI.dump());
 
   if (TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm()) {

test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir

body:             |
     %23:vgpr_32, dead %24:sreg_64_xexec = V_ADDC_U32_e64 %17, %20.sub1, killed %22, 0, implicit $exec
 
     %25:sgpr_32 = S_MOV_B32 6144
     %26:vgpr_32, %27:sreg_64_xexec = V_ADD_I32_e64 %21, %25, 0, implicit $exec
     %28:vgpr_32, dead %29:sreg_64_xexec = V_ADDC_U32_e64 %23, 4294967295, killed %27, 0, implicit $exec
     %30:vreg_64 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1
     %31:vreg_64 = GLOBAL_LOAD_DWORDX2 %30, 0, 0, 0, 0, implicit $exec
 ...
+---
+
+# GFX9-LABEL: name: diffoporder_add_store
+# GFX9: GLOBAL_STORE_DWORD %{{[0-9]+}}, %0.sub0, 1000, 0, 0, 0
+# GFX9: GLOBAL_STORE_DWORD %{{[0-9]+}}, %0.sub1, 0, 0, 0, 0
+
+name: diffoporder_add_store
+body:             |
+  bb.0.entry:
+
+    %0:vreg_64 = COPY $vgpr0_vgpr1
+
+    %1:sgpr_32 = S_MOV_B32 4000
+    %2:vgpr_32, %3:sreg_64_xexec = V_ADD_I32_e64 %0.sub0, %1, 0, implicit $exec
+    %4:vgpr_32, dead %5:sreg_64_xexec = V_ADDC_U32_e64 %0.sub1, 0, %3, 0, implicit $exec
+    %6:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %4, %subreg.sub1
+    GLOBAL_STORE_DWORD %6, %0.sub0, 0, 0, 0, 0, implicit $exec
+
+    %8:sgpr_32 = S_MOV_B32 3000
+    %9:vgpr_32, %10:sreg_64_xexec = V_ADD_I32_e64 %0.sub0, %8, 0, implicit $exec
+    %11:vgpr_32, dead %12:sreg_64_xexec = V_ADDC_U32_e64 %0.sub1, 0, %10, 0, implicit $exec
+    %13:vreg_64 = REG_SEQUENCE %9, %subreg.sub0, %11, %subreg.sub1
+    GLOBAL_STORE_DWORD %13, %0.sub1, 0, 0, 0, 0, implicit $exec
+...