Page MenuHomePhabricator

[ARM][MVE] Decoding of VMSR doesn't diagnose some unpredictable encodings
ClosedPublic

Authored by MarkMurrayARM on Aug 29 2019, 5:30 AM.

Details

Summary

Decoding of VMSR doesn't diagnose some unpredictable encodings, as the unpredictable bits are not correctly set.

Diff-reduce this instruction's internals WRT VMRS so I can see the differences better. Mostly this is s/src/Rt/g.

Fill in the "should-be-(0)" bits.

Designate the Unpredictable{} bits for both VMRS and VMSR.

Diff Detail

Repository
rL LLVM

Event Timeline

MarkMurrayARM created this revision.Aug 29 2019, 5:30 AM
ostannard accepted this revision.Sep 3 2019, 1:46 AM
ostannard added a subscriber: ostannard.

LGTM with one style nit.

lib/Target/ARM/ARMInstrVFP.td
2412 ↗(On Diff #217844)

These lines could be collapsed together:

let Inst{11-0} = 0b101000010000;
This revision is now accepted and ready to land.Sep 3 2019, 1:46 AM
MarkMurrayARM marked an inline comment as done.Sep 3 2019, 2:49 AM
MarkMurrayARM added inline comments.
lib/Target/ARM/ARMInstrVFP.td
2412 ↗(On Diff #217844)

Sure, that would be shorter, but this way matches the way the bits are described in the official public documentation.If future decodings start to use these bits, then diffs should be less disruptive.

Also, this way matches the existing VMRS instruction.

This revision was automatically updated to reflect the committed changes.