[mips] Use less registers to load address of TargetExternalSymbol

[atanasyan]

Summary

There is no pattern matched add hi, (MipsLo texternalsym). As a result, loading an address of 32-bit symbol requires two registers and one more additional instruction:

addiu $1, $zero, %lo(foo)
lui   $2, %hi(foo)
addu  $25, $2, $1

This patch adds the missed pattern and enables generation more effective set of instructions:

lui   $1, %hi(foo)
addiu $25, $1, %lo(foo)

[Petar.Avramovic]

LGTM.

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

multiclass MipsHiLoRelocs<Instruction Lui, Instruction Addiu,
   def : MipsPat<(add GPROpnd:$hi, (MipsLo tblockaddress:$lo)),
                 (Addiu GPROpnd:$hi, tblockaddress:$lo)>;
   def : MipsPat<(add GPROpnd:$hi, (MipsLo tjumptable:$lo)),
                 (Addiu GPROpnd:$hi, tjumptable:$lo)>;
   def : MipsPat<(add GPROpnd:$hi, (MipsLo tconstpool:$lo)),
                 (Addiu GPROpnd:$hi, tconstpool:$lo)>;
   def : MipsPat<(add GPROpnd:$hi, (MipsLo tglobaltlsaddr:$lo)),
                 (Addiu GPROpnd:$hi, tglobaltlsaddr:$lo)>;
+  def : MipsPat<(add GPROpnd:$hi, (MipsLo texternalsym:$lo)),
+                (Addiu GPROpnd:$hi, texternalsym:$lo)>;
 }
 
 // wrapper_pic
 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
       MipsPat<(MipsWrapper RC:$gp, node:$in), (ADDiuOp RC:$gp, node:$in)>;
 
 let AdditionalPredicates = [NotInMicroMips] in {
   defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>, ISA_MIPS1;

llvm/trunk/test/CodeGen/Mips/indirect-jump-hazard/long-calls.ll

 ; O32-NEXT:    addiu $sp, $sp, -24
 ; O32-NEXT:    .cfi_def_cfa_offset 24
 ; O32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; O32-NEXT:    .cfi_offset 31, -4
 ; O32-NEXT:    lui $1, %hi(callee)
 ; O32-NEXT:    addiu $25, $1, %lo(callee)
 ; O32-NEXT:    jalr.hb $25
 ; O32-NEXT:    nop
-; O32-NEXT:    addiu $1, $zero, %lo(memset)
-; O32-NEXT:    lui $2, %hi(memset)
-; O32-NEXT:    addu $25, $2, $1
 ; O32-NEXT:    lui $1, %hi(val)
 ; O32-NEXT:    addiu $4, $1, %lo(val)
+; O32-NEXT:    lui $1, %hi(memset)
+; O32-NEXT:    addiu $25, $1, %lo(memset)
 ; O32-NEXT:    addiu $5, $zero, 0
 ; O32-NEXT:    jalr.hb $25
 ; O32-NEXT:    addiu $6, $zero, 80
 ; O32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; O32-NEXT:    jr $ra
 ; O32-NEXT:    addiu $sp, $sp, 24
 ;
 ; N32-LABEL: caller:
 ; N32:       # %bb.0:
 ; N32-NEXT:    addiu $sp, $sp, -16
 ; N32-NEXT:    .cfi_def_cfa_offset 16
 ; N32-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
 ; N32-NEXT:    .cfi_offset 31, -8
 ; N32-NEXT:    lui $1, %hi(callee)
 ; N32-NEXT:    addiu $25, $1, %lo(callee)
 ; N32-NEXT:    jalr.hb $25
 ; N32-NEXT:    nop
-; N32-NEXT:    addiu $1, $zero, %lo(memset)
-; N32-NEXT:    lui $2, %hi(memset)
-; N32-NEXT:    addu $25, $2, $1
 ; N32-NEXT:    lui $1, %hi(val)
 ; N32-NEXT:    addiu $4, $1, %lo(val)
+; N32-NEXT:    lui $1, %hi(memset)
+; N32-NEXT:    addiu $25, $1, %lo(memset)
 ; N32-NEXT:    daddiu $5, $zero, 0
 ; N32-NEXT:    jalr.hb $25
 ; N32-NEXT:    daddiu $6, $zero, 80
 ; N32-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
 ; N32-NEXT:    jr $ra
 ; N32-NEXT:    addiu $sp, $sp, 16
 ;
 ; N64-LABEL: caller:

 ; N64-NEXT:    nop
 ; N64-NEXT:    daddiu $1, $zero, %higher(memset)
 ; N64-NEXT:    lui $2, %highest(memset)
 ; N64-NEXT:    daddu $1, $2, $1
 ; N64-NEXT:    dsll $1, $1, 16
 ; N64-NEXT:    lui $2, %hi(memset)
 ; N64-NEXT:    daddu $1, $1, $2
 ; N64-NEXT:    dsll $1, $1, 16
-; N64-NEXT:    daddiu $2, $zero, %lo(memset)
-; N64-NEXT:    daddu $25, $1, $2
+; N64-NEXT:    daddiu $25, $1, %lo(memset)
 ; N64-NEXT:    lui $1, %highest(val)
 ; N64-NEXT:    daddiu $1, $1, %higher(val)
 ; N64-NEXT:    dsll $1, $1, 16
 ; N64-NEXT:    daddiu $1, $1, %hi(val)
 ; N64-NEXT:    dsll $1, $1, 16
 ; N64-NEXT:    daddiu $4, $1, %lo(val)
 ; N64-NEXT:    daddiu $5, $zero, 0
 ; N64-NEXT:    jalr.hb $25

llvm/trunk/test/CodeGen/Mips/long-calls.ll

 ; OFF: jal memset
 
 ; Save the `callee` and `memset` addresses in $25 register
 ; and use `jalr` for the jumps.
 ; ON32: lui    $1, %hi(callee)
 ; ON32: addiu  $25, $1, %lo(callee)
 ; ON32: jalr   $25
 
-; ON32: addiu  $1, $zero, %lo(memset)
-; ON32: lui    $2, %hi(memset)
-; ON32: addu   $25, $2, $1
+; ON32: lui    $1, %hi(memset)
+; ON32: addiu  $25, $1, %lo(memset)
 ; ON32: jalr   $25
 
 ; ON64: lui     $1, %highest(callee)
 ; ON64: daddiu  $1, $1, %higher(callee)
 ; ON64: daddiu  $1, $1, %hi(callee)
 ; ON64: daddiu  $25, $1, %lo(callee)
 ; ON64: jalr    $25
 
 ; ON64: daddiu  $1, $zero, %higher(memset)
 ; ON64: lui     $2, %highest(memset)
 ; ON64: lui     $2, %hi(memset)
-; ON64: daddiu  $2, $zero, %lo(memset)
-; ON64: daddu   $25, $1, $2
+; ON64: daddiu  $25, $1, %lo(memset)
 ; ON64: jalr    $25
 
   call void @callee()
   call void @llvm.memset.p0i8.i32(i8* align 4 bitcast ([20 x i32]* @val to i8*), i8 0, i32 80, i1 false)
   ret  void
 }