[X86] Remove what little support we had for MPX

[craig.topper]

Summary

-Deprecate -mmpx and -mno-mpx command line options
-Remove CPUID detection of mpx for -march=native
-Remove MPX from all CPUs
-Remove MPX preprocessor define

I've left the "mpx" string in the backend so we don't fail on old IR, but its not connected to anything.

gcc has also deprecated these command line options. https://www.phoronix.com/scan.php?page=news_item&px=GCC-Patch-To-Drop-MPX

[craig.topper]

Update attributes in a couple tests that I forgot to check for

[RKSimon]

I think this needs adding to the draft 10.0 release notes as well.

llvm/lib/Target/X86/X86.td

244 ↗

(On Diff #216912)

Add a note saying this was deprecated at llvm10? We're not great at removing deprecations (AutoUpgrade.....) but we should keep track.

[xbolva00]

llvm/lib/Target/X86/X86InstrMPX.td

16 ↗

(On Diff #216912)

Fix comment?

[craig.topper]

Add to clang and llvm release notes

[RKSimon]

LGTM - please reword the X86InstrMPX.td comment like @xbolva00 suggested

cfe/trunk/docs/ReleaseNotes.rst

 - ...
 
 Deprecated Compiler Flags
 -------------------------
 
 The following options are deprecated and ignored. They will be removed in
 future versions of Clang.
 
+- -mmpx used to enable the __MPX__ preprocessor define for the Intel MPX
+  instructions. There were no MPX intrinsics.
+- -mno-mpx used to disable -mmpx and is the default behavior.
+
 - ...
 
 Modified Compiler Flags
 -----------------------
 
 - ...
 
 New Pragmas in Clang

cfe/trunk/include/clang/Driver/Options.td

 // easier garbage collection.
 def clang_ignored_legacy_options_Group : OptionGroup<"<clang legacy flags>">,
   Group<f_Group>, Flags<[Ignored]>;
 
 // Retired with clang-5.0
 def : Flag<["-"], "fslp-vectorize-aggressive">, Group<clang_ignored_legacy_options_Group>;
 def : Flag<["-"], "fno-slp-vectorize-aggressive">, Group<clang_ignored_legacy_options_Group>;
 
+// Retired with clang-10.0. Previously controlled X86 MPX ISA.
+def mmpx : Flag<["-"], "mmpx">, Group<clang_ignored_legacy_options_Group>;
+def mno_mpx : Flag<["-"], "mno-mpx">, Group<clang_ignored_legacy_options_Group>;
+
 // Group that ignores all gcc optimizations that won't be implemented
 def clang_ignored_gcc_optimization_f_Group : OptionGroup<
   "<clang_ignored_gcc_optimization_f_Group>">, Group<f_Group>, Flags<[Ignored]>;
 
 /////////
 // Options
 
 // The internal option ID must be a valid C++ identifier and results in a

 def mlzcnt : Flag<["-"], "mlzcnt">, Group<m_x86_Features_Group>;
 def mno_lzcnt : Flag<["-"], "mno-lzcnt">, Group<m_x86_Features_Group>;
 def mmovbe : Flag<["-"], "mmovbe">, Group<m_x86_Features_Group>;
 def mno_movbe : Flag<["-"], "mno-movbe">, Group<m_x86_Features_Group>;
 def mmovdiri : Flag<["-"], "mmovdiri">, Group<m_x86_Features_Group>;
 def mno_movdiri : Flag<["-"], "mno-movdiri">, Group<m_x86_Features_Group>;
 def mmovdir64b : Flag<["-"], "mmovdir64b">, Group<m_x86_Features_Group>;
 def mno_movdir64b : Flag<["-"], "mno-movdir64b">, Group<m_x86_Features_Group>;
-def mmpx : Flag<["-"], "mmpx">, Group<m_x86_Features_Group>;
-def mno_mpx : Flag<["-"], "mno-mpx">, Group<m_x86_Features_Group>;
 def mmwaitx : Flag<["-"], "mmwaitx">, Group<m_x86_Features_Group>;
 def mno_mwaitx : Flag<["-"], "mno-mwaitx">, Group<m_x86_Features_Group>;
 def mpku : Flag<["-"], "mpku">, Group<m_x86_Features_Group>;
 def mno_pku : Flag<["-"], "mno-pku">, Group<m_x86_Features_Group>;
 def mpclmul : Flag<["-"], "mpclmul">, Group<m_x86_Features_Group>;
 def mno_pclmul : Flag<["-"], "mno-pclmul">, Group<m_x86_Features_Group>;
 def mpconfig : Flag<["-"], "mpconfig">, Group<m_x86_Features_Group>;
 def mno_pconfig : Flag<["-"], "mno-pconfig">, Group<m_x86_Features_Group>;

cfe/trunk/lib/Basic/Targets/X86.h

class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
   bool HasAVX512BITALG = false;
   bool HasAVX512BW = false;
   bool HasAVX512VL = false;
   bool HasAVX512VBMI = false;
   bool HasAVX512VBMI2 = false;
   bool HasAVX512IFMA = false;
   bool HasAVX512VP2INTERSECT = false;
   bool HasSHA = false;
-  bool HasMPX = false;
   bool HasSHSTK = false;
   bool HasSGX = false;
   bool HasCX8 = false;
   bool HasCX16 = false;
   bool HasFXSR = false;
   bool HasXSAVE = false;
   bool HasXSAVEOPT = false;
   bool HasXSAVEC = false;

cfe/trunk/lib/Basic/Targets/X86.cpp

case CK_Cannonlake:
     setFeatureEnabledImpl(Features, "sha", true);
     LLVM_FALLTHROUGH;
   case CK_SkylakeClient:
     setFeatureEnabledImpl(Features, "sgx", true);
     // SkylakeServer cores inherits all SKL features, except SGX
 SkylakeCommon:
     setFeatureEnabledImpl(Features, "xsavec", true);
     setFeatureEnabledImpl(Features, "xsaves", true);
-    setFeatureEnabledImpl(Features, "mpx", true);
     setFeatureEnabledImpl(Features, "clflushopt", true);
     setFeatureEnabledImpl(Features, "aes", true);
     LLVM_FALLTHROUGH;
   case CK_Broadwell:
     setFeatureEnabledImpl(Features, "rdseed", true);
     setFeatureEnabledImpl(Features, "adx", true);
     setFeatureEnabledImpl(Features, "prfchw", true);
     LLVM_FALLTHROUGH;
SkylakeCommon:
   case CK_Goldmont:
     setFeatureEnabledImpl(Features, "sha", true);
     setFeatureEnabledImpl(Features, "rdseed", true);
     setFeatureEnabledImpl(Features, "xsave", true);
     setFeatureEnabledImpl(Features, "xsaveopt", true);
     setFeatureEnabledImpl(Features, "xsavec", true);
     setFeatureEnabledImpl(Features, "xsaves", true);
     setFeatureEnabledImpl(Features, "clflushopt", true);
-    setFeatureEnabledImpl(Features, "mpx", true);
     setFeatureEnabledImpl(Features, "fsgsbase", true);
     setFeatureEnabledImpl(Features, "aes", true);
     LLVM_FALLTHROUGH;
   case CK_Silvermont:
     setFeatureEnabledImpl(Features, "rdrnd", true);
     setFeatureEnabledImpl(Features, "pclmul", true);
     setFeatureEnabledImpl(Features, "sse4.2", true);
     setFeatureEnabledImpl(Features, "prfchw", true);
for (const auto &Feature : Features) {
     } else if (Feature == "+avx512vbmi2") {
       HasAVX512VBMI2 = true;
     } else if (Feature == "+avx512ifma") {
       HasAVX512IFMA = true;
     } else if (Feature == "+avx512vp2intersect") {
       HasAVX512VP2INTERSECT = true;
     } else if (Feature == "+sha") {
       HasSHA = true;
-    } else if (Feature == "+mpx") {
-      HasMPX = true;
     } else if (Feature == "+shstk") {
       HasSHSTK = true;
     } else if (Feature == "+movbe") {
       HasMOVBE = true;
     } else if (Feature == "+sgx") {
       HasSGX = true;
     } else if (Feature == "+cx8") {
       HasCX8 = true;
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   if (HasPKU)
     Builder.defineMacro("__PKU__");
   if (HasCLFLUSHOPT)
     Builder.defineMacro("__CLFLUSHOPT__");
   if (HasCLWB)
     Builder.defineMacro("__CLWB__");
   if (HasWBNOINVD)
     Builder.defineMacro("__WBNOINVD__");
-  if (HasMPX)
-    Builder.defineMacro("__MPX__");
   if (HasSHSTK)
     Builder.defineMacro("__SHSTK__");
   if (HasSGX)
     Builder.defineMacro("__SGX__");
   if (HasPREFETCHWT1)
     Builder.defineMacro("__PREFETCHWT1__");
   if (HasCLZERO)
     Builder.defineMacro("__CLZERO__");
return llvm::StringSwitch<bool>(Name)
       .Case("gfni", true)
       .Case("invpcid", true)
       .Case("lwp", true)
       .Case("lzcnt", true)
       .Case("mmx", true)
       .Case("movbe", true)
       .Case("movdiri", true)
       .Case("movdir64b", true)
-      .Case("mpx", true)
       .Case("mwaitx", true)
       .Case("pclmul", true)
       .Case("pconfig", true)
       .Case("pku", true)
       .Case("popcnt", true)
       .Case("prefetchwt1", true)
       .Case("prfchw", true)
       .Case("ptwrite", true)
return llvm::StringSwitch<bool>(Feature)
       .Case("lwp", HasLWP)
       .Case("lzcnt", HasLZCNT)
       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
       .Case("mmx", MMX3DNowLevel >= MMX)
       .Case("movbe", HasMOVBE)
       .Case("movdiri", HasMOVDIRI)
       .Case("movdir64b", HasMOVDIR64B)
-      .Case("mpx", HasMPX)
       .Case("mwaitx", HasMWAITX)
       .Case("pclmul", HasPCLMUL)
       .Case("pconfig", HasPCONFIG)
       .Case("pku", HasPKU)
       .Case("popcnt", HasPOPCNT)
       .Case("prefetchwt1", HasPREFETCHWT1)
       .Case("prfchw", HasPRFCHW)
       .Case("ptwrite", HasPTWRITE)

cfe/trunk/test/Driver/x86-target-features.c

 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mmovbe %s -### -o %t.o 2>&1 | FileCheck -check-prefix=MOVBE %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-movbe %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-MOVBE %s
 // MOVBE: "-target-feature" "+movbe"
 // NO-MOVBE: "-target-feature" "-movbe"
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mmpx %s -### -o %t.o 2>&1 | FileCheck -check-prefix=MPX %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-mpx %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-MPX %s
-// MPX: "-target-feature" "+mpx"
-// NO-MPX: "-target-feature" "-mpx"
+// MPX: the flag '-mmpx' has been deprecated and will be ignored
+// NO-MPX: the flag '-mno-mpx' has been deprecated and will be ignored
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mshstk %s -### -o %t.o 2>&1 | FileCheck -check-prefix=CETSS %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-shstk %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-CETSS %s
 // CETSS: "-target-feature" "+shstk"
 // NO-CETSS: "-target-feature" "-shstk"
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -msgx %s -### -o %t.o 2>&1 | FileCheck -check-prefix=SGX %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-sgx %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-SGX %s

cfe/trunk/test/Preprocessor/predefined-arch-macros.c

 // CHECK_SKL_M32: #define __BMI__ 1
 // CHECK_SKL_M32: #define __CLFLUSHOPT__ 1
 // CHECK_SKL_M32: #define __F16C__ 1
 // CHECK_SKL_M32: #define __FMA__ 1
 // CHECK_SKL_M32: #define __INVPCID__ 1
 // CHECK_SKL_M32: #define __LZCNT__ 1
 // CHECK_SKL_M32: #define __MMX__ 1
 // CHECK_SKL_M32: #define __MOVBE__ 1
-// CHECK_SKL_M32: #define __MPX__ 1
 // CHECK_SKL_M32: #define __PCLMUL__ 1
 // CHECK_SKL_M32: #define __POPCNT__ 1
 // CHECK_SKL_M32: #define __PRFCHW__ 1
 // CHECK_SKL_M32: #define __RDRND__ 1
 // CHECK_SKL_M32: #define __RDSEED__ 1
 // CHECK_SKL_M32: #define __SGX__ 1
 // CHECK_SKL_M32: #define __SSE2__ 1
 // CHECK_SKL_M32: #define __SSE3__ 1

 // CHECK_SKL_M64: #define __BMI__ 1
 // CHECK_SKL_M64: #define __CLFLUSHOPT__ 1
 // CHECK_SKL_M64: #define __F16C__ 1
 // CHECK_SKL_M64: #define __FMA__ 1
 // CHECK_SKL_M64: #define __INVPCID__ 1
 // CHECK_SKL_M64: #define __LZCNT__ 1
 // CHECK_SKL_M64: #define __MMX__ 1
 // CHECK_SKL_M64: #define __MOVBE__ 1
-// CHECK_SKL_M64: #define __MPX__ 1
 // CHECK_SKL_M64: #define __PCLMUL__ 1
 // CHECK_SKL_M64: #define __POPCNT__ 1
 // CHECK_SKL_M64: #define __PRFCHW__ 1
 // CHECK_SKL_M64: #define __RDRND__ 1
 // CHECK_SKL_M64: #define __RDSEED__ 1
 // CHECK_SKL_M64: #define __SGX__ 1
 // CHECK_SKL_M64: #define __SSE2_MATH__ 1
 // CHECK_SKL_M64: #define __SSE2__ 1

 // CHECK_SKX_M32: #define __CLFLUSHOPT__ 1
 // CHECK_SKX_M32: #define __CLWB__ 1
 // CHECK_SKX_M32: #define __F16C__ 1
 // CHECK_SKX_M32: #define __FMA__ 1
 // CHECK_SKX_M32: #define __INVPCID__ 1
 // CHECK_SKX_M32: #define __LZCNT__ 1
 // CHECK_SKX_M32: #define __MMX__ 1
 // CHECK_SKX_M32: #define __MOVBE__ 1
-// CHECK_SKX_M32: #define __MPX__ 1
 // CHECK_SKX_M32: #define __PCLMUL__ 1
 // CHECK_SKX_M32: #define __PKU__ 1
 // CHECK_SKX_M32: #define __POPCNT__ 1
 // CHECK_SKX_M32: #define __PRFCHW__ 1
 // CHECK_SKX_M32: #define __RDRND__ 1
 // CHECK_SKX_M32: #define __RDSEED__ 1
 // CHECK_SKX_M32-NOT: #define __SGX__ 1
 // CHECK_SKX_M32: #define __SSE2__ 1

 // CHECK_SKX_M64: #define __CLFLUSHOPT__ 1
 // CHECK_SKX_M64: #define __CLWB__ 1
 // CHECK_SKX_M64: #define __F16C__ 1
 // CHECK_SKX_M64: #define __FMA__ 1
 // CHECK_SKX_M64: #define __INVPCID__ 1
 // CHECK_SKX_M64: #define __LZCNT__ 1
 // CHECK_SKX_M64: #define __MMX__ 1
 // CHECK_SKX_M64: #define __MOVBE__ 1
-// CHECK_SKX_M64: #define __MPX__ 1
 // CHECK_SKX_M64: #define __PCLMUL__ 1
 // CHECK_SKX_M64: #define __PKU__ 1
 // CHECK_SKX_M64: #define __POPCNT__ 1
 // CHECK_SKX_M64: #define __PRFCHW__ 1
 // CHECK_SKX_M64: #define __RDRND__ 1
 // CHECK_SKX_M64: #define __RDSEED__ 1
 // CHECK_SKX_M64-NOT: #define __SGX__ 1
 // CHECK_SKX_M64: #define __SSE2_MATH__ 1

 // CHECK_CLX_M32: #define __CLFLUSHOPT__ 1
 // CHECK_CLX_M32: #define __CLWB__ 1
 // CHECK_CLX_M32: #define __F16C__ 1
 // CHECK_CLX_M32: #define __FMA__ 1
 // CHECK_CLX_M32: #define __INVPCID__ 1
 // CHECK_CLX_M32: #define __LZCNT__ 1
 // CHECK_CLX_M32: #define __MMX__ 1
 // CHECK_CLX_M32: #define __MOVBE__ 1
-// CHECK_CLX_M32: #define __MPX__ 1
 // CHECK_CLX_M32: #define __PCLMUL__ 1
 // CHECK_CLX_M32: #define __PKU__ 1
 // CHECK_CLX_M32: #define __POPCNT__ 1
 // CHECK_CLX_M32: #define __PRFCHW__ 1
 // CHECK_CLX_M32: #define __RDRND__ 1
 // CHECK_CLX_M32: #define __RDSEED__ 1
 // CHECK_CLX_M32-NOT: #define __SGX__ 1
 // CHECK_CLX_M32: #define __SSE2__ 1

 // CHECK_CLX_M64: #define __CLFLUSHOPT__ 1
 // CHECK_CLX_M64: #define __CLWB__ 1
 // CHECK_CLX_M64: #define __F16C__ 1
 // CHECK_CLX_M64: #define __FMA__ 1
 // CHECK_CLX_M64: #define __INVPCID__ 1
 // CHECK_CLX_M64: #define __LZCNT__ 1
 // CHECK_CLX_M64: #define __MMX__ 1
 // CHECK_CLX_M64: #define __MOVBE__ 1
-// CHECK_CLX_M64: #define __MPX__ 1
 // CHECK_CLX_M64: #define __PCLMUL__ 1
 // CHECK_CLX_M64: #define __PKU__ 1
 // CHECK_CLX_M64: #define __POPCNT__ 1
 // CHECK_CLX_M64: #define __PRFCHW__ 1
 // CHECK_CLX_M64: #define __RDRND__ 1
 // CHECK_CLX_M64: #define __RDSEED__ 1
 // CHECK_CLX_M64-NOT: #define __SGX__ 1
 // CHECK_CLX_M64: #define __SSE2_MATH__ 1

 // CHECK_CPX_M32: #define __CLFLUSHOPT__ 1
 // CHECK_CPX_M32: #define __CLWB__ 1
 // CHECK_CPX_M32: #define __F16C__ 1
 // CHECK_CPX_M32: #define __FMA__ 1
 // CHECK_CPX_M32: #define __INVPCID__ 1
 // CHECK_CPX_M32: #define __LZCNT__ 1
 // CHECK_CPX_M32: #define __MMX__ 1
 // CHECK_CPX_M32: #define __MOVBE__ 1
-// CHECK_CPX_M32: #define __MPX__ 1
 // CHECK_CPX_M32: #define __PCLMUL__ 1
 // CHECK_CPX_M32: #define __PKU__ 1
 // CHECK_CPX_M32: #define __POPCNT__ 1
 // CHECK_CPX_M32: #define __PRFCHW__ 1
 // CHECK_CPX_M32: #define __RDRND__ 1
 // CHECK_CPX_M32: #define __RDSEED__ 1
 // CHECK_CPX_M32-NOT: #define __SGX__ 1
 // CHECK_CPX_M32: #define __SSE2__ 1

 // CHECK_CPX_M64: #define __CLFLUSHOPT__ 1
 // CHECK_CPX_M64: #define __CLWB__ 1
 // CHECK_CPX_M64: #define __F16C__ 1
 // CHECK_CPX_M64: #define __FMA__ 1
 // CHECK_CPX_M64: #define __INVPCID__ 1
 // CHECK_CPX_M64: #define __LZCNT__ 1
 // CHECK_CPX_M64: #define __MMX__ 1
 // CHECK_CPX_M64: #define __MOVBE__ 1
-// CHECK_CPX_M64: #define __MPX__ 1
 // CHECK_CPX_M64: #define __PCLMUL__ 1
 // CHECK_CPX_M64: #define __PKU__ 1
 // CHECK_CPX_M64: #define __POPCNT__ 1
 // CHECK_CPX_M64: #define __PRFCHW__ 1
 // CHECK_CPX_M64: #define __RDRND__ 1
 // CHECK_CPX_M64: #define __RDSEED__ 1
 // CHECK_CPX_M64-NOT: #define __SGX__ 1
 // CHECK_CPX_M64: #define __SSE2_MATH__ 1

 // CHECK_CNL_M32: #define __CLFLUSHOPT__ 1
 // CHECK_CNL_M32-NOT: #define __CLWB__ 1
 // CHECK_CNL_M32: #define __F16C__ 1
 // CHECK_CNL_M32: #define __FMA__ 1
 // CHECK_CNL_M32: #define __INVPCID__ 1
 // CHECK_CNL_M32: #define __LZCNT__ 1
 // CHECK_CNL_M32: #define __MMX__ 1
 // CHECK_CNL_M32: #define __MOVBE__ 1
-// CHECK_CNL_M32: #define __MPX__ 1
 // CHECK_CNL_M32: #define __PCLMUL__ 1
 // CHECK_CNL_M32: #define __PKU__ 1
 // CHECK_CNL_M32: #define __POPCNT__ 1
 // CHECK_CNL_M32: #define __PRFCHW__ 1
 // CHECK_CNL_M32: #define __RDRND__ 1
 // CHECK_CNL_M32: #define __RDSEED__ 1
 // CHECK_CNL_M32: #define __SGX__ 1
 // CHECK_CNL_M32: #define __SHA__ 1

 // CHECK_CNL_M64: #define __CLFLUSHOPT__ 1
 // CHECK_CNL_M64-NOT: #define __CLWB__ 1
 // CHECK_CNL_M64: #define __F16C__ 1
 // CHECK_CNL_M64: #define __FMA__ 1
 // CHECK_CNL_M64: #define __INVPCID__ 1
 // CHECK_CNL_M64: #define __LZCNT__ 1
 // CHECK_CNL_M64: #define __MMX__ 1
 // CHECK_CNL_M64: #define __MOVBE__ 1
-// CHECK_CNL_M64: #define __MPX__ 1
 // CHECK_CNL_M64: #define __PCLMUL__ 1
 // CHECK_CNL_M64: #define __PKU__ 1
 // CHECK_CNL_M64: #define __POPCNT__ 1
 // CHECK_CNL_M64: #define __PRFCHW__ 1
 // CHECK_CNL_M64: #define __RDRND__ 1
 // CHECK_CNL_M64: #define __RDSEED__ 1
 // CHECK_CNL_M64: #define __SGX__ 1
 // CHECK_CNL_M64: #define __SHA__ 1

 // CHECK_ICL_M32: #define __CLWB__ 1
 // CHECK_ICL_M32: #define __F16C__ 1
 // CHECK_ICL_M32: #define __FMA__ 1
 // CHECK_ICL_M32: #define __GFNI__ 1
 // CHECK_ICL_M32: #define __INVPCID__ 1
 // CHECK_ICL_M32: #define __LZCNT__ 1
 // CHECK_ICL_M32: #define __MMX__ 1
 // CHECK_ICL_M32: #define __MOVBE__ 1
-// CHECK_ICL_M32: #define __MPX__ 1
 // CHECK_ICL_M32: #define __PCLMUL__ 1
 // CHECK_ICL_M32: #define __PKU__ 1
 // CHECK_ICL_M32: #define __POPCNT__ 1
 // CHECK_ICL_M32: #define __PRFCHW__ 1
 // CHECK_ICL_M32: #define __RDPID__ 1
 // CHECK_ICL_M32: #define __RDRND__ 1
 // CHECK_ICL_M32: #define __RDSEED__ 1
 // CHECK_ICL_M32: #define __SGX__ 1

 // CHECK_ICL_M64: #define __CLWB__ 1
 // CHECK_ICL_M64: #define __F16C__ 1
 // CHECK_ICL_M64: #define __FMA__ 1
 // CHECK_ICL_M64: #define __GFNI__ 1
 // CHECK_ICL_M64: #define __INVPCID__ 1
 // CHECK_ICL_M64: #define __LZCNT__ 1
 // CHECK_ICL_M64: #define __MMX__ 1
 // CHECK_ICL_M64: #define __MOVBE__ 1
-// CHECK_ICL_M64: #define __MPX__ 1
 // CHECK_ICL_M64: #define __PCLMUL__ 1
 // CHECK_ICL_M64: #define __PKU__ 1
 // CHECK_ICL_M64: #define __POPCNT__ 1
 // CHECK_ICL_M64: #define __PRFCHW__ 1
 // CHECK_ICL_M64: #define __RDPID__ 1
 // CHECK_ICL_M64: #define __RDRND__ 1
 // CHECK_ICL_M64: #define __RDSEED__ 1
 // CHECK_ICL_M64: #define __SGX__ 1

 // CHECK_ICX_M32: #define __CLWB__ 1
 // CHECK_ICX_M32: #define __F16C__ 1
 // CHECK_ICX_M32: #define __FMA__ 1
 // CHECK_ICX_M32: #define __GFNI__ 1
 // CHECK_ICX_M32: #define __INVPCID__ 1
 // CHECK_ICX_M32: #define __LZCNT__ 1
 // CHECK_ICX_M32: #define __MMX__ 1
 // CHECK_ICX_M32: #define __MOVBE__ 1
-// CHECK_ICX_M32: #define __MPX__ 1
 // CHECK_ICX_M32: #define __PCLMUL__ 1
 // CHECK_ICX_M32: #define __PCONFIG__ 1
 // CHECK_ICX_M32: #define __PKU__ 1
 // CHECK_ICX_M32: #define __POPCNT__ 1
 // CHECK_ICX_M32: #define __PRFCHW__ 1
 // CHECK_ICX_M32: #define __RDPID__ 1
 // CHECK_ICX_M32: #define __RDRND__ 1
 // CHECK_ICX_M32: #define __RDSEED__ 1

 // CHECK_ICX_M64: #define __CLWB__ 1
 // CHECK_ICX_M64: #define __F16C__ 1
 // CHECK_ICX_M64: #define __FMA__ 1
 // CHECK_ICX_M64: #define __GFNI__ 1
 // CHECK_ICX_M64: #define __INVPCID__ 1
 // CHECK_ICX_M64: #define __LZCNT__ 1
 // CHECK_ICX_M64: #define __MMX__ 1
 // CHECK_ICX_M64: #define __MOVBE__ 1
-// CHECK_ICX_M64: #define __MPX__ 1
 // CHECK_ICX_M64: #define __PCLMUL__ 1
 // CHECK_ICX_M64: #define __PCONFIG__ 1
 // CHECK_ICX_M64: #define __PKU__ 1
 // CHECK_ICX_M64: #define __POPCNT__ 1
 // CHECK_ICX_M64: #define __PRFCHW__ 1
 // CHECK_ICX_M64: #define __RDPID__ 1
 // CHECK_ICX_M64: #define __RDRND__ 1
 // CHECK_ICX_M64: #define __RDSEED__ 1

 // CHECK_TGL_M32: #define __FMA__ 1
 // CHECK_TGL_M32: #define __GFNI__ 1
 // CHECK_TGL_M32: #define __INVPCID__ 1
 // CHECK_TGL_M32: #define __LZCNT__ 1
 // CHECK_TGL_M32: #define __MMX__ 1
 // CHECK_TGL_M32: #define __MOVBE__ 1
 // CHECK_TGL_M32: #define __MOVDIR64B__ 1
 // CHECK_TGL_M32: #define __MOVDIRI__ 1
-// CHECK_TGL_M32: #define __MPX__ 1
 // CHECK_TGL_M32: #define __PCLMUL__ 1
 // CHECK_TGL_M32-NOT: #define __PCONFIG__ 1
 // CHECK_TGL_M32: #define __PKU__ 1
 // CHECK_TGL_M32: #define __POPCNT__ 1
 // CHECK_TGL_M32: #define __PRFCHW__ 1
 // CHECK_TGL_M32: #define __RDPID__ 1
 // CHECK_TGL_M32: #define __RDRND__ 1
 // CHECK_TGL_M32: #define __RDSEED__ 1

 // CHECK_TGL_M64: #define __FMA__ 1
 // CHECK_TGL_M64: #define __GFNI__ 1
 // CHECK_TGL_M64: #define __INVPCID__ 1
 // CHECK_TGL_M64: #define __LZCNT__ 1
 // CHECK_TGL_M64: #define __MMX__ 1
 // CHECK_TGL_M64: #define __MOVBE__ 1
 // CHECK_TGL_M64: #define __MOVDIR64B__ 1
 // CHECK_TGL_M64: #define __MOVDIRI__ 1
-// CHECK_TGL_M64: #define __MPX__ 1
 // CHECK_TGL_M64: #define __PCLMUL__ 1
 // CHECK_TGL_M64-NOT: #define __PCONFIG__ 1
 // CHECK_TGL_M64: #define __PKU__ 1
 // CHECK_TGL_M64: #define __POPCNT__ 1
 // CHECK_TGL_M64: #define __PRFCHW__ 1
 // CHECK_TGL_M64: #define __RDPID__ 1
 // CHECK_TGL_M64: #define __RDRND__ 1
 // CHECK_TGL_M64: #define __RDSEED__ 1

 // RUN:     -target i386-unknown-linux \
 // RUN:   | FileCheck %s -check-prefix=CHECK_GLM_M32
 // CHECK_GLM_M32: #define __AES__ 1
 // CHECK_GLM_M32: #define __CLFLUSHOPT__ 1
 // CHECK_GLM_M32: #define __FSGSBASE__ 1
 // CHECK_GLM_M32: #define __FXSR__ 1
 // CHECK_GLM_M32: #define __MMX__ 1
 // CHECK_GLM_M32: #define __MOVBE__ 1
-// CHECK_GLM_M32: #define __MPX__ 1
 // CHECK_GLM_M32: #define __PCLMUL__ 1
 // CHECK_GLM_M32: #define __POPCNT__ 1
 // CHECK_GLM_M32: #define __PRFCHW__ 1
 // CHECK_GLM_M32: #define __RDRND__ 1
 // CHECK_GLM_M32: #define __RDSEED__ 1
 // CHECK_GLM_M32: #define __SHA__ 1
 // CHECK_GLM_M32: #define __SSE2__ 1
 // CHECK_GLM_M32: #define __SSE3__ 1

 // RUN:     -target i386-unknown-linux \
 // RUN:   | FileCheck %s -check-prefix=CHECK_GLM_M64
 // CHECK_GLM_M64: #define __AES__ 1
 // CHECK_GLM_M64: #define __CLFLUSHOPT__ 1
 // CHECK_GLM_M64: #define __FSGSBASE__ 1
 // CHECK_GLM_M64: #define __FXSR__ 1
 // CHECK_GLM_M64: #define __MMX__ 1
 // CHECK_GLM_M64: #define __MOVBE__ 1
-// CHECK_GLM_M64: #define __MPX__ 1
 // CHECK_GLM_M64: #define __PCLMUL__ 1
 // CHECK_GLM_M64: #define __POPCNT__ 1
 // CHECK_GLM_M64: #define __PRFCHW__ 1
 // CHECK_GLM_M64: #define __RDRND__ 1
 // CHECK_GLM_M64: #define __RDSEED__ 1
 // CHECK_GLM_M64: #define __SHA__ 1
 // CHECK_GLM_M64: #define __SSE2__ 1
 // CHECK_GLM_M64: #define __SSE3__ 1

 // RUN:     -target i386-unknown-linux \
 // RUN:   | FileCheck %s -check-prefix=CHECK_GLMP_M32
 // CHECK_GLMP_M32: #define __AES__ 1
 // CHECK_GLMP_M32: #define __CLFLUSHOPT__ 1
 // CHECK_GLMP_M32: #define __FSGSBASE__ 1
 // CHECK_GLMP_M32: #define __FXSR__ 1
 // CHECK_GLMP_M32: #define __MMX__ 1
 // CHECK_GLMP_M32: #define __MOVBE__ 1
-// CHECK_GLMP_M32: #define __MPX__ 1
 // CHECK_GLMP_M32: #define __PCLMUL__ 1
 // CHECK_GLMP_M32: #define __POPCNT__ 1
 // CHECK_GLMP_M32: #define __PRFCHW__ 1
 // CHECK_GLMP_M32: #define __PTWRITE__ 1
 // CHECK_GLMP_M32: #define __RDPID__ 1
 // CHECK_GLMP_M32: #define __RDRND__ 1
 // CHECK_GLMP_M32: #define __RDSEED__ 1
 // CHECK_GLMP_M32: #define __SGX__ 1

 // RUN:     -target i386-unknown-linux \
 // RUN:   | FileCheck %s -check-prefix=CHECK_GLMP_M64
 // CHECK_GLMP_M64: #define __AES__ 1
 // CHECK_GLMP_M64: #define __CLFLUSHOPT__ 1
 // CHECK_GLMP_M64: #define __FSGSBASE__ 1
 // CHECK_GLMP_M64: #define __FXSR__ 1
 // CHECK_GLMP_M64: #define __MMX__ 1
 // CHECK_GLMP_M64: #define __MOVBE__ 1
-// CHECK_GLMP_M64: #define __MPX__ 1
 // CHECK_GLMP_M64: #define __PCLMUL__ 1
 // CHECK_GLMP_M64: #define __POPCNT__ 1
 // CHECK_GLMP_M64: #define __PRFCHW__ 1
 // CHECK_GLMP_M64: #define __PTWRITE__ 1
 // CHECK_GLMP_M64: #define __RDPID__ 1
 // CHECK_GLMP_M64: #define __RDRND__ 1
 // CHECK_GLMP_M64: #define __RDSEED__ 1
 // CHECK_GLMP_M64: #define __SGX__ 1

 // CHECK_TRM_M32: #define __CLFLUSHOPT__ 1
 // CHECK_TRM_M32: #define __FSGSBASE__ 1
 // CHECK_TRM_M32: #define __FXSR__ 1
 // CHECK_TRM_M32: #define __GFNI__ 1
 // CHECK_TRM_M32: #define __MMX__ 1
 // CHECK_TRM_M32: #define __MOVBE__ 1
 // CHECK_TRM_M32: #define __MOVDIR64B__ 1
 // CHECK_TRM_M32: #define __MOVDIRI__ 1
-// CHECK_TRM_M32: #define __MPX__ 1
 // CHECK_TRM_M32: #define __PCLMUL__ 1
 // CHECK_TRM_M32: #define __POPCNT__ 1
 // CHECK_TRM_M32: #define __PRFCHW__ 1
 // CHECK_TRM_M32: #define __PTWRITE__ 1
 // CHECK_TRM_M32: #define __RDPID__ 1
 // CHECK_TRM_M32: #define __RDRND__ 1
 // CHECK_TRM_M32: #define __RDSEED__ 1
 // CHECK_TRM_M32: #define __SGX__ 1

 // CHECK_TRM_M64: #define __CLFLUSHOPT__ 1
 // CHECK_TRM_M64: #define __FSGSBASE__ 1
 // CHECK_TRM_M64: #define __FXSR__ 1
 // CHECK_TRM_M64: #define __GFNI__ 1
 // CHECK_TRM_M64: #define __MMX__ 1
 // CHECK_TRM_M64: #define __MOVBE__ 1
 // CHECK_TRM_M64: #define __MOVDIR64B__ 1
 // CHECK_TRM_M64: #define __MOVDIRI__ 1
-// CHECK_TRM_M64: #define __MPX__ 1
 // CHECK_TRM_M64: #define __PCLMUL__ 1
 // CHECK_TRM_M64: #define __POPCNT__ 1
 // CHECK_TRM_M64: #define __PRFCHW__ 1
 // CHECK_TRM_M64: #define __PTWRITE__ 1
 // CHECK_TRM_M64: #define __RDPID__ 1
 // CHECK_TRM_M64: #define __RDRND__ 1
 // CHECK_TRM_M64: #define __RDSEED__ 1
 // CHECK_TRM_M64: #define __SGX__ 1

llvm/trunk/docs/ReleaseNotes.rst

 Changes to the AMDGPU Target
 -----------------------------
 
 Changes to the AVR Target
 -----------------------------
 
  During this release ...
 
+* Deprecated the mpx feature flag for the Intel MPX instructions. There were no
+  intrinsics for this feature. This change only this effects the results
+  returned by getHostCPUFeatures on CPUs that implement the MPX instructions.
+
 Changes to the WebAssembly Target
 ---------------------------------
 
  During this release ...
 
 
 Changes to the OCaml bindings
 -----------------------------

llvm/trunk/lib/Support/Host.cpp

bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
   Features["fsgsbase"]   = HasLeaf7 && ((EBX >>  0) & 1);
   Features["sgx"]        = HasLeaf7 && ((EBX >>  2) & 1);
   Features["bmi"]        = HasLeaf7 && ((EBX >>  3) & 1);
   // AVX2 is only supported if we have the OS save support from AVX.
   Features["avx2"]       = HasLeaf7 && ((EBX >>  5) & 1) && HasAVXSave;
   Features["bmi2"]       = HasLeaf7 && ((EBX >>  8) & 1);
   Features["invpcid"]    = HasLeaf7 && ((EBX >> 10) & 1);
   Features["rtm"]        = HasLeaf7 && ((EBX >> 11) & 1);
-  Features["mpx"]        = HasLeaf7 && ((EBX >> 14) & 1);
   // AVX512 is only supported if the OS supports the context save for it.
   Features["avx512f"]    = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
   Features["avx512dq"]   = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
   Features["rdseed"]     = HasLeaf7 && ((EBX >> 18) & 1);
   Features["adx"]        = HasLeaf7 && ((EBX >> 19) & 1);
   Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
   Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
   Features["clwb"]       = HasLeaf7 && ((EBX >> 24) & 1);

llvm/trunk/lib/Target/X86/X86.td

 def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
                                       "Enable MONITORX/MWAITX timer functionality">;
 def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
                                       "Enable Cache Line Zero">;
 def FeatureCLDEMOTE  : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
                                       "Enable Cache Demote">;
 def FeaturePTWRITE  : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
                                       "Support ptwrite instruction">;
-def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
-                                      "Support MPX instructions">;
+// FIXME: This feature is deprecated in 10.0 and should not be used for
+// anything, but removing it would break IR files that may contain it in a
+// target-feature attribute.
+def FeatureDeprecatedMPX : SubtargetFeature<"mpx", "DeprecatedHasMPX", "false",
+                                      "Deprecated. Support MPX instructions">;
 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
                                      "Use LEA for adjusting the stack pointer">;
 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
                                      "HasSlowDivide32", "true",
                                      "Use 8-bit divide for positive values less than 256">;
 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
                                      "HasSlowDivide64", "true",
                                      "Use 32-bit divide for positive values less than 2^32">;
list<SubtargetFeature> BDWSpecificFeatures = [FeaturePOPCNTFalseDeps,
                                                 FeatureLZCNTFalseDeps];
   list<SubtargetFeature> BDWInheritableFeatures =
     !listconcat(HSWInheritableFeatures, BDWAdditionalFeatures);
   list<SubtargetFeature> BDWFeatures =
     !listconcat(BDWInheritableFeatures, BDWSpecificFeatures);
 
   // Skylake
   list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES,
-                                                  FeatureMPX,
                                                   FeatureXSAVEC,
                                                   FeatureXSAVES,
                                                   FeatureCLFLUSHOPT,
                                                   FeatureFastVectorFSQRT];
   list<SubtargetFeature> SKLSpecificFeatures = [FeatureHasFastGather,
                                                 FeaturePOPCNTFalseDeps,
                                                 FeatureSGX];
   list<SubtargetFeature> SKLInheritableFeatures =
list<SubtargetFeature> SLMSpecificFeatures = [ProcIntelSLM,
                                                 FeaturePOPCNTFalseDeps];
   list<SubtargetFeature> SLMInheritableFeatures =
     !listconcat(AtomInheritableFeatures, SLMAdditionalFeatures);
   list<SubtargetFeature> SLMFeatures =
     !listconcat(SLMInheritableFeatures, SLMSpecificFeatures);
 
   // Goldmont
   list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES,
-                                                  FeatureMPX,
                                                   FeatureSHA,
                                                   FeatureRDSEED,
                                                   FeatureXSAVE,
                                                   FeatureXSAVEOPT,
                                                   FeatureXSAVEC,
                                                   FeatureXSAVES,
                                                   FeatureCLFLUSHOPT,
                                                   FeatureFSGSBase];

llvm/trunk/lib/Target/X86/X86InstrInfo.td

 def HasMWAITX    : Predicate<"Subtarget->hasMWAITX()">;
 def HasCLZERO    : Predicate<"Subtarget->hasCLZERO()">;
 def HasCLDEMOTE  : Predicate<"Subtarget->hasCLDEMOTE()">;
 def HasMOVDIRI   : Predicate<"Subtarget->hasMOVDIRI()">;
 def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">;
 def HasPTWRITE   : Predicate<"Subtarget->hasPTWRITE()">;
 def FPStackf32   : Predicate<"!Subtarget->hasSSE1()">;
 def FPStackf64   : Predicate<"!Subtarget->hasSSE2()">;
-def HasMPX       : Predicate<"Subtarget->hasMPX()">;
 def HasSHSTK     : Predicate<"Subtarget->hasSHSTK()">;
 def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
 def HasCLWB      : Predicate<"Subtarget->hasCLWB()">;
 def HasWBNOINVD  : Predicate<"Subtarget->hasWBNOINVD()">;
 def HasRDPID     : Predicate<"Subtarget->hasRDPID()">;
 def HasWAITPKG   : Predicate<"Subtarget->hasWAITPKG()">;
 def HasINVPCID   : Predicate<"Subtarget->hasINVPCID()">;
 def HasCmpxchg8b : Predicate<"Subtarget->hasCmpxchg8b()">;

llvm/trunk/lib/Target/X86/X86InstrMPX.td

 //===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the X86 MPX instruction set, defining the
 // instructions, and properties of the instructions which are needed for code
 // generation, machine code emission, and analysis.
 //
 //===----------------------------------------------------------------------===//
 
-// FIXME: Investigate a better scheduler class once MPX is used inside LLVM.
+// FIXME: Investigate a better scheduler class if MPX is ever used inside LLVM.
 let SchedRW = [WriteSystem] in {
 
 multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {
   def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
               OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
-              Requires<[HasMPX, Not64BitMode]>;
+              Requires<[Not64BitMode]>;
   def 64rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
               OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
-              Requires<[HasMPX, In64BitMode]>;
+              Requires<[In64BitMode]>;
 }
 
 defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS;
 
 multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> {
   def 32rm: I<opc, MRMSrcMem, (outs), (ins  BNDR:$src1, anymem:$src2),
               OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
-              Requires<[HasMPX, Not64BitMode]>;
+              Requires<[Not64BitMode]>;
   def 64rm: I<opc, MRMSrcMem, (outs), (ins  BNDR:$src1, anymem:$src2),
               OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
-              Requires<[HasMPX, In64BitMode]>;
+              Requires<[In64BitMode]>;
 
   def 32rr: I<opc, MRMSrcReg, (outs), (ins  BNDR:$src1, GR32:$src2),
               OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
-              Requires<[HasMPX, Not64BitMode]>;
+              Requires<[Not64BitMode]>;
   def 64rr: I<opc, MRMSrcReg, (outs), (ins  BNDR:$src1, GR64:$src2),
               OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
-              Requires<[HasMPX, In64BitMode]>;
+              Requires<[In64BitMode]>;
 }
 defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS, NotMemoryFoldable;
 defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD, NotMemoryFoldable;
 defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD, NotMemoryFoldable;
 
 def BNDMOVrr   : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src),
                   "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
-                  Requires<[HasMPX]>, NotMemoryFoldable;
+                  NotMemoryFoldable;
 let mayLoad = 1 in {
 def BNDMOV32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
                   "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
-                  Requires<[HasMPX, Not64BitMode]>, NotMemoryFoldable;
+                  Requires<[Not64BitMode]>, NotMemoryFoldable;
 def BNDMOV64rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src),
                   "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
-                  Requires<[HasMPX, In64BitMode]>, NotMemoryFoldable;
+                  Requires<[In64BitMode]>, NotMemoryFoldable;
 }
 let isCodeGenOnly = 1, ForceDisassemble = 1 in
 def BNDMOVrr_REV   : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src),
                        "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
-                       Requires<[HasMPX]>, NotMemoryFoldable;
+                       NotMemoryFoldable;
 let mayStore = 1 in {
 def BNDMOV32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
                   "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
-                  Requires<[HasMPX, Not64BitMode]>, NotMemoryFoldable;
+                  Requires<[Not64BitMode]>, NotMemoryFoldable;
 def BNDMOV64mr : I<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src),
                   "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
-                  Requires<[HasMPX, In64BitMode]>, NotMemoryFoldable;
+                  Requires<[In64BitMode]>, NotMemoryFoldable;
 
 def BNDSTXmr:      I<0x1B, MRMDestMem, (outs), (ins anymem:$dst, BNDR:$src),
-                    "bndstx\t{$src, $dst|$dst, $src}", []>, PS,
-                    Requires<[HasMPX]>;
+                    "bndstx\t{$src, $dst|$dst, $src}", []>, PS;
 }
 let mayLoad = 1 in
 def BNDLDXrm:      I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
-                    "bndldx\t{$src, $dst|$dst, $src}", []>, PS,
-                    Requires<[HasMPX]>;
+                    "bndldx\t{$src, $dst|$dst, $src}", []>, PS;
 } // SchedRW

llvm/trunk/lib/Target/X86/X86Subtarget.h

protected:
   bool HasENQCMD = false;
 
   /// Processor has AVX-512 Bit Algorithms instructions
   bool HasBITALG = false;
 
   /// Processor has AVX-512 vp2intersect instructions
   bool HasVP2INTERSECT = false;
 
-  /// Processor supports MPX - Memory Protection Extensions
-  bool HasMPX = false;
+  /// Deprecated flag for MPX instructions.
+  bool DeprecatedHasMPX = false;
 
   /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
   /// using Shadow Stack
   bool HasSHSTK = false;
 
   /// Processor supports Invalidate Process-Context Identifier
   bool HasINVPCID = false;
 
public:
   bool hasDQI() const { return HasDQI; }
   bool hasBWI() const { return HasBWI; }
   bool hasVLX() const { return HasVLX; }
   bool hasPKU() const { return HasPKU; }
   bool hasVNNI() const { return HasVNNI; }
   bool hasBF16() const { return HasBF16; }
   bool hasVP2INTERSECT() const { return HasVP2INTERSECT; }
   bool hasBITALG() const { return HasBITALG; }
-  bool hasMPX() const { return HasMPX; }
   bool hasSHSTK() const { return HasSHSTK; }
   bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
   bool hasCLWB() const { return HasCLWB; }
   bool hasWBNOINVD() const { return HasWBNOINVD; }
   bool hasRDPID() const { return HasRDPID; }
   bool hasWAITPKG() const { return HasWAITPKG; }
   bool hasPCONFIG() const { return HasPCONFIG; }
   bool hasSGX() const { return HasSGX; }

llvm/trunk/test/CodeGen/X86/ms-inline-asm-avx512.ll

 
 ; CHECK-LABEL: ignore_fe_size:
 ; CHECK: vaddps  7(%rsp){1to4}, %xmm2, %xmm1
 ; CHECK: vaddps  7(%rsp), %xmm2, %xmm1
 ; CHECK: movl    7(%rsp), %eax
 ; CHECK: movq    %rax, 7(%rsp)
 ; CHECK: retq
 
-attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+mpx,+pclmul,+pku,+popcnt,+rdrnd,+rdseed,+rtm,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+rdrnd,+rdseed,+rtm,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { nounwind }

llvm/trunk/test/CodeGen/X86/vector-width-store-merge.ll

 ; CHECK: vmovups %ymm
   call void @llvm.memmove.p0i8.p0i8.i64(i8* align 1 %dst, i8* align 1 %src, i64 64, i1 false)
   ret void
 }
 
 ; Function Attrs: argmemonly nounwind
 declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1 immarg) #1
 
-attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="128" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+mpx,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="128" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { argmemonly nounwind }
-attributes #2 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="256" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+mpx,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="256" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" }
 
 !0 = !{i32 1, !"wchar_size", i32 4}