AArch64: avoid cycle when forming post-increment NEON loads

[t.p.northover]

Summary

Inserting a value into Visited has the effect of terminating a search for predecessors if that node is seen. This is legitimate for the base address (as used in DAGCombiner.cpp), and acts as a slight performance optimization. But the vector-building node here can be part of a legitimate cycle so we shouldn't stop searching there.

Should fix https://bugs.llvm.org/show_bug.cgi?id=43056.

[efriedma]

LGTM

On a side-note, we really should try to come up with a better algorithm for forming pre/post-increment operations; hasPredecessorHelper is slow.

[t.p.northover]

Thanks Eli. r370036.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
         continue;
       Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
     }
 
     // To avoid cycle construction make sure that neither the load nor the add
     // are predecessors to each other or the Vector.
     SmallPtrSet<const SDNode *, 32> Visited;
     SmallVector<const SDNode *, 16> Worklist;
-    Visited.insert(N);
+    Visited.insert(Addr.getNode());
     Worklist.push_back(User);
     Worklist.push_back(LD);
     Worklist.push_back(Vector.getNode());
     if (SDNode::hasPredecessorHelper(LD, Visited, Worklist) ||
         SDNode::hasPredecessorHelper(User, Visited, Worklist))
       continue;
 
     SmallVector<SDValue, 8> Ops;

llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll

define void  @test_ld1lane_build_i8(i8* %a, i8* %b, i8* %c, i8* %d, i8* %e, i8* %f, i8* %g, i8* %h, <8 x i8> %v, <8 x i8>* %p) {
   %v.e = insertelement <8 x i8> %v.d,  i8 %ld.e, i64 4
   %v.f = insertelement <8 x i8> %v.e,  i8 %ld.f, i64 5
   %v.g = insertelement <8 x i8> %v.f,  i8 %ld.g, i64 6
   %v1 = insertelement <8 x i8> %v.g,  i8 %ld.h, i64 7
   %sub = sub nsw <8 x i8> %v1, %v
   store <8 x i8> %sub, <8 x i8>* %p
   ret void
 }
+
+define <4 x i32> @test_inc_cycle(<4 x i32> %vec, i32* %in) {
+; CHECK-LABEL: test_inc_cycle:
+; CHECK: ld1.s { v0 }[0], [x0]{{$}}
+
+  %elt = load i32, i32* %in
+  %newvec = insertelement <4 x i32> %vec, i32 %elt, i32 0
+
+  ; %inc cannot be %elt directly because we check that the load is only
+  ; used by the insert before trying to form post-inc.
+  %inc.vec = bitcast <4 x i32> %newvec to <2 x i64>
+  %inc = extractelement <2 x i64> %inc.vec, i32 0
+  %newaddr = getelementptr i32, i32* %in, i64 %inc
+  store i32* %newaddr, i32** @var
+
+  ret <4 x i32> %newvec
+}
+
+@var = global i32* null