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Differential D66203

[MIPS GlobalISel] Consider type1 when legalizing shifts after r351882
ClosedPublic

Authored by Petar.Avramovic on Aug 14 2019, 1:52 AM.

Details

Reviewers
atanasyan
petarj
Commits
rG61bf2675b986: [MIPS GlobalISel] Consider type1 when legalizing shifts after r351882
rL369510: [MIPS GlobalISel] Consider type1 when legalizing shifts after r351882
Summary

r351882 allows different type for shift amount then result and value
being shifted. Fix MIPS Legalizer rules to take r351882 into account.

Diff Detail

Event Timeline

Petar.Avramovic created this revision.Aug 14 2019, 1:52 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 14 2019, 1:52 AM
Herald added subscribers: llvm-commits, jrtc27, arichardson and 2 others. · View Herald Transcript
Petar.Avramovic added a parent revision: D66202: [MIPS GlobalISel] NarrowScalar G_TRUNC .Aug 14 2019, 1:52 AM
Petar.Avramovic added a child revision: D66204: [MIPS GlobalISel] NarrowScalar G_ZEXT and G_SEXT.Aug 14 2019, 1:55 AM
atanasyan accepted this revision.Aug 14 2019, 9:00 AM

LGTM

This revision is now accepted and ready to land.Aug 14 2019, 9:00 AM
Closed by commit rL369510: [MIPS GlobalISel] Consider type1 when legalizing shifts after r351882 (authored by Petar.Avramovic). · Explain WhyAug 21 2019, 2:32 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
4 lines
test/
CodeGen/
Mips/
GlobalISel/
legalizer/
37 lines

Diff 215053

lib/Target/Mips/MipsLegalizerInfo.cpp

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
.clampScalar(0, s32, s32); .clampScalar(0, s32, s32);
getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UREM, G_UDIV}) getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UREM, G_UDIV})
.legalFor({s32}) .legalFor({s32})
.minScalar(0, s32) .minScalar(0, s32)
.libcallFor({s64}); .libcallFor({s64});
getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR}) getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
.legalFor({s32, s32}) .legalFor({{s32, s32}})
.minScalar(1, s32); .clampScalar(1, s32, s32);
getActionDefinitionsBuilder(G_ICMP) getActionDefinitionsBuilder(G_ICMP)
.legalForCartesianProduct({s32}, {s32, p0}) .legalForCartesianProduct({s32}, {s32, p0})
.clampScalar(1, s32, s32) .clampScalar(1, s32, s32)
.minScalar(0, s32); .minScalar(0, s32);
getActionDefinitionsBuilder(G_CONSTANT) getActionDefinitionsBuilder(G_CONSTANT)
.legalFor({s32}) .legalFor({s32})
▲ Show 20 Lines • Show All 88 Lines • Show Last 20 Lines

test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir

Show All 14 Lines--- |
define void @xor_i1() {entry: ret void} define void @xor_i1() {entry: ret void}
define void @xor_i8() {entry: ret void} define void @xor_i8() {entry: ret void}
define void @xor_i16() {entry: ret void} define void @xor_i16() {entry: ret void}
define void @xor_i32() {entry: ret void} define void @xor_i32() {entry: ret void}
define void @xor_i64() {entry: ret void} define void @xor_i64() {entry: ret void}
define void @shl(i32) {entry: ret void} define void @shl(i32) {entry: ret void}
define void @ashr(i32) {entry: ret void} define void @ashr(i32) {entry: ret void}
define void @lshr(i32) {entry: ret void} define void @lshr(i32) {entry: ret void}
define void @lshr_i64_shift_amount(i32) {entry: ret void}
define void @shlv(i32, i32) {entry: ret void} define void @shlv(i32, i32) {entry: ret void}
define void @ashrv(i32, i32) {entry: ret void} define void @ashrv(i32, i32) {entry: ret void}
define void @lshrv(i32, i32) {entry: ret void} define void @lshrv(i32, i32) {entry: ret void}
... ...
--- ---
name: and_i1 name: and_i1
alignment: 2 alignment: 2
▲ Show 20 Lines • Show All 415 Lines • ▼ Show 20 Lines
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0 liveins: $a0
; MIPS32-LABEL: name: shl ; MIPS32-LABEL: name: shl
; MIPS32: liveins: $a0 ; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]] ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; MIPS32: $v0 = COPY [[SHL]](s32) ; MIPS32: $v0 = COPY [[SHL]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s32) = G_CONSTANT i32 1 %1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_SHL %0, %1 %2:_(s32) = G_SHL %0, %1
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: ashr name: ashr
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0 liveins: $a0
; MIPS32-LABEL: name: ashr ; MIPS32-LABEL: name: ashr
; MIPS32: liveins: $a0 ; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]] ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s32) = G_CONSTANT i32 1 %1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_ASHR %0, %1 %2:_(s32) = G_ASHR %0, %1
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: lshr name: lshr
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0 liveins: $a0
; MIPS32-LABEL: name: lshr ; MIPS32-LABEL: name: lshr
; MIPS32: liveins: $a0 ; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]] ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; MIPS32: $v0 = COPY [[LSHR]](s32) ; MIPS32: $v0 = COPY [[LSHR]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s32) = G_CONSTANT i32 1 %1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_LSHR %0, %1 %2:_(s32) = G_LSHR %0, %1
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: lshr_i64_shift_amount
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: lshr_i64_shift_amount
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
; MIPS32: $v0 = COPY [[LSHR]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s32) = G_LSHR %0, %1
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: shlv name: shlv
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: shlv ; MIPS32-LABEL: name: shlv
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]] ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; MIPS32: $v0 = COPY [[SHL]](s32) ; MIPS32: $v0 = COPY [[SHL]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1 %1:_(s32) = COPY $a1
%2:_(s32) = G_SHL %0, %1 %2:_(s32) = G_SHL %0, %1
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: ashrv name: ashrv
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: ashrv ; MIPS32-LABEL: name: ashrv
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]] ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1 %1:_(s32) = COPY $a1
%2:_(s32) = G_ASHR %0, %1 %2:_(s32) = G_ASHR %0, %1
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: lshrv name: lshrv
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0, $a1 liveins: $a0, $a1
; MIPS32-LABEL: name: lshrv ; MIPS32-LABEL: name: lshrv
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]] ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
; MIPS32: $v0 = COPY [[LSHR]](s32) ; MIPS32: $v0 = COPY [[LSHR]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1 %1:_(s32) = COPY $a1
%2:_(s32) = G_LSHR %0, %1 %2:_(s32) = G_LSHR %0, %1
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...