[GlobalISel]: Fix lowering of G_SHUFFLE_VECTOR with scalar sources

[aditya_nandakumar]

Summary

We need to handle scalar sources (1 element vector) correctly while lowering.

[arsenm]

LGTM, although I rather dislike that we allow these. Maybe the IRTranslator should be trying to turn these into the equivalent G_BUILD_VECTOR?

[aditya_nandakumar]

In D66171#1627953, @arsenm wrote:

LGTM, although I rather dislike that we allow these. Maybe the IRTranslator should be trying to turn these into the equivalent G_BUILD_VECTOR?

Thanks for the quick review.
I agree that this is messy. Turning it into BUILD_VECTOR seems to be like an optimization for now - but I don't really have a better solution. It's probably worth creating a patch and seeing what others think about it.

[aditya_nandakumar]

368753.

[aemerson]

In D66171#1627953, @arsenm wrote:

LGTM, although I rather dislike that we allow these. Maybe the IRTranslator should be trying to turn these into the equivalent G_BUILD_VECTOR?

+1

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
   return UnableToLegalize;
 }
 
 LegalizerHelper::LegalizeResult
 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
   Register DstReg = MI.getOperand(0).getReg();
   Register Src0Reg = MI.getOperand(1).getReg();
   Register Src1Reg = MI.getOperand(2).getReg();
+  LLT Src0Ty = MRI.getType(Src0Reg);
   LLT DstTy = MRI.getType(DstReg);
   LLT EltTy = DstTy.getElementType();
   int NumElts = DstTy.getNumElements();
   LLT IdxTy = LLT::scalar(32);
 
   const Constant *ShufMask = MI.getOperand(3).getShuffleMask();
 
   SmallVector<int, 32> Mask;
   ShuffleVectorInst::getShuffleMask(ShufMask, Mask);
 
   Register Undef;
   SmallVector<Register, 32> BuildVec;
 
   for (int Idx : Mask) {
     if (Idx < 0) {
       if (!Undef.isValid())
         Undef = MIRBuilder.buildUndef(EltTy).getReg(0);
       BuildVec.push_back(Undef);
       continue;
     }
 
+    if (Src0Ty.isScalar()) {
+      BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
+    } else {
       Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
       int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
       auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
       auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK);
       BuildVec.push_back(Extract.getReg(0));
     }
+  }
 
   MIRBuilder.buildBuildVector(DstReg, BuildVec);
   MI.eraseFromParent();
   return Legalized;
 }

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
+name: shufflevector_scalar_src
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: shufflevector_scalar_src
+    ; CHECK: liveins: $vgpr0, $vgpr1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = COPY $vgpr1
+    %2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0, %1, shufflemask(0, 1)
+    $vgpr0_vgpr1 = COPY %2
+
+...
+---
 name: shufflevector_v2s32_0_1
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     ; CHECK-LABEL: name: shufflevector_v2s32_0_1

llvm/test/MachineVerifier/test_g_shuffle_vector.mir

bb.0:
     %19:_(s16) = G_CONSTANT i16 0
 
     ; CHECK: Bad machine code: Source operands must be the same type
     %20:_(<2 x s32>) = G_SHUFFLE_VECTOR %3, %19, shufflemask(1, 0)
 
     ; CHECK: Bad machine code: G_SHUFFLE_VECTOR cannot change element type
     %21:_(s16) = G_SHUFFLE_VECTOR %3, %4, shufflemask(0)
 
+    ; CHECK: Bad machine code: Out of bounds shuffle index
+    %22:_(s32) = G_IMPLICIT_DEF
+    %20:_(<2 x s32>) = G_SHUFFLE_VECTOR %22, %22, shufflemask(0, 2)
+
 ...