[GlobalISel]: Add KnownBits for G_XOR

[aditya_nandakumar]

Summary

Added test + implementation for knownBits for G_XOR.

[dsanders]

LGTM

[aditya_nandakumar]

368648

llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

case TargetOpcode::G_SUB: {
     if (KnownZeroLow == 0)
       break;
     computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
                          Depth + 1);
     KnownZeroLow = std::min(KnownZeroLow, Known2.countMinTrailingZeros());
     Known.Zero.setLowBits(KnownZeroLow);
     break;
   }
+  case TargetOpcode::G_XOR: {
+    computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
+                         Depth + 1);
+    computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
+                         Depth + 1);
+
+    // Output known-0 bits are known if clear or set in both the LHS & RHS.
+    APInt KnownZeroOut = (Known.Zero & Known2.Zero) | (Known.One & Known2.One);
+    // Output known-1 are known to be set if set in only one of the LHS, RHS.
+    Known.One = (Known.Zero & Known2.One) | (Known.One & Known2.Zero);
+    Known.Zero = KnownZeroOut;
+    break;
+  }
   // G_GEP is like G_ADD. FIXME: Is this true for all targets?
   case TargetOpcode::G_GEP:
   case TargetOpcode::G_ADD: {
     // Output known-0 bits are known if clear or set in both the low clear bits
     // common to both LHS & RHS.  For example, 8+(X<<3) is known to have the
     // low 3 bits clear.
     // Output known-0 bits are also known if the top bits of each input are
     // known to be clear. For example, if one input has the top 10 bits clear

llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp

TEST_F(GISelMITest, TestKnownBitsPtrToIntViceVersa) {
   unsigned CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   unsigned SrcReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
   EXPECT_EQ(256u, Res.One.getZExtValue());
   EXPECT_EQ(0xfffffeffu, Res.Zero.getZExtValue());
 }
+TEST_F(GISelMITest, TestKnownBitsXOR) {
+  StringRef MIRString = "  %3:_(s8) = G_CONSTANT i8 4\n"
+                        "  %4:_(s8) = G_CONSTANT i8 7\n"
+                        "  %5:_(s8) = G_XOR %3, %4\n"
+                        "  %6:_(s8) = COPY %5\n";
+  setUp(MIRString);
+  if (!TM)
+    return;
+  unsigned CopyReg = Copies[Copies.size() - 1];
+  MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
+  unsigned SrcReg = FinalCopy->getOperand(1).getReg();
+  GISelKnownBits Info(*MF);
+  KnownBits Res = Info.getKnownBits(SrcReg);
+  EXPECT_EQ(3u, Res.One.getZExtValue());
+  EXPECT_EQ(252u, Res.Zero.getZExtValue());
+}
 
 TEST_F(GISelMITest, TestKnownBits) {
 
   StringRef MIR = "  %3:_(s32) = G_TRUNC %0\n"
                   "  %4:_(s32) = G_TRUNC %1\n"
                   "  %5:_(s32) = G_CONSTANT i32 5\n"
                   "  %6:_(s32) = G_CONSTANT i32 24\n"
                   "  %7:_(s32) = G_CONSTANT i32 28\n"