[MC][PowerPC] Emit R_PPC_UADDR32 and R_PPC64_UADDR64 if r_offset is misaligned

[MaskRay]

Summary

R_PPC_ADDR32 and R_PPC64_ADDR64 may be emitted at misaligned r_offset.
This does not conform to the ABIs.

32-bit psABI says:

word32
Specifies a 32-bit bit-field taking up 4 bytes maintaining 4-byte alignment unless otherwise indicated.

ELFv2 ABI says:

doubleword64 specifies a 64-bit field occupying 8 bytes, the alignment of which is 8 bytes unless otherwise specified.

R_PPC_UADDR32 and R_PPC64_UADDR64 belong to the word32 and doubleword64 classes, respectively.

This patch fixes the problem by teaching ELFWriter::writeRelocations to
emit UADDR if an ADDR has a misaligned r_offset. This cannot be done in
the derived MCELFObjectTargetWriter::getRelocType because r_offset is
not known there.

When objects are linked into executable/DSO:

• If sh_addralign >= 8, an R_PPC64_ADDR64 whose r_offset%8!=0 is guaranteed to have a misaligned address.
• Otherwise, it may have an aligned address if the relocated section is combined with other sections, e.g.

.section .data,"aw",@progbits,unique,0; .align 8; .byte 0
.section .data,"aw",@progbits,unique,1; .space 7; .long a

UADDR are rare: they are caused by initialized data at misaligned
addresses (e.g. attribute((packed))). So we don't necessarily
optimize for them.

This change also simplifies the linker design. Since R_PPC64_ADDR64 will
be guaranteed to be aligned, we can safely emit dynamic R_PPC64_RELATIVE
for R_PPC64_ADDR64 to a non-preemptable symbol in a writable location.
(Currently lld ppc{32,64} and ld.bfd ppc32 can emit misaligned
R_PPC{,64}_RELATIVE. This is not a big problem - kernels (verified with Linux
and FreeBSD) trap handlers will fix misaligned accesses).)

[MaskRay]

Probably not worth the trouble: rL177160 , newer ppc64 processors can do unaligned memory access nearly as efficient as aligned accesses? If that is true, we should not do misaligned ADDR -> UADDR transforms as powerpc64 ld.bfd does (https://sourceware.org/bugzilla/show_bug.cgi?id=24896)

include/llvm/BinaryFormat/ELFRelocs/PowerPC64.def

 #undef R_PPC64_JMP_SLOT
 #undef R_PPC64_RELATIVE
 #undef R_PPC64_REL32
 #undef R_PPC64_ADDR64
 #undef R_PPC64_ADDR16_HIGHER
 #undef R_PPC64_ADDR16_HIGHERA
 #undef R_PPC64_ADDR16_HIGHEST
 #undef R_PPC64_ADDR16_HIGHESTA
+#undef R_PPC64_UADDR64
 #undef R_PPC64_REL64
 #undef R_PPC64_TOC16
 #undef R_PPC64_TOC16_LO
 #undef R_PPC64_TOC16_HI
 #undef R_PPC64_TOC16_HA
 #undef R_PPC64_TOC
 #undef R_PPC64_ADDR16_DS
 #undef R_PPC64_ADDR16_LO_DS

 ELF_RELOC(R_PPC64_JMP_SLOT,             21)
 ELF_RELOC(R_PPC64_RELATIVE,             22)
 ELF_RELOC(R_PPC64_REL32,                26)
 ELF_RELOC(R_PPC64_ADDR64,               38)
 ELF_RELOC(R_PPC64_ADDR16_HIGHER,        39)
 ELF_RELOC(R_PPC64_ADDR16_HIGHERA,       40)
 ELF_RELOC(R_PPC64_ADDR16_HIGHEST,       41)
 ELF_RELOC(R_PPC64_ADDR16_HIGHESTA,      42)
+ELF_RELOC(R_PPC64_UADDR64,              43)
 ELF_RELOC(R_PPC64_REL64,                44)
 ELF_RELOC(R_PPC64_TOC16,                47)
 ELF_RELOC(R_PPC64_TOC16_LO,             48)
 ELF_RELOC(R_PPC64_TOC16_HI,             49)
 ELF_RELOC(R_PPC64_TOC16_HA,             50)
 ELF_RELOC(R_PPC64_TOC,                  51)
 ELF_RELOC(R_PPC64_ADDR16_DS,            56)
 ELF_RELOC(R_PPC64_ADDR16_LO_DS,         57)

lib/MC/ELFObjectWriter.cpp

void ELFWriter::WriteSecHdrEntry(uint32_t Name, uint32_t Type, uint64_t Flags,
   W.write<uint32_t>(Info);        // sh_info
   WriteWord(Alignment); // sh_addralign
   WriteWord(EntrySize); // sh_entsize
 }
 
 void ELFWriter::writeRelocations(const MCAssembler &Asm,
                                        const MCSectionELF &Sec) {
   std::vector<ELFRelocationEntry> &Relocs = OWriter.Relocations[&Sec];
+  unsigned EMachine = OWriter.TargetObjectWriter->getEMachine();
 
   // We record relocations by pushing to the end of a vector. Reverse the vector
   // to get the relocations in the order they were created.
   // In most cases that is not important, but it can be for special sections
   // (.eh_frame) or specific relocations (TLS optimizations on SystemZ).
   std::reverse(Relocs.begin(), Relocs.end());
 
   // Sort the relocation entries. MIPS needs this.
   OWriter.TargetObjectWriter->sortRelocs(Asm, Relocs);
 
   for (unsigned i = 0, e = Relocs.size(); i != e; ++i) {
     const ELFRelocationEntry &Entry = Relocs[e - i - 1];
     unsigned Index = Entry.Symbol ? Entry.Symbol->getIndex() : 0;
 
     if (is64Bit()) {
       write(Entry.Offset);
-      if (OWriter.TargetObjectWriter->getEMachine() == ELF::EM_MIPS) {
+      if (EMachine == ELF::EM_MIPS) {
         write(uint32_t(Index));
 
         write(OWriter.TargetObjectWriter->getRSsym(Entry.Type));
         write(OWriter.TargetObjectWriter->getRType3(Entry.Type));
         write(OWriter.TargetObjectWriter->getRType2(Entry.Type));
         write(OWriter.TargetObjectWriter->getRType(Entry.Type));
       } else {
         struct ELF::Elf64_Rela ERE64;
-        ERE64.setSymbolAndType(Index, Entry.Type);
+        unsigned Type = Entry.Type;
+        if (EMachine == ELF::EM_PPC64 && Type == ELF::R_PPC64_ADDR64 &&
+            Entry.Offset % 8 != 0)
+          Type = ELF::R_PPC64_UADDR64;
+        ERE64.setSymbolAndType(Index, Type);
         write(ERE64.r_info);
       }
       if (hasRelocationAddend())
         write(Entry.Addend);
     } else {
       write(uint32_t(Entry.Offset));
 
       struct ELF::Elf32_Rela ERE32;
-      ERE32.setSymbolAndType(Index, Entry.Type);
+      unsigned Type = Entry.Type;
+      if (EMachine == ELF::EM_PPC && Type == ELF::R_PPC_ADDR32 &&
+          Entry.Offset % 4 != 0)
+        Type = ELF::R_PPC_UADDR32;
+      ERE32.setSymbolAndType(Index, Type);
       write(ERE32.r_info);
 
       if (hasRelocationAddend())
         write(uint32_t(Entry.Addend));
 
-      if (OWriter.TargetObjectWriter->getEMachine() == ELF::EM_MIPS) {
+      if (EMachine == ELF::EM_MIPS) {
         if (uint32_t RType =
                 OWriter.TargetObjectWriter->getRType2(Entry.Type)) {
           write(uint32_t(Entry.Offset));
 
           ERE32.setSymbolAndType(0, RType);
           write(ERE32.r_info);
           write(uint32_t(0));
         }

lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp

case PPC::fixup_ppc_nofixup:
       break;
     case FK_Data_8:
       switch (Modifier) {
       default: llvm_unreachable("Unsupported Modifier");
       case MCSymbolRefExpr::VK_PPC_TOCBASE:
         Type = ELF::R_PPC64_TOC;
         break;
       case MCSymbolRefExpr::VK_None:
+        // R_PPC64_UADDR64 may be emitted if r_offset % 8 != 0.
         Type = ELF::R_PPC64_ADDR64;
         break;
       case MCSymbolRefExpr::VK_PPC_DTPMOD:
         Type = ELF::R_PPC64_DTPMOD64;
         break;
       case MCSymbolRefExpr::VK_TPREL:
         Type = ELF::R_PPC64_TPREL64;
         break;
       case MCSymbolRefExpr::VK_DTPREL:
         Type = ELF::R_PPC64_DTPREL64;
         break;
       }
       break;
     case FK_Data_4:
+      // R_PPC_UADDR32 may be emitted if r_offset % 4 != 0.
       Type = ELF::R_PPC_ADDR32;
       break;
     case FK_Data_2:
       Type = ELF::R_PPC_ADDR16;
       break;
     }
   }
   return Type;

test/MC/PowerPC/ppc32-uaddr.s

+# RUN: llvm-mc -filetype=obj -triple=powerpc %s | llvm-readobj -r | FileCheck %s
+
+# CHECK:      0x1 R_PPC_UADDR32 foo 0x0
+# CHECK-NEXT: 0x5 R_PPC_UADDR32 foo 0x1
+
+.data
+.byte 0
+.long foo
+.long foo+1

test/MC/PowerPC/ppc64-uaddr.s

+# RUN: llvm-mc -filetype=obj -triple=powerpc64 %s | llvm-readobj -r | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=powerpc64le %s | llvm-readobj -r | FileCheck %s
+
+# CHECK:      0x1 R_PPC64_UADDR64 foo 0x0
+# CHECK-NEXT: 0x9 R_PPC64_UADDR64 foo 0x1
+
+.data
+.byte 0
+.quad foo
+.quad foo+1