This is the codegen part of fixing:
https://bugs.llvm.org/show_bug.cgi?id=32939
Even with the optimal/canonical IR that is ideally created by D65954, we would reverse that transform in DAGCombiner and end up with the same asm on AArch64 or x86.
I see 2 options for trying to correct this:
- Limit isNegatibleForFree() by special-casing the fmul pattern (this patch).
- Avoid creating (fmul X, 2.0) in the 1st place by adding a special-case transform to SelectionDAG::getNode() that matches the transform done by DAGCombiner.
This seems like the less intrusive patch, but let me know if there's some other reason to prefer 1 option over the other.