[ARM] Reject CSEL instructions with invalid operands

[miyuki]

Summary

According to the Armv8.1-M manual CSEL, CSINC, CSINV and CSNEG are
"constrained unpredictable" when SP is used as the source register Rn.

The assembler should diagnose this case.

[ostannard]

LGTM

llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

def t2LoopEnd :
   t2PseudoInst<(outs), (ins GPRlr:$elts, brtarget:$target),
   8, IIC_Br, []>, Sched<[WriteBr]>;
 
 } // end isBranch, isTerminator, hasSideEffects
 
 } // end isNotDuplicable
 
 class CS<string iname, bits<4> opcode, list<dag> pattern=[]>
-  : V8_1MI<(outs rGPR:$Rd), (ins GPRwithZR:$Rn, GPRwithZRnosp:$Rm, pred_noal:$fcond),
+  : V8_1MI<(outs rGPR:$Rd), (ins GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rm, pred_noal:$fcond),
            AddrModeNone, NoItinerary, iname, "$Rd, $Rn, $Rm, $fcond", "", pattern> {
   bits<4> Rd;
   bits<4> Rm;
   bits<4> Rn;
   bits<4> fcond;
 
   let Inst{31-20} = 0b111010100101;
   let Inst{19-16} = Rn{3-0};

llvm/trunk/test/MC/ARM/thumbv8.1m.s

 # CHECK-NOLOB: cinv    lr, r2, pl  @ encoding: [0x52,0xea,0x42,0xae]
 csinv   lr, r2, r2, mi
 
 # CHECK: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
 # CHECK-FP: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
 # CHECK-NOLOB: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
 csel r0, r0, r1, eq
 
+// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14
+csel sp, r0, r1, eq
+
+// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
+csel r0, sp, r1, eq
+
+// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
+csinc r0, sp, r1, eq
+
+// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
+csinv r0, sp, r1, eq
+
+// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
+csneg r0, sp, r1, eq
+
+// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
+csel r0, r0, sp, eq
+
 // ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable
 it eq
 csel r0, r0, r1, eq
 
 // ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable
 it eq
 csinc r0, r0, r1, ne
 
 // ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable
 it gt
 csinv r0, r0, r1, ge
 
 // ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable
 it lt
 csneg r0, r0, r1, gt

llvm/trunk/test/MC/Disassembler/ARM/thumbv8.1m.s

 [0x50,0xea,0x01,0x80]
 # CHECK: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
 
 [0x51,0xea,0x02,0x8d]
 # CHECK: csel sp, r1, r2, eq @ encoding: [0x51,0xea,0x02,0x8d]
 # ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
 
 [0x5d,0xea,0x02,0x80]
-# CHECK: csel r0, sp, r2, eq @ encoding: [0x5d,0xea,0x02,0x80]
-# ERROR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
 
 [0x51,0xea,0x0d,0x80]
 # ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
 
 [0x5f,0xea,0x0d,0x83]
 # ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
 
 [0x5d 0xea 0x22 0x9e]
-# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
 
 [0x5d 0xea 0x47 0x9e]
-# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
 
 [0x5d 0xea 0x3c 0xae]
-# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
 
 [0x5d 0xea 0x3a 0xbe]
-# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
 
 [0x5d 0xea 0x7b 0x89]
-# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
 
 [0x5d 0xea 0x1f 0x9e]
-# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
 
 [0x5d 0xea 0x3f 0xae]
-# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
 
 [0x5d 0xea 0xd7 0x9e]
-# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
 
 [0x5d 0xea 0x2f 0xae]
-# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
 
 [0x5d 0xea 0x42 0xae]
-# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
 
 [0x5d 0xea 0x7b 0xbe]
-# ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
+# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
 
 [0x52 0xea 0x22 0x9d]
 # ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
 
 [0x57 0xea 0x47 0x9d]
 # ERROR: [[@LINE-1]]:2: warning: potentially undefined instruction encoding
 
 [0x5c 0xea 0x3c 0xad]