[AMDGPU] Fix high occupancy calculation and print it

[rampitec]

Summary

We had couple places which still return 10 as a maximum
occupancy. Fixed.

Also print comment about occupancy as compiler see it.

[arsenm]

lib/Target/AMDGPU/AMDGPUSubtarget.h

1322

Should just set a field in the constructor rather than introducing a virtual

[rampitec]

lib/Target/AMDGPU/AMDGPUSubtarget.h

1322

That is too early, constructor does not know it yet.
Also look at the other functions of the same family, they are all virtual: getMaxWorkGroupsPerCU, getMinFlatWorkGroupSize, getMaxFlatWorkGroupSize, getMinWavesPerEU, getMaxWavesPerEU(unsigned FlatWorkGroupSize).

[rampitec]

lib/Target/AMDGPU/AMDGPUSubtarget.h

1322

Well, OK, I still can do it. Just overwrite value in GCNSubtarget(). It looks a little weird because I still have to duplicate this function in the GCNSubtarget(), otherwise C++ has problems with name resolve. Either this or we will always have to specify AMDGPUSubtarget:: prefix.

[rampitec]

Added field MaxWavesPerEU instead of virtualizing the function.

[rampitec]

Removed "GCNSubtarget::getMaxWavesPerEU()" in favor of using "AMDGPUSubtarget::getMaxWavesPerEU;"

[arsenm]

LGTM

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

if (isVerbose()) {
     OutStreamer->emitRawComment(
       " NumSGPRsForWavesPerEU: " +
       Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
     OutStreamer->emitRawComment(
       " NumVGPRsForWavesPerEU: " +
       Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
 
     OutStreamer->emitRawComment(
+      " Occupancy: " +
+      Twine(CurrentProgramInfo.Occupancy), false);
+
+    OutStreamer->emitRawComment(
       " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false);
 
     OutStreamer->emitRawComment(
       " COMPUTE_PGM_RSRC2:USER_SGPR: " +
       Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
     OutStreamer->emitRawComment(
       " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
       Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
ProgInfo.ComputePGMRSrc2 =
       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
       S_00B84C_EXCP_EN_MSB(0) |
       // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
       S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
       S_00B84C_EXCP_EN(0);
+
+  ProgInfo.Occupancy = STM.computeOccupancy(MF, ProgInfo.LDSSize,
+                                            ProgInfo.NumSGPRsForWavesPerEU,
+                                            ProgInfo.NumVGPRsForWavesPerEU);
 }
 
 static unsigned getRsrcReg(CallingConv::ID CallConv) {
   switch (CallConv) {
   default: LLVM_FALLTHROUGH;
   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
   case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
   case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;

lib/Target/AMDGPU/AMDGPUSubtarget.h

protected:
   bool HasSDWA;
   bool HasVOP3PInsts;
   bool HasMulI24;
   bool HasMulU24;
   bool HasInv2PiInlineImm;
   bool HasFminFmaxLegacy;
   bool EnablePromoteAlloca;
   bool HasTrigReducedRange;
+  unsigned MaxWavesPerEU;
   int LocalMemorySize;
   unsigned WavefrontSize;
 
 public:
   AMDGPUSubtarget(const Triple &TT);
 
   static const AMDGPUSubtarget &get(const MachineFunction &MF);
   static const AMDGPUSubtarget &get(const TargetMachine &TM,
public:
   /// \returns Maximum number of waves per execution unit supported by the
   /// subtarget and limited by given \p FlatWorkGroupSize.
   virtual unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const  = 0;
 
   /// \returns Minimum number of waves per execution unit supported by the
   /// subtarget.
   virtual unsigned getMinWavesPerEU() const = 0;
 
-  unsigned getMaxWavesPerEU() const { return 10; }
+  /// \returns Maximum number of waves per execution unit supported by the
+  /// subtarget without any kind of limitation.
+  unsigned getMaxWavesPerEU() const { return MaxWavesPerEU; }
 
   /// Creates value range metadata on an workitemid.* inrinsic call or load.
   bool makeLIDRangeMetadata(Instruction *I) const;
 
   /// \returns Number of bytes of arguments that are passed to a shader or
   /// kernel in addition to the explicit ones declared for the function.
   unsigned getImplicitArgNumBytes(const Function &F) const {
     if (isMesaKernel(F))
       return 16;
     return AMDGPU::getIntegerAttribute(F, "amdgpu-implicitarg-num-bytes", 0);
   }
   uint64_t getExplicitKernArgSize(const Function &F,
                                   unsigned &MaxAlign) const;
   unsigned getKernArgSegmentSize(const Function &F,
                                  unsigned &MaxAlign) const;
 
   virtual ~AMDGPUSubtarget() {}
 };
 
 class GCNSubtarget : public AMDGPUGenSubtargetInfo,
                      public AMDGPUSubtarget {
+
+  using AMDGPUSubtarget::getMaxWavesPerEU;
+
 public:
   enum TrapHandlerAbi {
     TrapHandlerAbiNone = 0,
     TrapHandlerAbiHsa = 1
   };
 
   enum TrapID {
     TrapIDHardwareReserved = 0,
public:
   }
 
   /// \returns Maximum number of waves per compute unit supported by the
   /// subtarget and limited by given \p FlatWorkGroupSize.
   unsigned getMaxWavesPerCU(unsigned FlatWorkGroupSize) const {
     return AMDGPU::IsaInfo::getMaxWavesPerCU(this, FlatWorkGroupSize);
   }
 
-  /// \returns Maximum number of waves per execution unit supported by the
-  /// subtarget without any kind of limitation.
-  unsigned getMaxWavesPerEU() const {
-    return AMDGPU::IsaInfo::getMaxWavesPerEU(this);
-  }
-
   /// \returns Number of waves per work group supported by the subtarget and
   /// limited by given \p FlatWorkGroupSize.
   unsigned getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const {
     return AMDGPU::IsaInfo::getWavesPerWorkGroup(this, FlatWorkGroupSize);
   }
 
   // static wrappers
   static bool hasHalfRate64Ops(const TargetSubtargetInfo &STI);
public:
   /// Return the maximum number of waves per SIMD for kernels using \p SGPRs
   /// SGPRs
   unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
 
   /// Return the maximum number of waves per SIMD for kernels using \p VGPRs
   /// VGPRs
   unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const;
 
+  /// Return occupancy for the given function. Used LDS and a number of
+  /// registers if provided.
+  /// Note, occupancy can be affected by the scratch allocation as well, but
+  /// we do not have enough information to compute it.
+  unsigned computeOccupancy(const MachineFunction &MF, unsigned LDSSize = 0,
+                            unsigned NumSGPRs = 0, unsigned NumVGPRs = 0) const;
+
   /// \returns true if the flat_scratch register should be initialized with the
   /// pointer to the wave's scratch memory rather than a size and offset.
   bool flatScratchIsPointer() const {
     return getGeneration() >= AMDGPUSubtarget::GFX9;
   }
 
   /// \returns true if the machine has merged shaders in which s0-s7 are
   /// reserved by the hardware and user SGPRs start at s8
public:
   }
 
   /// \returns Minimum number of waves per execution unit supported by the
   /// subtarget.
   unsigned getMinWavesPerEU() const override {
     return AMDGPU::IsaInfo::getMinWavesPerEU(this);
   }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H

lib/Target/AMDGPU/AMDGPUSubtarget.cpp

AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT) :
   HasSDWA(false),
   HasVOP3PInsts(false),
   HasMulI24(true),
   HasMulU24(true),
   HasInv2PiInlineImm(false),
   HasFminFmaxLegacy(true),
   EnablePromoteAlloca(false),
   HasTrigReducedRange(false),
+  MaxWavesPerEU(10),
   LocalMemorySize(0),
   WavefrontSize(0)
   { }
 
 GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
                            const GCNTargetMachine &TM) :
     AMDGPUGenSubtargetInfo(TT, GPU, FS),
     AMDGPUSubtarget(TT),
GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
     HasNSAtoVMEMBug(false),
     HasOffset3fBug(false),
     HasFlatSegmentOffsetBug(false),
 
     FeatureDisable(false),
     InstrInfo(initializeSubtargetDependencies(TT, GPU, FS)),
     TLInfo(TM, *this),
     FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0) {
+  MaxWavesPerEU = AMDGPU::IsaInfo::getMaxWavesPerEU(this);
   CallLoweringInfo.reset(new AMDGPUCallLowering(*getTargetLowering()));
   Legalizer.reset(new AMDGPULegalizerInfo(*this, TM));
   RegBankInfo.reset(new AMDGPURegisterBankInfo(*getRegisterInfo()));
   InstSelector.reset(new AMDGPUInstructionSelector(
   *this, *static_cast<AMDGPURegisterBankInfo *>(RegBankInfo.get()), TM));
 }
 
 unsigned GCNSubtarget::getConstantBusLimit(unsigned Opcode) const {

 }
 
 bool GCNSubtarget::hasMadF16() const {
   return InstrInfo.pseudoToMCOpcode(AMDGPU::V_MAD_F16) != -1;
 }
 
 unsigned GCNSubtarget::getOccupancyWithNumSGPRs(unsigned SGPRs) const {
   if (getGeneration() >= AMDGPUSubtarget::GFX10)
-    return 10;
+    return getMaxWavesPerEU();
 
   if (getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
     if (SGPRs <= 80)
       return 10;
     if (SGPRs <= 88)
       return 9;
     if (SGPRs <= 100)
       return 8;
if (getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
       return 4; // FLAT_SCRATCH, VCC (in that order).
   }
 
   if (isXNACKEnabled())
     return 4; // XNACK, VCC (in that order).
   return 2; // VCC.
 }
 
+unsigned GCNSubtarget::computeOccupancy(const MachineFunction &MF,
+                                        unsigned LDSSize,
+                                        unsigned NumSGPRs,
+                                        unsigned NumVGPRs) const {
+  unsigned Occupancy =
+    std::min(getMaxWavesPerEU(),
+             getOccupancyWithLocalMemSize(LDSSize, MF.getFunction()));
+  if (NumSGPRs)
+    Occupancy = std::min(Occupancy, getOccupancyWithNumSGPRs(NumSGPRs));
+  if (NumVGPRs)
+    Occupancy = std::min(Occupancy, getOccupancyWithNumVGPRs(NumVGPRs));
+  return Occupancy;
+}
+
 unsigned GCNSubtarget::getMaxNumSGPRs(const MachineFunction &MF) const {
   const Function &F = MF.getFunction();
   const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
 
   // Compute maximum number of SGPRs function can use using default/requested
   // minimum number of waves per execution unit.
   std::pair<unsigned, unsigned> WavesPerEU = MFI.getWavesPerEU();
   unsigned MaxNumSGPRs = getMaxNumSGPRs(WavesPerEU.first, false);

lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

: AMDGPUMachineFunction(MF),
     GITPtrHigh(0xffffffff),
     HighBitsOf32BitAddress(0),
     GDSSize(0) {
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   const Function &F = MF.getFunction();
   FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
   WavesPerEU = ST.getWavesPerEU(F);
 
-  Occupancy = getMaxWavesPerEU();
-  limitOccupancy(MF);
+  Occupancy = ST.computeOccupancy(MF, getLDSSize());
   CallingConv::ID CC = F.getCallingConv();
 
   if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL) {
     if (!F.arg_empty())
       KernargSegmentPtr = true;
     WorkGroupIDX = true;
     WorkItemIDX = true;
   } else if (CC == CallingConv::AMDGPU_PS) {

lib/Target/AMDGPU/SIProgramInfo.h

struct SIProgramInfo {
     bool FlatUsed = false;
 
     // Number of SGPRs that meets number of waves per execution unit request.
     uint32_t NumSGPRsForWavesPerEU = 0;
 
     // Number of VGPRs that meets number of waves per execution unit request.
     uint32_t NumVGPRsForWavesPerEU = 0;
 
+    // Final occupancy.
+    uint32_t Occupancy = 0;
+
     // Whether there is recursion, dynamic allocas, indirect calls or some other
     // reason there may be statically unknown stack usage.
     bool DynamicCallStack = false;
 
     // Bonus information for debugging.
     bool VCCUsed = false;
 
     SIProgramInfo() = default;
 };
 
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H

test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props-v3.ll

entry:
   store i32 %ind, i32 addrspace(1)* %outd
   store i32 %ine, i32 addrspace(1)* %oute
   store i32 %inf, i32 addrspace(1)* %outf
   ret void
 }
 
 ; CHECK:   .name:       num_spilled_vgprs
 ; CHECK:   .symbol:     num_spilled_vgprs.kd
-; GFX700:   .vgpr_spill_count: 14
-; GFX803:   .vgpr_spill_count: 14
-; GFX900:   .vgpr_spill_count: 14
-; GFX1010:  .vgpr_spill_count: 0
+; CHECK:   .vgpr_spill_count: 14
 define amdgpu_kernel void @num_spilled_vgprs() #1 {
   %val0 = load volatile float, float addrspace(1)* @var
   %val1 = load volatile float, float addrspace(1)* @var
   %val2 = load volatile float, float addrspace(1)* @var
   %val3 = load volatile float, float addrspace(1)* @var
   %val4 = load volatile float, float addrspace(1)* @var
   %val5 = load volatile float, float addrspace(1)* @var
   %val6 = load volatile float, float addrspace(1)* @var

test/CodeGen/AMDGPU/nsa-reassign.ll

main_body:
   %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare.1, float %s1.1, float %t1.1, float %r1.1, float %lod.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   %r.0 = insertelement <2 x float> undef, float %v1, i32 0
   %r = insertelement <2 x float> %r.0, float %v2, i32 1
   ret <2 x float> %r
 }
 
 ; GCN-LABEL: {{^}}sample_contig_nsa_10vgprs:
-; GCN-DAG: image_sample_c_l v{{[0-9]+}}, v[{{[0-9:]+}}],
-; GCN-DAG: image_sample v{{[0-9]+}}, v[{{[0-9:]+}}],
+; GCN-DAG: image_sample_c_l v{{[0-9]+}}, [{{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}],
+; GCN-DAG: image_sample v{{[0-9]+}}, [{{v[0-9]+, v[0-9]+, v[0-9]+}}],
 define amdgpu_ps <2 x float> @sample_contig_nsa_10vgprs(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) #0 {
 main_body:
   %zcompare.1 = fadd float %zcompare, 1.0
   %s1.1 = fadd float %s1, 1.0
   %t1.1 = fadd float %t1, 1.0
   %r1.1 = fadd float %r1, 1.0
   %s2.1 = fadd float %s2, 1.0
   %t2.1 = fadd float %t2, 1.0

test/CodeGen/AMDGPU/occupancy-levels.ll

+; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefixes=GCN,GFX9 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1010 < %s | FileCheck --check-prefixes=GCN,GFX1010,GFX1010W32 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefixes=GCN,GFX1010,GFX1010W64 %s
+
+; GCN-LABEL: {{^}}max_occupancy:
+; GFX9:       ; Occupancy: 10
+; GFX1010:    ; Occupancy: 20
+define amdgpu_kernel void @max_occupancy() {
+  ret void
+}
+
+; GCN-LABEL: {{^}}limited_occupancy_3:
+; GFX9:       ; Occupancy: 3
+; GFX1010W64: ; Occupancy: 3
+; GFX1010W32: ; Occupancy: 4
+define amdgpu_kernel void @limited_occupancy_3() #0 {
+  ret void
+}
+
+; GCN-LABEL: {{^}}limited_occupancy_18:
+; GFX9:       ; Occupancy: 10
+; GFX1010:    ; Occupancy: 18
+define amdgpu_kernel void @limited_occupancy_18() #1 {
+  ret void
+}
+
+; GCN-LABEL: {{^}}limited_occupancy_19:
+; GFX9:       ; Occupancy: 10
+; GFX1010:    ; Occupancy: 18
+define amdgpu_kernel void @limited_occupancy_19() #2 {
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_24_vgprs:
+; GFX9:       ; Occupancy: 10
+; GFX1010:    ; Occupancy: 20
+define amdgpu_kernel void @used_24_vgprs() {
+  call void asm sideeffect "", "~{v23}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_28_vgprs:
+; GFX9:       ; Occupancy: 9
+; GFX1010W64: ; Occupancy: 18
+; GFX1010W32: ; Occupancy: 20
+define amdgpu_kernel void @used_28_vgprs() {
+  call void asm sideeffect "", "~{v27}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_32_vgprs:
+; GFX9:       ; Occupancy: 8
+; GFX1010W64: ; Occupancy: 16
+; GFX1010W32: ; Occupancy: 20
+define amdgpu_kernel void @used_32_vgprs() {
+  call void asm sideeffect "", "~{v31}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_36_vgprs:
+; GFX9:       ; Occupancy: 7
+; GFX1010W64: ; Occupancy: 14
+; GFX1010W32: ; Occupancy: 20
+define amdgpu_kernel void @used_36_vgprs() {
+  call void asm sideeffect "", "~{v35}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_40_vgprs:
+; GFX9:       ; Occupancy: 6
+; GFX1010W64: ; Occupancy: 12
+; GFX1010W32: ; Occupancy: 20
+define amdgpu_kernel void @used_40_vgprs() {
+  call void asm sideeffect "", "~{v39}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_44_vgprs:
+; GFX9:       ; Occupancy: 5
+; GFX1010W64: ; Occupancy: 11
+; GFX1010W32: ; Occupancy: 20
+define amdgpu_kernel void @used_44_vgprs() {
+  call void asm sideeffect "", "~{v43}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_48_vgprs:
+; GFX9:       ; Occupancy: 5
+; GFX1010W64: ; Occupancy: 10
+; GFX1010W32: ; Occupancy: 20
+define amdgpu_kernel void @used_48_vgprs() {
+  call void asm sideeffect "", "~{v47}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_56_vgprs:
+; GFX9:       ; Occupancy: 4
+; GFX1010W64: ; Occupancy: 9
+; GFX1010W32: ; Occupancy: 18
+define amdgpu_kernel void @used_56_vgprs() {
+  call void asm sideeffect "", "~{v55}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_64_vgprs:
+; GFX9:       ; Occupancy: 4
+; GFX1010W64: ; Occupancy: 8
+; GFX1010W32: ; Occupancy: 16
+define amdgpu_kernel void @used_64_vgprs() {
+  call void asm sideeffect "", "~{v63}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_72_vgprs:
+; GFX9:       ; Occupancy: 3
+; GFX1010W64: ; Occupancy: 7
+; GFX1010W32: ; Occupancy: 14
+define amdgpu_kernel void @used_72_vgprs() {
+  call void asm sideeffect "", "~{v71}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_80_vgprs:
+; GFX9:       ; Occupancy: 3
+; GFX1010W64: ; Occupancy: 6
+; GFX1010W32: ; Occupancy: 12
+define amdgpu_kernel void @used_80_vgprs() {
+  call void asm sideeffect "", "~{v79}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_84_vgprs:
+; GFX9:       ; Occupancy: 3
+; GFX1010W64: ; Occupancy: 6
+; GFX1010W32: ; Occupancy: 11
+define amdgpu_kernel void @used_84_vgprs() {
+  call void asm sideeffect "", "~{v83}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_88_vgprs:
+; GFX9:       ; Occupancy: 2
+; GFX1010W64: ; Occupancy: 5
+; GFX1010W32: ; Occupancy: 11
+define amdgpu_kernel void @used_88_vgprs() {
+  call void asm sideeffect "", "~{v87}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_96_vgprs:
+; GFX9:       ; Occupancy: 2
+; GFX1010W64: ; Occupancy: 5
+; GFX1010W32: ; Occupancy: 10
+define amdgpu_kernel void @used_96_vgprs() {
+  call void asm sideeffect "", "~{v95}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_100_vgprs:
+; GFX9:       ; Occupancy: 2
+; GFX1010W64: ; Occupancy: 5
+; GFX1010W32: ; Occupancy: 9
+define amdgpu_kernel void @used_100_vgprs() {
+  call void asm sideeffect "", "~{v99}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_112_vgprs:
+; GFX9:       ; Occupancy: 2
+; GFX1010W64: ; Occupancy: 4
+; GFX1010W32: ; Occupancy: 9
+define amdgpu_kernel void @used_112_vgprs() {
+  call void asm sideeffect "", "~{v111}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_128_vgprs:
+; GFX9:       ; Occupancy: 2
+; GFX1010W64: ; Occupancy: 4
+; GFX1010W32: ; Occupancy: 8
+define amdgpu_kernel void @used_128_vgprs() {
+  call void asm sideeffect "", "~{v127}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_144_vgprs:
+; GFX9:       ; Occupancy: 1
+; GFX1010W64: ; Occupancy: 3
+; GFX1010W32: ; Occupancy: 7
+define amdgpu_kernel void @used_144_vgprs() {
+  call void asm sideeffect "", "~{v143}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_168_vgprs:
+; GFX9:       ; Occupancy: 1
+; GFX1010W64: ; Occupancy: 3
+; GFX1010W32: ; Occupancy: 6
+define amdgpu_kernel void @used_168_vgprs() {
+  call void asm sideeffect "", "~{v167}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_200_vgprs:
+; GFX9:       ; Occupancy: 1
+; GFX1010W64: ; Occupancy: 2
+; GFX1010W32: ; Occupancy: 5
+define amdgpu_kernel void @used_200_vgprs() {
+  call void asm sideeffect "", "~{v199}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_256_vgprs:
+; GFX9:       ; Occupancy: 1
+; GFX1010W64: ; Occupancy: 2
+; GFX1010W32: ; Occupancy: 4
+define amdgpu_kernel void @used_256_vgprs() {
+  call void asm sideeffect "", "~{v255}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_80_sgprs:
+; GFX9:       ; Occupancy: 10
+; GFX1010:    ; Occupancy: 20
+define amdgpu_kernel void @used_80_sgprs() {
+  call void asm sideeffect "", "~{s79}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_88_sgprs:
+; GFX9:       ; Occupancy: 9
+; GFX1010:    ; Occupancy: 20
+define amdgpu_kernel void @used_88_sgprs() {
+  call void asm sideeffect "", "~{s87}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_100_sgprs:
+; GFX9:       ; Occupancy: 8
+; GFX1010:    ; Occupancy: 20
+define amdgpu_kernel void @used_100_sgprs() {
+  call void asm sideeffect "", "~{s99}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_101_sgprs:
+; GFX9:       ; Occupancy: 7
+; GFX1010:    ; Occupancy: 20
+define amdgpu_kernel void @used_101_sgprs() {
+  call void asm sideeffect "", "~{s100}" ()
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_lds_6552:
+; GFX9:       ; Occupancy: 10
+; GFX1010:    ; Occupancy: 20
+@lds6552 = internal addrspace(3) global [6552 x i8] undef, align 4
+define amdgpu_kernel void @used_lds_6552() {
+  %p = bitcast [6552 x i8] addrspace(3)* @lds6552 to i8 addrspace(3)*
+  store volatile i8 1, i8 addrspace(3)* %p
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_lds_6556:
+; GFX9:       ; Occupancy: 9
+; GFX1010W64: ; Occupancy: 19
+; GFX1010W32: ; Occupancy: 20
+@lds6556 = internal addrspace(3) global [6556 x i8] undef, align 4
+define amdgpu_kernel void @used_lds_6556() {
+  %p = bitcast [6556 x i8] addrspace(3)* @lds6556 to i8 addrspace(3)*
+  store volatile i8 1, i8 addrspace(3)* %p
+  ret void
+}
+
+; GCN-LABEL: {{^}}used_lds_13112:
+; GFX9:       ; Occupancy: 4
+; GFX1010W64: ; Occupancy: 9
+; GFX1010W32: ; Occupancy: 19
+@lds13112 = internal addrspace(3) global [13112 x i8] undef, align 4
+define amdgpu_kernel void @used_lds_13112() {
+  %p = bitcast [13112 x i8] addrspace(3)* @lds13112 to i8 addrspace(3)*
+  store volatile i8 1, i8 addrspace(3)* %p
+  ret void
+}
+
+attributes #0 = { "amdgpu-waves-per-eu"="2,3" }
+attributes #1 = { "amdgpu-waves-per-eu"="18,18" }
+attributes #2 = { "amdgpu-waves-per-eu"="19,19" }

test/CodeGen/AMDGPU/wave32.ll

main_body:
   %s.8 = fadd float %s.7, %j
   %s.9 = fadd float %s.8, %k
   %s.10 = fadd float %s.9, %l
   ret float %s.10
 }
 
 ; GCN-LABEL: {{^}}test_vgprblocks_w64_attr:
 ; Test that the wave size can be overridden in function attributes and that the block size is correct as a result
-; GFX10DEFWAVE: ; VGPRBlocks: 11
+; GFX10DEFWAVE: ; VGPRBlocks: 2
 define amdgpu_gs float @test_vgprblocks_w64_attr(float %a, float %b, float %c, float %d, float %e,
                                         float %f, float %g, float %h, float %i, float %j, float %k, float %l) #4 {
 main_body:
   %s = fadd float %a, %b
   %s.1 = fadd float %s, %c
   %s.2 = fadd float %s.1, %d
   %s.3 = fadd float %s.2, %e
   %s.4 = fadd float %s.3, %f