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Differential D65398

[ARM] Generate MVE VFMAs
ClosedPublic

Authored by oliverlars on Jul 29 2019, 6:27 AM.

Details

Reviewers
t.p.northover
dmgreen
samparker
SjoerdMeijer
simon_tatham
Summary

Generate MVE VFMAs/VFMSs from fadd/fsub and fmul instructions.

Diff Detail

Event Timeline

oliverlars created this revision.Jul 29 2019, 6:27 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 29 2019, 6:27 AM
Herald added subscribers: hiraditya, kristof.beyls, javed.absar. · View Herald Transcript
dmgreen accepted this revision.Jul 29 2019, 8:02 AM

Looks good to me, with one minor formatting nit.

llvm/lib/Target/ARM/ARMInstrMVE.td
2582

Nit: you line this up a little, based on the brackets. I mean something like:

def : Pat<(v4f32 (fadd (v4f32 MQPR:$src1),
                       (fmul (v4f32 MQPR:$src2),
                             (v4f32 MQPR:$src3)))),
This revision is now accepted and ready to land.Jul 29 2019, 8:02 AM
oliverlars closed this revision.Jul 31 2019, 5:08 AM

rL367408

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
21 lines
test/
CodeGen/
Thumb2/
370 lines

Diff 212161

llvm/lib/Target/ARM/ARMInstrMVE.td

Show First 20 Lines • Show All 2,571 Lines • ▼ Show 20 Lines
def MVE_VFMAf16 : MVE_VADDSUBFMA_fp<"vfma", "f16", 0b1, 0b1, 0b0, 0b0, def MVE_VFMAf16 : MVE_VADDSUBFMA_fp<"vfma", "f16", 0b1, 0b1, 0b0, 0b0,
(ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">; (ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">;
def MVE_VFMSf32 : MVE_VADDSUBFMA_fp<"vfms", "f32", 0b0, 0b1, 0b0, 0b1, def MVE_VFMSf32 : MVE_VADDSUBFMA_fp<"vfms", "f32", 0b0, 0b1, 0b0, 0b1,
(ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">; (ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">;
def MVE_VFMSf16 : MVE_VADDSUBFMA_fp<"vfms", "f16", 0b1, 0b1, 0b0, 0b1, def MVE_VFMSf16 : MVE_VADDSUBFMA_fp<"vfms", "f16", 0b1, 0b1, 0b0, 0b1,
(ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">; (ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">;
let Predicates = [HasMVEFloat, UseFusedMAC] in {
def : Pat<(v8f16 (fadd (v8f16 MQPR:$src1),
(fmul (v8f16 MQPR:$src2),
dmgreenUnsubmitted
Not Done
ReplyInline Actions

Nit: you line this up a little, based on the brackets. I mean something like:

def : Pat<(v4f32 (fadd (v4f32 MQPR:$src1),
                       (fmul (v4f32 MQPR:$src2),
                             (v4f32 MQPR:$src3)))),
dmgreen: Nit: you line this up a little, based on the brackets. I mean something like: ``` def : Pat<…
(v8f16 MQPR:$src3)))),
(v8f16 (MVE_VFMAf16 $src1, $src2, $src3))>;
def : Pat<(v4f32 (fadd (v4f32 MQPR:$src1),
(fmul (v4f32 MQPR:$src2),
(v4f32 MQPR:$src3)))),
(v4f32 (MVE_VFMAf32 $src1, $src2, $src3))>;
def : Pat<(v8f16 (fsub (v8f16 MQPR:$src1),
(fmul (v8f16 MQPR:$src2),
(v8f16 MQPR:$src3)))),
(v8f16 (MVE_VFMSf16 $src1, $src2, $src3))>;
def : Pat<(v4f32 (fsub (v4f32 MQPR:$src1),
(fmul (v4f32 MQPR:$src2),
(v4f32 MQPR:$src3)))),
(v4f32 (MVE_VFMSf32 $src1, $src2, $src3))>;
}
def MVE_VADDf32 : MVE_VADDSUBFMA_fp<"vadd", "f32", 0b0, 0b0, 0b1, 0b0>; def MVE_VADDf32 : MVE_VADDSUBFMA_fp<"vadd", "f32", 0b0, 0b0, 0b1, 0b0>;
def MVE_VADDf16 : MVE_VADDSUBFMA_fp<"vadd", "f16", 0b1, 0b0, 0b1, 0b0>; def MVE_VADDf16 : MVE_VADDSUBFMA_fp<"vadd", "f16", 0b1, 0b0, 0b1, 0b0>;
let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
def : Pat<(v4f32 (fadd (v4f32 MQPR:$val1), (v4f32 MQPR:$val2))), def : Pat<(v4f32 (fadd (v4f32 MQPR:$val1), (v4f32 MQPR:$val2))),
(v4f32 (MVE_VADDf32 (v4f32 MQPR:$val1), (v4f32 MQPR:$val2)))>; (v4f32 (MVE_VADDf32 (v4f32 MQPR:$val1), (v4f32 MQPR:$val2)))>;
def : Pat<(v8f16 (fadd (v8f16 MQPR:$val1), (v8f16 MQPR:$val2))), def : Pat<(v8f16 (fadd (v8f16 MQPR:$val1), (v8f16 MQPR:$val2))),
(v8f16 (MVE_VADDf16 (v8f16 MQPR:$val1), (v8f16 MQPR:$val2)))>; (v8f16 (MVE_VADDf16 (v8f16 MQPR:$val1), (v8f16 MQPR:$val2)))>;
▲ Show 20 Lines • Show All 2,296 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-fmas.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi, -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-FP
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi, -mattr=+mve.fp -fp-contract=fast -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-VMLA
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE
define arm_aapcs_vfpcc <8 x half> @vfma16_v1(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
; CHECK-MVE-FP-LABEL: vfma16_v1:
; CHECK-MVE-FP: @ %bb.0: @ %entry
; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q2
; CHECK-MVE-FP-NEXT: vadd.f16 q0, q0, q1
; CHECK-MVE-FP-NEXT: bx lr
;
; CHECK-MVE-VMLA-LABEL: vfma16_v1:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr
;
; CHECK-MVE-LABEL: vfma16_v1:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
; CHECK-MVE-NEXT: vpush {d8, d9, d10}
; CHECK-MVE-NEXT: vmov.u16 r0, q2[0]
; CHECK-MVE-NEXT: vmov.u16 r1, q1[0]
; CHECK-MVE-NEXT: vmov.u16 r2, q0[0]
; CHECK-MVE-NEXT: vmov s14, r1
; CHECK-MVE-NEXT: vmov s13, r2
; CHECK-MVE-NEXT: vmov.u16 r1, q2[1]
; CHECK-MVE-NEXT: vmov s12, r0
; CHECK-MVE-NEXT: vmov.u16 r2, q1[1]
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmov.u16 r3, q0[1]
; CHECK-MVE-NEXT: vmov r0, s13
; CHECK-MVE-NEXT: vmov s14, r2
; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
; CHECK-MVE-NEXT: vmov s12, r1
; CHECK-MVE-NEXT: vmov s13, r3
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmov s20, r2
; CHECK-MVE-NEXT: vmov r1, s13
; CHECK-MVE-NEXT: vmov.16 q3[0], r0
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: vmov.u16 r0, q2[2]
; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmov s18, r1
; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[3]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[3]
; CHECK-MVE-NEXT: vmov s18, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[3]
; CHECK-MVE-NEXT: vmov s20, r0
; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov s18, r1
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[4]
; CHECK-MVE-NEXT: vmov s20, r2
; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[5]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[5]
; CHECK-MVE-NEXT: vmov s18, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[5]
; CHECK-MVE-NEXT: vmov s20, r0
; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov s18, r1
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[6]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmov s20, r2
; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[7]
; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[7]
; CHECK-MVE-NEXT: vmov s4, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[7]
; CHECK-MVE-NEXT: vmov s0, r0
; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr
entry:
%0 = fmul <8 x half> %src2, %src3
%1 = fadd <8 x half> %src1, %0
ret <8 x half> %1
}
define arm_aapcs_vfpcc <8 x half> @vfma16_v2(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
; CHECK-MVE-FP-LABEL: vfma16_v2:
; CHECK-MVE-FP: @ %bb.0: @ %entry
; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q2
; CHECK-MVE-FP-NEXT: vadd.f16 q0, q1, q0
; CHECK-MVE-FP-NEXT: bx lr
;
; CHECK-MVE-VMLA-LABEL: vfma16_v2:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr
;
; CHECK-MVE-LABEL: vfma16_v2:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
; CHECK-MVE-NEXT: vpush {d8, d9, d10}
; CHECK-MVE-NEXT: vmov.u16 r0, q2[0]
; CHECK-MVE-NEXT: vmov.u16 r1, q1[0]
; CHECK-MVE-NEXT: vmov.u16 r2, q0[0]
; CHECK-MVE-NEXT: vmov s14, r1
; CHECK-MVE-NEXT: vmov s13, r2
; CHECK-MVE-NEXT: vmov.u16 r1, q2[1]
; CHECK-MVE-NEXT: vmov s12, r0
; CHECK-MVE-NEXT: vmov.u16 r2, q1[1]
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmov.u16 r3, q0[1]
; CHECK-MVE-NEXT: vmov r0, s13
; CHECK-MVE-NEXT: vmov s14, r2
; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
; CHECK-MVE-NEXT: vmov s12, r1
; CHECK-MVE-NEXT: vmov s13, r3
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmov s20, r2
; CHECK-MVE-NEXT: vmov r1, s13
; CHECK-MVE-NEXT: vmov.16 q3[0], r0
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: vmov.u16 r0, q2[2]
; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmov s18, r1
; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[3]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[3]
; CHECK-MVE-NEXT: vmov s18, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[3]
; CHECK-MVE-NEXT: vmov s20, r0
; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov s18, r1
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[4]
; CHECK-MVE-NEXT: vmov s20, r2
; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[5]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[5]
; CHECK-MVE-NEXT: vmov s18, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[5]
; CHECK-MVE-NEXT: vmov s20, r0
; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov s18, r1
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[6]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmov s20, r2
; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[7]
; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[7]
; CHECK-MVE-NEXT: vmov s4, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[7]
; CHECK-MVE-NEXT: vmov s0, r0
; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr
entry:
%0 = fmul <8 x half> %src2, %src3
%1 = fadd <8 x half> %0, %src1
ret <8 x half> %1
}
define arm_aapcs_vfpcc <8 x half> @vfms16(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
; CHECK-MVE-FP-LABEL: vfms16:
; CHECK-MVE-FP: @ %bb.0: @ %entry
; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q2
; CHECK-MVE-FP-NEXT: vsub.f16 q0, q0, q1
; CHECK-MVE-FP-NEXT: bx lr
;
; CHECK-MVE-VMLA-LABEL: vfms16:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vfms.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr
;
; CHECK-MVE-LABEL: vfms16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
; CHECK-MVE-NEXT: vpush {d8, d9, d10}
; CHECK-MVE-NEXT: vmov.u16 r0, q2[0]
; CHECK-MVE-NEXT: vmov.u16 r1, q1[0]
; CHECK-MVE-NEXT: vmov.u16 r2, q0[0]
; CHECK-MVE-NEXT: vmov s14, r1
; CHECK-MVE-NEXT: vmov s13, r2
; CHECK-MVE-NEXT: vmov.u16 r1, q2[1]
; CHECK-MVE-NEXT: vmov s12, r0
; CHECK-MVE-NEXT: vmov.u16 r2, q1[1]
; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmov.u16 r3, q0[1]
; CHECK-MVE-NEXT: vmov r0, s13
; CHECK-MVE-NEXT: vmov s14, r2
; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
; CHECK-MVE-NEXT: vmov s12, r1
; CHECK-MVE-NEXT: vmov s13, r3
; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmov s20, r2
; CHECK-MVE-NEXT: vmov r1, s13
; CHECK-MVE-NEXT: vmov.16 q3[0], r0
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: vmov.u16 r0, q2[2]
; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmov s18, r1
; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
; CHECK-MVE-NEXT: vmls.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[3]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[3]
; CHECK-MVE-NEXT: vmov s18, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[3]
; CHECK-MVE-NEXT: vmov s20, r0
; CHECK-MVE-NEXT: vmls.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov s18, r1
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[4]
; CHECK-MVE-NEXT: vmov s20, r2
; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmls.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[5]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[5]
; CHECK-MVE-NEXT: vmov s18, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[5]
; CHECK-MVE-NEXT: vmov s20, r0
; CHECK-MVE-NEXT: vmls.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov s18, r1
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[6]
; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmov s20, r2
; CHECK-MVE-NEXT: vmls.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q2[7]
; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[7]
; CHECK-MVE-NEXT: vmov s4, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[7]
; CHECK-MVE-NEXT: vmov s0, r0
; CHECK-MVE-NEXT: vmls.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr
entry:
%0 = fmul <8 x half> %src2, %src3
%1 = fsub <8 x half> %src1, %0
ret <8 x half> %1
}
define arm_aapcs_vfpcc <4 x float> @vfma32_v1(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
; CHECK-MVE-FP-LABEL: vfma32_v1:
; CHECK-MVE-FP: @ %bb.0: @ %entry
; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, q2
; CHECK-MVE-FP-NEXT: vadd.f32 q0, q0, q1
; CHECK-MVE-FP-NEXT: bx lr
;
; CHECK-MVE-VMLA-LABEL: vfma32_v1:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vfma.f32 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr
;
; CHECK-MVE-LABEL: vfma32_v1:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmla.f32 s3, s7, s11
; CHECK-MVE-NEXT: vmla.f32 s2, s6, s10
; CHECK-MVE-NEXT: vmla.f32 s1, s5, s9
; CHECK-MVE-NEXT: vmla.f32 s0, s4, s8
; CHECK-MVE-NEXT: bx lr
entry:
%0 = fmul <4 x float> %src2, %src3
%1 = fadd <4 x float> %src1, %0
ret <4 x float> %1
}
define arm_aapcs_vfpcc <4 x float> @vfma32_v2(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
; CHECK-MVE-FP-LABEL: vfma32_v2:
; CHECK-MVE-FP: @ %bb.0: @ %entry
; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, q2
; CHECK-MVE-FP-NEXT: vadd.f32 q0, q1, q0
; CHECK-MVE-FP-NEXT: bx lr
;
; CHECK-MVE-VMLA-LABEL: vfma32_v2:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vfma.f32 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr
;
; CHECK-MVE-LABEL: vfma32_v2:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmla.f32 s3, s7, s11
; CHECK-MVE-NEXT: vmla.f32 s2, s6, s10
; CHECK-MVE-NEXT: vmla.f32 s1, s5, s9
; CHECK-MVE-NEXT: vmla.f32 s0, s4, s8
; CHECK-MVE-NEXT: bx lr
entry:
%0 = fmul <4 x float> %src2, %src3
%1 = fadd <4 x float> %0, %src1
ret <4 x float> %1
}
define arm_aapcs_vfpcc <4 x float> @vfms32(<4 x float> %src1, <4 x float> %src2, <4 x float> %src3) {
; CHECK-MVE-FP-LABEL: vfms32:
; CHECK-MVE-FP: @ %bb.0: @ %entry
; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, q2
; CHECK-MVE-FP-NEXT: vsub.f32 q0, q0, q1
; CHECK-MVE-FP-NEXT: bx lr
;
; CHECK-MVE-VMLA-LABEL: vfms32:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vfms.f32 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr
;
; CHECK-MVE-LABEL: vfms32:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmls.f32 s3, s7, s11
; CHECK-MVE-NEXT: vmls.f32 s2, s6, s10
; CHECK-MVE-NEXT: vmls.f32 s1, s5, s9
; CHECK-MVE-NEXT: vmls.f32 s0, s4, s8
; CHECK-MVE-NEXT: bx lr
entry:
%0 = fmul <4 x float> %src2, %src3
%1 = fsub <4 x float> %src1, %0
ret <4 x float> %1
}