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Differential D65316

AMDGPU/SILoadStoreOptimizer: Make some functions const
ClosedPublic

Authored by tstellar on Jul 25 2019, 8:17 PM.

Details

Reviewers
arsenm
pendingchaos
rampitec
Commits
rG7a2958bc20bc: AMDGPU/SILoadStoreOptimizer: Make some functions const
rL367517: AMDGPU/SILoadStoreOptimizer: Make some functions const

Diff Detail

Event Timeline

tstellar created this revision.Jul 25 2019, 8:17 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 25 2019, 8:17 PM
Herald added subscribers: hiraditya, t-tye, tpr and 6 others. · View Herald Transcript
Harbormaster completed remote builds in B35659: Diff 211873.Jul 25 2019, 8:20 PM
rampitec accepted this revision.Jul 25 2019, 8:24 PM

LGTM

This revision is now accepted and ready to land.Jul 25 2019, 8:24 PM
Closed by commit rG7a2958bc20bc: AMDGPU/SILoadStoreOptimizer: Make some functions const (authored by tstellar). · Explain WhyJul 31 2019, 10:40 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
12 lines

Diff 212730

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Linesprivate:
AliasAnalysis *AA = nullptr; AliasAnalysis *AA = nullptr;
bool OptimizeAgain; bool OptimizeAgain;
static bool offsetsCanBeCombined(CombineInfo &CI); static bool offsetsCanBeCombined(CombineInfo &CI);
static bool widthsFit(const GCNSubtarget &STM, const CombineInfo &CI); static bool widthsFit(const GCNSubtarget &STM, const CombineInfo &CI);
static unsigned getNewOpcode(const CombineInfo &CI); static unsigned getNewOpcode(const CombineInfo &CI);
static std::pair<unsigned, unsigned> getSubRegIdxs(const CombineInfo &CI); static std::pair<unsigned, unsigned> getSubRegIdxs(const CombineInfo &CI);
const TargetRegisterClass *getTargetRegisterClass(const CombineInfo &CI); const TargetRegisterClass *getTargetRegisterClass(const CombineInfo &CI);
unsigned getOpcodeWidth(const MachineInstr &MI); unsigned getOpcodeWidth(const MachineInstr &MI) const;
InstClassEnum getInstClass(unsigned Opc); InstClassEnum getInstClass(unsigned Opc) const;
unsigned getRegs(unsigned Opc); unsigned getRegs(unsigned Opc) const;
bool findMatchingInst(CombineInfo &CI); bool findMatchingInst(CombineInfo &CI);
unsigned read2Opcode(unsigned EltSize) const; unsigned read2Opcode(unsigned EltSize) const;
unsigned read2ST64Opcode(unsigned EltSize) const; unsigned read2ST64Opcode(unsigned EltSize) const;
MachineBasicBlock::iterator mergeRead2Pair(CombineInfo &CI); MachineBasicBlock::iterator mergeRead2Pair(CombineInfo &CI);
unsigned write2Opcode(unsigned EltSize) const; unsigned write2Opcode(unsigned EltSize) const;
▲ Show 20 Lines • Show All 210 Lines • ▼ Show 20 Lines default:
return false; return false;
case 2: case 2:
case 4: case 4:
return true; return true;
} }
} }
} }
unsigned SILoadStoreOptimizer::getOpcodeWidth(const MachineInstr &MI) { unsigned SILoadStoreOptimizer::getOpcodeWidth(const MachineInstr &MI) const {
const unsigned Opc = MI.getOpcode(); const unsigned Opc = MI.getOpcode();
if (TII->isMUBUF(MI)) { if (TII->isMUBUF(MI)) {
return AMDGPU::getMUBUFDwords(Opc); return AMDGPU::getMUBUFDwords(Opc);
} }
switch (Opc) { switch (Opc) {
default: default:
return 0; return 0;
case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: case AMDGPU::S_BUFFER_LOAD_DWORD_IMM:
return 1; return 1;
case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM:
return 2; return 2;
case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM:
return 4; return 4;
} }
} }
InstClassEnum SILoadStoreOptimizer::getInstClass(unsigned Opc) { InstClassEnum SILoadStoreOptimizer::getInstClass(unsigned Opc) const {
if (TII->isMUBUF(Opc)) { if (TII->isMUBUF(Opc)) {
const int baseOpcode = AMDGPU::getMUBUFBaseOpcode(Opc); const int baseOpcode = AMDGPU::getMUBUFBaseOpcode(Opc);
// If we couldn't identify the opcode, bail out. // If we couldn't identify the opcode, bail out.
if (baseOpcode == -1) { if (baseOpcode == -1) {
return UNKNOWN; return UNKNOWN;
} }
Show All 34 LinesInstClassEnum SILoadStoreOptimizer::getInstClass(unsigned Opc) const {
case AMDGPU::DS_WRITE_B32: case AMDGPU::DS_WRITE_B32:
case AMDGPU::DS_WRITE_B64: case AMDGPU::DS_WRITE_B64:
case AMDGPU::DS_WRITE_B32_gfx9: case AMDGPU::DS_WRITE_B32_gfx9:
case AMDGPU::DS_WRITE_B64_gfx9: case AMDGPU::DS_WRITE_B64_gfx9:
return DS_WRITE; return DS_WRITE;
} }
} }
unsigned SILoadStoreOptimizer::getRegs(unsigned Opc) { unsigned SILoadStoreOptimizer::getRegs(unsigned Opc) const {
if (TII->isMUBUF(Opc)) { if (TII->isMUBUF(Opc)) {
unsigned result = 0; unsigned result = 0;
if (AMDGPU::getMUBUFHasVAddr(Opc)) { if (AMDGPU::getMUBUFHasVAddr(Opc)) {
result |= VADDR; result |= VADDR;
} }
if (AMDGPU::getMUBUFHasSrsrc(Opc)) { if (AMDGPU::getMUBUFHasSrsrc(Opc)) {
▲ Show 20 Lines • Show All 1,108 Lines • Show Last 20 Lines