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[IPRA][ARM] Disable no-CSR optimisation for ARM
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Authored by ostannard on Jul 18 2019, 3:19 AM.

Details

Summary

This optimisation isn't generally profitable for ARM, because we can
save/restore many registers in the prologue and epilogue using the PUSH
and POP instructions, but mostly use individual LDR/STR instructions for
other spills.

Diff Detail

Repository
rL LLVM

Event Timeline

ostannard created this revision.Jul 18 2019, 3:19 AM
lebedev.ri added inline comments.
llvm/include/llvm/CodeGen/TargetFrameLowering.h
367–369 ↗(On Diff #210521)

Why not just add the enableNoCSROpt() hook instead?
The existing isSafeForNoCSROpt() seems well-defined..

ostannard updated this revision to Diff 210544.Jul 18 2019, 6:23 AM

Split into separate functions for safe/profitable.

dmgreen added inline comments.Aug 1 2019, 9:42 AM
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
814 ↗(On Diff #210544)

This is no longer needed?

ostannard updated this revision to Diff 213003.Aug 2 2019, 2:54 AM
dmgreen accepted this revision.Aug 2 2019, 3:04 AM

Nice. LGTM

This revision is now accepted and ready to land.Aug 2 2019, 3:04 AM
This revision was automatically updated to reflect the committed changes.