AMDGPU/GFX10: Apply the VMEM-to-scalar-write hazard also to writes to EXEC

[nhaehnle]

Summary

Change-Id: I854fbf7d48e937bef9f8f3f5d0c8aeb970652630

[rampitec]

LGTM

[nhaehnle]

Add missing test changes

lib/Target/AMDGPU/GCNHazardRecognizer.cpp

bool GCNHazardRecognizer::fixVMEMtoScalarWriteHazards(MachineInstr *MI) {
 
   auto IsHazardFn = [TRI, MI] (MachineInstr *I) {
     if (!SIInstrInfo::isVMEM(*I) && !SIInstrInfo::isDS(*I) &&
         !SIInstrInfo::isFLAT(*I))
       return false;
 
     for (const MachineOperand &Def : MI->defs()) {
       MachineOperand *Op = I->findRegisterUseOperand(Def.getReg(), false, TRI);
-      if (!Op || (Op->isImplicit() && Op->getReg() == AMDGPU::EXEC))
+      if (!Op)
         continue;
       return true;
     }
     return false;
   };
 
   auto IsExpiredFn = [] (MachineInstr *MI, int) {
     return MI && (SIInstrInfo::isVALU(*MI) ||

test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll

 ; GCN-NEXT:    s_cmp_eq_u32 s1, 0
 ; GCN-NEXT:    s_cbranch_scc0 BB0_2
 ; GCN-NEXT:  ; %bb.1: ; %mid
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0
 ; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GCN-NEXT:    flat_store_dword v[0:1], v0
 ; GCN-NEXT:  BB0_2: ; %bb
+; GCN-NEXT:    v_nop
 ; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0
 ; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GCN-NEXT:    flat_store_dword v[0:1], v0
 ; GCN-NEXT:    s_endpgm
 entry:
   %cond = icmp eq i32 %arg0, 0

test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir

bb.0:
     $sgpr4 = IMPLICIT_DEF
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
     S_WAITCNT 1
     $sgpr0 = S_MOV_B32 0
 ...
 # GCN-LABEL: name: vmem_write_exec_impread
 # GCN:      BUFFER_LOAD_DWORD_OFFEN
+# GCN:      V_NOP
 # GCN-NEXT: S_MOV_B64
 ---
 name:            vmem_write_exec_impread
 body:             |
   bb.0:
     $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
     $sgpr4 = IMPLICIT_DEF
     $vgpr0 = IMPLICIT_DEF
bb.0:
     $sgpr4 = IMPLICIT_DEF
     $vgpr0 = IMPLICIT_DEF
     $sgpr0 = S_MOV_B32 0
 
   bb.1:
     $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
     S_BRANCH %bb.0
 ...
+# GCN-LABEL: name: ds_write_exec
+# GCN:      DS_WRITE_B32_gfx9
+# GCN-NEXT: V_NOP
+# GCN-NEXT: S_MOV_B32
+---
+name:            ds_write_exec
+body:             |
+  bb.0:
+    $vgpr0 = IMPLICIT_DEF
+    $vgpr1 = IMPLICIT_DEF
+    DS_WRITE_B32_gfx9 $vgpr0, $vgpr1, 0, 0, implicit $exec
+    $exec_lo = S_MOV_B32 -1
+...

test/CodeGen/AMDGPU/wave32.ll

 
 ; GCN-LABEL: {{^}}callee_no_stack_with_call:
 ; GCN: s_waitcnt
 ; GCN-NEXT: s_waitcnt_vscnt
 
 ; GFX1064-NEXT: s_or_saveexec_b64 [[COPY_EXEC0:s\[[0-9]+:[0-9]+\]]], -1{{$}}
 ; GFX1032-NEXT: s_or_saveexec_b32 [[COPY_EXEC0:s[0-9]]], -1{{$}}
 ; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-NEXT: v_nop
 ; GFX1064-NEXT: s_mov_b64 exec, [[COPY_EXEC0]]
 ; GFX1032-NEXT: s_mov_b32 exec_lo, [[COPY_EXEC0]]
 
 ; GCN-NEXT: v_writelane_b32 v32, s34, 2
 ; GCN: s_mov_b32 s34, s32
 ; GFX1064: s_add_u32 s32, s32, 0x400
 ; GFX1032: s_add_u32 s32, s32, 0x200
 
 
 ; GCN-DAG: v_writelane_b32 v32, s30, 0
 ; GCN-DAG: v_writelane_b32 v32, s31, 1
 ; GCN: s_swappc_b64
 ; GCN-DAG: v_readlane_b32 s4, v32, 0
 ; GCN-DAG: v_readlane_b32 s5, v32, 1
 
 
 ; GFX1064: s_sub_u32 s32, s32, 0x400
 ; GFX1032: s_sub_u32 s32, s32, 0x200
 ; GCN: v_readlane_b32 s34, v32, 2
 ; GFX1064: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}}
 ; GFX1032: s_or_saveexec_b32 [[COPY_EXEC1:s[0-9]]], -1{{$}}
 ; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-NEXT: v_nop
 ; GFX1064-NEXT: s_mov_b64 exec, [[COPY_EXEC1]]
 ; GFX1032-NEXT: s_mov_b32 exec_lo, [[COPY_EXEC1]]
 ; GCN-NEXT: s_waitcnt vmcnt(0)
 ; GCN-NEXT: s_setpc_b64
 define void @callee_no_stack_with_call() #1 {
   call void @external_void_func_void()
   ret void
 }