[Mips][ABI]The ELF container needs to depend on the ABI rather than the target triple.

[vmedic]

Summary

At the moment Mips back-end is deciding between ELF32/64 output based on target triple. We should instead use ABI which should be passed as -target-abi command line option. This is the patch that has been created on the bases of http://reviews.llvm.org/D6092 and updated to the top of the tree with no functional changes, subscribers added as requested in initial patch. It is still missing the test files, but we'd like to keep it short at the time until the remaining issues are solved. We still looking where would it be the best to initialize and store the ABI info value so that it's accessible from codegen, the integrated assembler, and the disassembler. Also, selectMipsCPU is currently a member of MipsABIInfo class which is not a best logical place for it, but it is placed there to be visible to all calling classes to avoid code multiplication.

[vmedic]

Daniel's comments from original issue(6092):
Thanks for working on this. It's very important that we stop our triples from affecting our targets behaviour (except in so far as they affect default option values).

I'm still going through the patch but there's one big thing I'm concerned about. We seem to be repeating ourselves quite a lot, so far I've counted five classes holding MipsABIInfo objects (one of which is cached from another object), and six places where it is (at least partially) initialized. At the moment, I'm not sure where best initialize and store the value so that it's accessible from codegen, the integrated assembler, and the disassembler. Perhaps we should be arranging for llc/clang/llvm-mc/etc. to pass in the ABI name through a target-independent API?
Rafael, do you have any suggestions?

Also, this patch needs clang-formatting and rebasing to top-of-tree. The rebase is needed because I've committed the MipsABIInfo patch you've built on top of and you seem to have some conflicts with it.

[dsanders]

(Please include the context as described at http://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface).

I'd like to move MipsABIInfo.{cpp,h} in a separate patch if that's ok with you. This will make it easier to see what the changes are made by this patch.

so far I've counted five classes holding MipsABIInfo objects

I've looked into this properly and I believe we can reduce this a bit but not as much as I'd hoped. At the moment this patch initializes a MipsABIInfo object in:

• MipsAsmParser::MipsAsmParser()
• MipsDisassemblerBase::MipsDisassemblerBase()
• MipsAsmBackend::createObjectWriter()
• MipsRegInfoRecord::MipsRegInfoRecord()
• MipsTargetELFStreamer::MipsTargetELFStreamer()
• MipsSubtarget::MipsSubtarget()

MipsAsmParser doesn't really need it's own copy of the MipsABIInfo object. It could access it via the target streamers instead. To do this, we would have to move the initialization from MipsTargetELFStreamer::MipsTargetELFStreamer() into createMCStreamer() and pass it into both MipsTargetELFStreamer and MipsTargetAsmStreamer. Then MipsAsmParser can get the ABI with something like getTargetStreamer().getABI().

MipsRegInfoRecord doesn't really need to know the ABI. It only needs to know whether it should emit the record as part of .MIPS.options or .reginfo. We should therefore pass this information in to the MipsRegInfoRecord constructor (from MipsTargetELFStreamer which in turn got it from createMCStreamer) and remove the MipsABIInfo object.

The single check for N64 inside MipsDisassemblerBase's subclasses is actually wrong. It should be testing for FeatureGP64bit. Once this is fixed, this class won't need to know the ABI.

These refactors (which should be done in separate patches) leave us with these three initializations.

• MipsAsmBackend::createObjectWriter()
• createMCStreamer()
• MipsSubtarget::MipsSubtarget()

I don't think it's possible to eliminate any more than that. With the constructor change as well (see below), the implementation will end up inside the MipsABIInfo constructor so this isn't too bad.

Do you mind doing those refactors before this patch?

lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp

56–66 ↗

(On Diff #16803)

All the uses of MipsABIInfo use the following pattern:

MipsABIInfo ABI; // <- Default constructor reads the TargetABI option
if (!ABI.IsKnown())
  ABI = MipsABIInfo(IsGP64Bit);

sometimes this is split across functions but we never use a MipsABIInfo until we've done the if-statement.

Rather than having two constructors like this, I think it would be best to merge them into one like so:

MipsABIInfo::MipsABIInfo(bool Is64bit) {
  ThisABI = StringSwitch<ABI>(TargetABI.getValue())
    .Cases("32", "o32", ABI::O32)
    .Case("n32", ABI::N32)
    .Cases("64", "n64", ABI::N64)
    .Default(ABI::Unknown);
  if (!IsKnown())
    ThisABI = Is64Bit ? ABI::N64 : ABI::O32;
}

This makes it easy to see that it is impossible to use a partially constructed object.

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

145–155

See comment on MipsABIInfo constructor.

157

We should be testing for properties of the ABI rather than the ABI itself. E.g. ABIInfo.UsesELF64Objects() rather than ABIInfo.IsN64().

The existing places where we test for the ABI need updating to this style but that's for another patch-series.

lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

344–346 ↗

(On Diff #16803)

See comment in MipsABIInfo constructor

lib/Target/Mips/MipsSubtarget.cpp

130–131 ↗

(On Diff #16803)

See comment on MipsABIInfo constructor

lib/Target/Mips/MipsSubtarget.h

48 ↗

(On Diff #16803)

This comment is wrong, it's the selected ABI. Please change it back.

49 ↗

(On Diff #16803)

I don't see a need to rename this member.

lib/Target/Mips/MipsTargetStreamer.h

110–112 ↗

(On Diff #16803)

Indendation should be spaces.

[vmedic]

Patch refactored according to previous comments.

[dsanders]

Thanks for doing those refactors. There's quite a few comments below. Many are nits but there's a couple important ones.

As you mentioned when we spoke off-list, we still need test cases for this. An assembler test that verifies that mips/mips64 triples have no effect on the ELF32/ELF64-ness of the ELF output should do.

include/llvm/MC/MCParser/MCAsmParserExtension.h

68–71 ↗

(On Diff #17632)

This new function isn't needed (deleting it doesn't break the build) and just calls the existing getStreamer() above after doing a dangerous cast.

include/llvm/MC/MCStreamer.h

233–236 ↗

(On Diff #17632)

Deleting this doesn't break the build and that cast is dangerous.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

97–100 ↗

(On Diff #17632)

This does seem to be needed but the cast is dangerous, we need to find another way.

It looks like we're going to have to cache the MipsABIInfo object from the target streamer during the MipsAsmParser constructor. Fortunately, it shouldn't change during execution.

334–335 ↗

(On Diff #17632)

I don't see why this cast is needed.

lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp

50–55 ↗

(On Diff #17632)

You'll need to resolve a conflict with the 'target-abi' option Eric Christopher added in r224492. It's normally accessed through the TargetOptions class.

I tried a couple quick fixes but didn't successfully get 'make check' passing.

56 ↗

(On Diff #17632)

Nit: Variables normally start with a capital

lib/Target/Mips/MCTargetDesc/MipsABIInfo.h

30 ↗

(On Diff #17632)

Nit: Variables normally start with capitals.

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

145–150

This should probably be in MipsABIInfo just to keep it near to MipsABIInfo::selectMipsCPU(). We ought to find a proper home for both at some point.

409

Nit: You've added an unnecessary blank line here

lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp

13

I don't think you need this include.

lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

117–125 ↗

(On Diff #17632)

These will both do the right thing (at the moment) since it only matters for ELF output but I'm not happy with the idea that the ABI can be different between ELF and Assembly output, nor that it can be O32 when we are really doing N32/N64.

lib/Target/Mips/MipsSubtarget.cpp

209 ↗

(On Diff #17632)

Nit: You seem to have added a blank line here. Intentional? The context is missing so I can't tell if it's the end of the file or next to another blank line.

[vmedic]

lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp

50–55 ↗

(On Diff #17632)

It seems to me that the patch does the same thing we do, only it puts the flag info TargetOptions and accesses trough TargetMachine class, while we are putting it into MipsABIInfo class. I'll try to see if we can use their implementation in our code.

[vmedic]

As suggested by Eric, ABI info is taken from MCTargetOptions which is passed to createAsmBackend method. Definitions of these methods for all targets have been extended with this parameter to keep the build sanity. For the Mips target ABI info is extracted to create elf32/64 object file. Also, the way that extracts the target triple information from ELF header is changed for Mips platform. This patch is followed with a necessary change in clang driver.

[echristo]

Let's split this patch into two pieces to make the review easier - part of this patch is ok (#1) and I'd like to chat about #2 :)

1. Passing MCOptions to the backend,
2. Using it in the mips backend

Thanks!

-eric

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h

33

You could probably store just the ABI here and unify the previous 3 class variables with just the triple rather than OSType.

[dsanders]

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h

33

I don't think we should unify those variables. The triple is meaningless except in so far as it implies some default values.

For example, mips-linux-gnu in conjunction with the -mips64r2 option is equivalent to mips64-linux-gnu. Conversely mips64-linux-gnu and -mips32r2 is equivalent to mips-linux-gnu. I think it's better to keep the values separate and stick to initializing them from the options and (when lacking explicit options) the triple.

IsLittle can probably be derived from the triple but only because we have some dubious code to change the triple given to the backend when -EL and -EB are given to clang.

[vmedic]

The previous patch is split into two parts. This one contains changes to all targets and common code. Mips specific part will be moved to a separate patch.

include/llvm/Object/ELFObjectFile.h

   case ELF::EM_HEXAGON:
     return Triple::hexagon;
   case ELF::EM_MIPS:
-    switch (EF.getHeader()->e_ident[ELF::EI_CLASS]) {
-    case ELF::ELFCLASS32:
+    switch (EF.getHeader()->e_flags & ELF::EF_MIPS_ARCH) {
+    case ELF::EF_MIPS_ARCH_32R6:
+    case ELF::EF_MIPS_ARCH_32R2:
+    case ELF::EF_MIPS_ARCH_32:
+    case ELF::EF_MIPS_ARCH_2:
+    case ELF::EF_MIPS_ARCH_1:
       return IsLittleEndian ? Triple::mipsel : Triple::mips;
-    case ELF::ELFCLASS64:
+    case ELF::EF_MIPS_ARCH_64R6:
+    case ELF::EF_MIPS_ARCH_64R2:
+    case ELF::EF_MIPS_ARCH_64:
+    case ELF::EF_MIPS_ARCH_5:
+    case ELF::EF_MIPS_ARCH_4:
+    case ELF::EF_MIPS_ARCH_3:
       return IsLittleEndian ? Triple::mips64el : Triple::mips64;
     default:
-      report_fatal_error("Invalid ELFCLASS!");
+      report_fatal_error("Invalid MIPS ARCH!");
     }
   case ELF::EM_PPC:
     return Triple::ppc;

include/llvm/Support/TargetRegistry.h

     typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T,
                                                 const MCRegisterInfo &MRI,
                                                 StringRef TT,
-                                                StringRef CPU);
+                                                StringRef CPU,
+                                                const MCTargetOptions &Options);
     typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(
         MCSubtargetInfo &STI,
         MCAsmParser &P,

     ///
     /// \param Triple The target triple string.
     MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
-                                     StringRef Triple, StringRef CPU) const {
+                                     StringRef Triple, StringRef CPU,
+                                     const MCTargetOptions &Options) const {
       if (!MCAsmBackendCtorFn)
         return nullptr;
-      return MCAsmBackendCtorFn(*this, MRI, Triple, CPU);
+      return MCAsmBackendCtorFn(*this, MRI, Triple, CPU, Options);
     }
 
     /// createMCAsmParser - Create a target specific assembly parser.

lib/CodeGen/LLVMTargetMachine.cpp

       MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, *Context);
 
     MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
-                                                       TargetCPU);
+                                                       TargetCPU,
+                                                       Options.MCOptions);
     MCStreamer *S = getTarget().createAsmStreamer(
         *Context, Out, Options.MCOptions.AsmVerbose,
         Options.MCOptions.MCUseDwarfDirectory, InstPrinter, MCE, MAB,

     MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, STI,
                                                          *Context);
     MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
-                                                       TargetCPU);
+                                                       TargetCPU,
+                                                       Options.MCOptions);
     if (!MCE || !MAB)
       return true;
 

   MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(
       *getSubtargetImpl()->getInstrInfo(), MRI, STI, *Ctx);
   MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
-                                                     TargetCPU);
+                                                     TargetCPU,
+                                                     Options.MCOptions);
   if (!MCE || !MAB)
     return true;
 

lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

 
 MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
                                             const MCRegisterInfo &MRI,
-                                            StringRef TT, StringRef CPU) {
+                                            StringRef TT, StringRef CPU,
+                                            const MCTargetOptions&) {
   Triple TheTriple(TT);
 
   if (TheTriple.isOSDarwin())

 
 MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
                                             const MCRegisterInfo &MRI,
-                                            StringRef TT, StringRef CPU) {
+                                            StringRef TT, StringRef CPU,
+                                            const MCTargetOptions&) {
   Triple TheTriple(TT);
 
   assert(TheTriple.isOSBinFormatELF() &&

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h

 class MCObjectWriter;
 class MCStreamer;
 class MCSubtargetInfo;
+class MCTargetOptions;
 class StringRef;
 class Target;
 class raw_ostream;

                                         MCContext &Ctx);
 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI, StringRef TT,
-                                        StringRef CPU);
+                                        StringRef CPU,
+                                        const MCTargetOptions &Options);
 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI, StringRef TT,
-                                        StringRef CPU);
+                                        StringRef CPUi,
+                                        const MCTargetOptions &Options);
 
 MCObjectWriter *createAArch64ELFObjectWriter(raw_ostream &OS, uint8_t OSABI,
                                              bool IsLittleEndian);

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

 
 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
                                           const MCRegisterInfo &MRI,
-                                          StringRef TT, StringRef CPU) {
+                                          StringRef TT, StringRef CPU,
+                                          const MCTargetOptions&) {
   return createARMAsmBackend(T, MRI, TT, CPU, true);
 }
 
 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
                                           const MCRegisterInfo &MRI,
-                                          StringRef TT, StringRef CPU) {
+                                          StringRef TT, StringRef CPU,
+                                          const MCTargetOptions&) {
   return createARMAsmBackend(T, MRI, TT, CPU, false);
 }
 
 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
                                             const MCRegisterInfo &MRI,
-                                            StringRef TT, StringRef CPU) {
+                                            StringRef TT, StringRef CPU,
+                                            const MCTargetOptions&) {
   return createARMAsmBackend(T, MRI, TT, CPU, true);
 }
 
 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
                                             const MCRegisterInfo &MRI,
-                                            StringRef TT, StringRef CPU) {
+                                            StringRef TT, StringRef CPU,
+                                            const MCTargetOptions&) {
   return createARMAsmBackend(T, MRI, TT, CPU, false);
 }

lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

 class MCSubtargetInfo;
 class MCStreamer;
 class MCRelocationInfo;
+class MCTargetOptions;
 class MCTargetStreamer;
 class StringRef;
 class Target;

                                   bool IsLittleEndian);
 
 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                  StringRef TT, StringRef CPU);
+                                    StringRef TT, StringRef CPU,
+                                    const MCTargetOptions &Options);
 
 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                  StringRef TT, StringRef CPU);
+                                    StringRef TT, StringRef CPU,
+                                    const MCTargetOptions &Options);
 
 MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                      StringRef TT, StringRef CPU);
+                                      StringRef TT, StringRef CPU,
+                                      const MCTargetOptions &Options);
 
 MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                      StringRef TT, StringRef CPU);
+                                      StringRef TT, StringRef CPU,
+                                      const MCTargetOptions &Options);
 
 /// createARMWinCOFFStreamer - Construct a PE/COFF machine code streamer which
 /// will generate a PE/COFF object file.

lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp

 
 MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI, StringRef TT,
-                                        StringRef CPU) {
+                                        StringRef CPU, const MCTargetOptions&) {
   return new BPFAsmBackend();
 }

lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h

 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
+class MCTargetOptions;
 class Target;
 class StringRef;
 class raw_ostream;

                                       MCContext &Ctx);
 
 MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                  StringRef TT, StringRef CPU);
+                                  StringRef TT, StringRef CPU,
+                                  const MCTargetOptions &Options);
 
 MCObjectWriter *createBPFELFObjectWriter(raw_ostream &OS, uint8_t OSABI);
 }

lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

 namespace llvm {
 MCAsmBackend *createHexagonAsmBackend(Target const &T,
                                       MCRegisterInfo const & /*MRI*/,
-                                      StringRef TT, StringRef /*CPU*/) {
+                                      StringRef TT, StringRef /*CPU*/,
+                                      const MCTargetOptions&) {
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
   return new ELFHexagonAsmBackend(T, OSABI);
 }

lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h

 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
+class MCTargetOptions;
 class Target;
 class StringRef;
 class raw_ostream;

 
 MCAsmBackend *createHexagonAsmBackend(Target const &T,
                                       MCRegisterInfo const &MRI, StringRef TT,
-                                      StringRef CPU);
+                                      StringRef CPU,
+                                      const MCTargetOptions &Options);
 
 MCObjectWriter *createHexagonELFObjectWriter(raw_ostream &OS, uint8_t OSABI,
                                              StringRef CPU);

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h

   Triple::OSType OSType;
   bool IsLittle; // Big or little endian
   bool Is64Bit;  // 32 or 64 bit words
-
+  bool IsN64;    // Is ABI n64
 public:
   MipsAsmBackend(const Target &T, Triple::OSType _OSType, bool _isLittle,
-                 bool _is64Bit)
+                 bool _is64Bit, bool _isN64)
       : MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle),
-        Is64Bit(_is64Bit) {}
+        Is64Bit(_is64Bit), IsN64(_isN64) {}
 
   MCObjectWriter *createObjectWriter(raw_ostream &OS) const override;
 

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

 #include "MCTargetDesc/MipsFixupKinds.h"
 #include "MCTargetDesc/MipsAsmBackend.h"
 #include "MCTargetDesc/MipsMCTargetDesc.h"
+#include "MCTargetDesc/MipsABIInfo.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCContext.h"

 
 MCObjectWriter *MipsAsmBackend::createObjectWriter(raw_ostream &OS) const {
   return createMipsELFObjectWriter(OS,
-    MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
+    MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit, IsN64);
 }
 
 // Little-endian fixup data byte ordering:

 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
                                              const MCRegisterInfo &MRI,
                                              StringRef TT,
-                                             StringRef CPU) {
+                                             StringRef CPU,
+                                             const MCTargetOptions &Options) {
+  MipsABIInfo ABI = MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options);
   return new MipsAsmBackend(T, Triple(TT).getOS(),
-                            /*IsLittle*/true, /*Is64Bit*/false);
+                            /*IsLittle*/true, /*Is64Bit*/false, ABI.IsN64());
 }
 
 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
                                              const MCRegisterInfo &MRI,
                                              StringRef TT,
-                                             StringRef CPU) {
+                                             StringRef CPU,
+                                             const MCTargetOptions &Options) {
+  MipsABIInfo ABI = MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options);
   return new MipsAsmBackend(T, Triple(TT).getOS(),
-                            /*IsLittle*/false, /*Is64Bit*/false);
+                            /*IsLittle*/false, /*Is64Bit*/false, ABI.IsN64());
 }
 
 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
                                              const MCRegisterInfo &MRI,
                                              StringRef TT,
-                                             StringRef CPU) {
+                                             StringRef CPU,
+                                             const MCTargetOptions &Options) {
+  MipsABIInfo ABI = MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options);
   return new MipsAsmBackend(T, Triple(TT).getOS(),
-                            /*IsLittle*/true, /*Is64Bit*/true);
+                            /*IsLittle*/true, /*Is64Bit*/true, ABI.IsN64());
 }
 
 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
                                              const MCRegisterInfo &MRI,
                                              StringRef TT,
-                                             StringRef CPU) {
+                                             StringRef CPU,
+                                             const MCTargetOptions &Options) {
+  MipsABIInfo ABI = MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options);
   return new MipsAsmBackend(T, Triple(TT).getOS(),
-                            /*IsLittle*/false, /*Is64Bit*/true);
+                            /*IsLittle*/false, /*Is64Bit*/true, ABI.IsN64());
 }

lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp

 MCObjectWriter *llvm::createMipsELFObjectWriter(raw_ostream &OS,
                                                 uint8_t OSABI,
                                                 bool IsLittleEndian,
-                                                bool Is64Bit) {
-  MCELFObjectTargetWriter *MOTW = new MipsELFObjectWriter(Is64Bit, OSABI,
+                                                bool Is64Bit,
+                                                bool IsN64) {
+  MCELFObjectTargetWriter *MOTW = new MipsELFObjectWriter(IsN64, OSABI,
                                                 (Is64Bit) ? true : false,
                                                 IsLittleEndian);
   return createELFObjectWriter(MOTW, OS, IsLittleEndian);

lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h

 class StringRef;
 class Target;
 class raw_ostream;
+class MCTargetOptions;
 
 extern Target TheMipsTarget;
 extern Target TheMipselTarget;

 
 MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
                                        const MCRegisterInfo &MRI, StringRef TT,
-                                       StringRef CPU);
+                                       StringRef CPU,
+                                       const MCTargetOptions &Options);
 MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
                                        const MCRegisterInfo &MRI, StringRef TT,
-                                       StringRef CPU);
+                                       StringRef CPU,
+                                       const MCTargetOptions &Options);
 MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
                                        const MCRegisterInfo &MRI, StringRef TT,
-                                       StringRef CPU);
+                                       StringRef CPU,
+                                       const MCTargetOptions &Options);
 MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
                                        const MCRegisterInfo &MRI, StringRef TT,
-                                       StringRef CPU);
+                                       StringRef CPU,
+                                       const MCTargetOptions &Options);
 
 MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS, uint8_t OSABI,
-                                          bool IsLittleEndian, bool Is64Bit);
+                                          bool IsLittleEndian, bool Is64Bit,
+                                          bool IsN64);
 
 namespace MIPS_MC {
 StringRef selectMipsCPU(StringRef TT, StringRef CPU);

lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

 
 MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        StringRef TT, StringRef CPU) {
+                                        StringRef TT, StringRef CPU,
+                                        const MCTargetOptions&) {
   if (Triple(TT).isOSDarwin())
     return new DarwinPPCAsmBackend(T);
 

lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h

 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
+class MCTargetOptions;
 class Target;
 class StringRef;
 class raw_ostream;

                                       MCContext &Ctx);
 
 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                  StringRef TT, StringRef CPU);
+                                  StringRef TT, StringRef CPU,
+                                  const MCTargetOptions &Options);
 
 /// createPPCELFObjectWriter - Construct an PPC ELF object writer.
 MCObjectWriter *createPPCELFObjectWriter(raw_ostream &OS,

lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp

 MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
                                            const MCRegisterInfo &MRI,
                                            StringRef TT,
-                                           StringRef CPU) {
+                                           StringRef CPU,
+                                           const MCTargetOptions&) {
   return new ELFAMDGPUAsmBackend(T);
 }

lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h

 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
+class MCTargetOptions;
 class Target;
 class raw_ostream;
 

                                      MCContext &Ctx);
 
 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                     StringRef TT, StringRef CPU);
+                                     StringRef TT, StringRef CPU,
+                                     const MCTargetOptions &Options);
 
 MCObjectWriter *createAMDGPUELFObjectWriter(raw_ostream &OS);
 } // End llvm namespace

lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

 MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
                                           const MCRegisterInfo &MRI,
                                           StringRef TT,
-                                          StringRef CPU) {
+                                          StringRef CPU,
+                                          const MCTargetOptions&) {
   return new ELFSparcAsmBackend(T, Triple(TT).getOS());
 }

lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h

 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
+class MCTargetOptions;
 class Target;
 class StringRef;
 class raw_ostream;

 MCAsmBackend *createSparcAsmBackend(const Target &T,
                                     const MCRegisterInfo &MRI,
                                     StringRef TT,
-                                    StringRef CPU);
+                                    StringRef CPU,
+                                    const MCTargetOptions &Options);
 MCObjectWriter *createSparcELFObjectWriter(raw_ostream &OS,
                                            bool Is64Bit,
                                            uint8_t OSABI);

lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp

 
 MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
                                               const MCRegisterInfo &MRI,
-                                              StringRef TT, StringRef CPU) {
+                                              StringRef TT, StringRef CPU,
+                                              const MCTargetOptions&) {
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
   return new SystemZMCAsmBackend(OSABI);
 }

lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h

 class MCObjectWriter;
 class MCRegisterInfo;
 class MCSubtargetInfo;
+class MCTargetOptions;
 class StringRef;
 class Target;
 class raw_ostream;

 
 MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        StringRef TT, StringRef CPU);
+                                        StringRef TT, StringRef CPU,
+                                        const MCTargetOptions &Options);
 
 MCObjectWriter *createSystemZObjectWriter(raw_ostream &OS, uint8_t OSABI);
 } // end namespace llvm

lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
                                            const MCRegisterInfo &MRI,
                                            StringRef TT,
-                                           StringRef CPU) {
+                                           StringRef CPU,
+                                           const MCTargetOptions&) {
   Triple TheTriple(TT);
 
   if (TheTriple.isOSBinFormatMachO())

 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
                                            const MCRegisterInfo &MRI,
                                            StringRef TT,
-                                           StringRef CPU) {
+                                           StringRef CPU,
+                                           const MCTargetOptions&) {
   Triple TheTriple(TT);
 
   if (TheTriple.isOSBinFormatMachO()) {

lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h

 class MCSubtargetInfo;
 class MCRelocationInfo;
 class MCStreamer;
+class MCTargetOptions;
 class Target;
 class Triple;
 class StringRef;

                                       MCContext &Ctx);
 
 MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                     StringRef TT, StringRef CPU);
+                                     StringRef TT, StringRef CPU,
+                                     const MCTargetOptions &Options);
 MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                     StringRef TT, StringRef CPU);
+                                     StringRef TT, StringRef CPU,
+                                     const MCTargetOptions &Options);
 
 /// createX86WinCOFFStreamer - Construct an X86 Windows COFF machine code
 /// streamer which will generate PE/COFF format object files.

test/MC/Mips/cpsetup.s

 
 # NXX: sd       $gp, 8($sp)
 # NXX: lui      $gp, 0
-# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16  __cerror
+# N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16  __cerror
+# N23: R_MIPS_GPREL16  __cerror
 # NXX: addiu    $gp, $gp, 0
-# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16  __cerror
+# N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16  __cerror
+# N32: R_MIPS_GPREL16  __cerror
 # N32: addu     $gp, $gp, $25
 # N64: daddu    $gp, $gp, $25
 

 
 # NXX: move     $2, $gp
 # NXX: lui      $gp, 0
-# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16  __cerror
+# N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16  __cerror
+# N32: R_MIPS_GPREL16  __cerror
 # NXX: addiu    $gp, $gp, 0
-# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16  __cerror
+# N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16  __cerror
+# N32: R_MIPS_GPREL16  __cerror
 # N32: addu     $gp, $gp, $25
 # N64: daddu    $gp, $gp, $25
 

 
 # NXX: move     $2, $gp
 # NXX: lui      $gp, 0
-# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16  $tmp0
+# N^$: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16  $tmp0
+# N32: R_MIPS_GPREL16  $tmp0
 # NXX: addiu    $gp, $gp, 0
-# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16  $tmp0
+# N32: R_MIPS_GPREL16  $tmp0
+# N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16  $tmp0
 # N32: addu     $gp, $gp, $25
 # N64: daddu    $gp, $gp, $25
 # NXX: nop

test/MC/Mips/mips64r6/relocations.s

 # Check that the appropriate relocations were created.
 #------------------------------------------------------------------------------
 # CHECK-ELF: Relocations [
-# CHECK-ELF:     0x0 R_MIPS_PC19_S2 bar 0x0
-# CHECK-ELF:     0x4 R_MIPS_PC16 bar 0x0
-# CHECK-ELF:     0x8 R_MIPS_PC16 bar 0x0
-# CHECK-ELF:     0xC R_MIPS_PC21_S2 bar 0x0
-# CHECK-ELF:     0x10 R_MIPS_PC21_S2 bar 0x0
-# CHECK-ELF:     0x14 R_MIPS_PC26_S2 bar 0x0
-# CHECK-ELF:     0x18 R_MIPS_PC26_S2 bar 0x0
-# CHECK-ELF:     0x1C R_MIPS_PCHI16 bar 0x0
-# CHECK-ELF:     0x20 R_MIPS_PCLO16 bar 0x0
-# CHECK-ELF:     0x24 R_MIPS_PC18_S3 bar 0x0
-# CHECK-ELF:     0x28 R_MIPS_PC19_S2 bar 0x0
-# CHECK-ELF:     0x2C R_MIPS_PC19_S2 bar 0x0
+# CHECK-ELF:     0x0 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x4 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x8 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0xC R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x10 R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x14 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x18 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x1C R_MIPS_PCHI16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x20 R_MIPS_PCLO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x24 R_MIPS_PC18_S3/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x28 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x2C R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
 # CHECK-ELF: ]
 
   addiupc   $2,bar

tools/llvm-mc/llvm-mc.cpp

     MCAsmBackend *MAB = nullptr;
     if (ShowEncoding) {
       CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
-      MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
+      MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU, MCOptions);
     }
     Str.reset(TheTarget->createAsmStreamer(Ctx, FOS, /*asmverbose*/ true,
                                            /*useDwarfDirectory*/ true, IP, CE,

   } else {
     assert(FileType == OFT_ObjectFile && "Invalid file type!");
     MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
-    MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
+    MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU, MCOptions);
     Str.reset(TheTarget->createMCObjectStreamer(TripleName, Ctx, *MAB, FOS, CE,
                                                 *STI, RelaxAll));
     if (NoExecStack)