AMDGPU/GlobalISel: Don't constrain source register of VCC copies

[arsenm]

Summary

This is a hack until I come up with a better way of dealing with the
pseudo-register banks used for boolean values. If the use instruction
constrains the register, the selector for the def instruction won't
see that the bank was VCC. A 1-bit SReg_32 is could ambiguously have
been SCCRegBank or VCCRegBank in wave32.

This is necessary to successfully select branches with and and/or/xor
condition.

[tstellar]

LGTM, do you think we'll need new register classes for the 32-bit boolean values?

[arsenm]

In D64728#1585640, @tstellar wrote:

LGTM, do you think we'll need new register classes for the 32-bit boolean values?

Possibly, there are a lot of things to try for booleans

[arsenm]

r366120

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

if (!isVCC(SrcReg, MRI)) {
         .addImm(0)
         .addReg(SrcReg);
 
       if (!MRI.getRegClassOrNull(SrcReg))
         MRI.setRegClass(SrcReg, TRI.getConstrainedRegClassForOperand(Src, MRI));
       I.eraseFromParent();
       return true;
     }
+
+    const TargetRegisterClass *RC =
+      TRI.getConstrainedRegClassForOperand(Dst, MRI);
+    if (RC && !RBI.constrainGenericRegister(DstReg, *RC, MRI))
+      return false;
+
+    // Don't constrain the source register to a class so the def instruction
+    // handles it (unless it's undef).
+    //
+    // FIXME: This is a hack. When selecting the def, we neeed to know
+    // specifically know that the result is VCCRegBank, and not just an SGPR
+    // with size 1. An SReg_32 with size 1 is ambiguous with wave32.
+    if (Src.isUndef()) {
+      const TargetRegisterClass *SrcRC =
+        TRI.getConstrainedRegClassForOperand(Src, MRI);
+      if (SrcRC && !RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI))
+        return false;
+    }
+
+    return true;
   }
 
   for (const MachineOperand &MO : I.operands()) {
     if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
       continue;
 
     const TargetRegisterClass *RC =
             TRI.getConstrainedRegClassForOperand(MO, MRI);

test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir

 
 
 body: |
   bb.0:
     liveins: $sgpr0_sgpr1
 
     ; WAVE64-LABEL: name: copy_s1_vcc_to_vcc
     ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
-    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
-    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]]
+    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_NE_U32_e64_]]
+    ; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
     ; WAVE32-LABEL: name: copy_s1_vcc_to_vcc
     ; WAVE32: $vcc_hi = IMPLICIT_DEF
     ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
-    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
-    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]]
+    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
+    ; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s1) = G_TRUNC %0
     %2:vcc(s1) = COPY %1
     %3:vcc(s1) = COPY %2
     S_ENDPGM 0, implicit %3
 
 ...
+
+---
+
+name:            copy_s1_vcc_to_vcc_undef
+legalized:       true
+regBankSelected: true
+
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+
+    ; WAVE64-LABEL: name: copy_s1_vcc_to_vcc_undef
+    ; WAVE64: S_ENDPGM 0, implicit %1:sreg_64_xexec
+    ; WAVE32-LABEL: name: copy_s1_vcc_to_vcc_undef
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: S_ENDPGM 0, implicit %1:sreg_32_xm0_xexec
+    %1:vcc(s1) = COPY undef  %0:vcc(s1)
+    S_ENDPGM 0, implicit %1
+
+...