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AMDGPU/GlobalISel: Don't constrain source register of VCC copies
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Authored by arsenm on Jul 15 2019, 5:57 AM.

Details

Reviewers
tstellar
nhaehnle
Summary

This is a hack until I come up with a better way of dealing with the
pseudo-register banks used for boolean values. If the use instruction
constrains the register, the selector for the def instruction won't
see that the bank was VCC. A 1-bit SReg_32 is could ambiguously have
been SCCRegBank or VCCRegBank in wave32.

This is necessary to successfully select branches with and and/or/xor
condition.

Diff Detail

Event Timeline

arsenm created this revision.Jul 15 2019, 5:57 AM
tstellar accepted this revision.Jul 15 2019, 7:44 AM

LGTM, do you think we'll need new register classes for the 32-bit boolean values?

This revision is now accepted and ready to land.Jul 15 2019, 7:44 AM

LGTM, do you think we'll need new register classes for the 32-bit boolean values?

Possibly, there are a lot of things to try for booleans

arsenm closed this revision.Jul 15 2019, 12:48 PM

r366120