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Differential D64716

[AMDGPU][MC] Corrected encoding of src0 for DS_GWS_* instructions
ClosedPublic

Authored by dp on Jul 15 2019, 5:25 AM.

Details

Reviewers
arsenm
artem.tamazov
b-sumner
Commits
rG8d879c8d9549: [AMDGPU][MC] Corrected encoding of src0 for DS_GWS_* instructions
rL366067: [AMDGPU][MC] Corrected encoding of src0 for DS_GWS_* instructions
Summary

See bug 42599: https://bugs.llvm.org/show_bug.cgi?id=42599

Note that changes in generated tests are not included in this review due to large tests size.

Diff Detail

Event Timeline

dp created this revision.Jul 15 2019, 5:25 AM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptJul 15 2019, 5:25 AM
arsenm accepted this revision.Jul 15 2019, 6:20 AM

LGTM

This revision is now accepted and ready to land.Jul 15 2019, 6:20 AM
artem.tamazov accepted this revision.Jul 15 2019, 7:02 AM

LGTM!

Closed by commit rL366067: [AMDGPU][MC] Corrected encoding of src0 for DS_GWS_* instructions (authored by dpreobra). · Explain WhyJul 15 2019, 7:38 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptJul 15 2019, 7:38 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript

Revision Contents

PathSize
lib/
Target/
AMDGPU/
8 lines
test/
MC/
AMDGPU/
16 lines
2 lines
Disassembler/
AMDGPU/
16 lines

Diff 209806

lib/Target/AMDGPU/DSInstructions.td

Show All 32 Linesclass DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
// Well these bits a kind of hack because it would be more natural // Well these bits a kind of hack because it would be more natural
// to test "outs" and "ins" dags for the presence of particular operands // to test "outs" and "ins" dags for the presence of particular operands
bits<1> has_vdst = 1; bits<1> has_vdst = 1;
bits<1> has_addr = 1; bits<1> has_addr = 1;
bits<1> has_data0 = 1; bits<1> has_data0 = 1;
bits<1> has_data1 = 1; bits<1> has_data1 = 1;
bits<1> has_gws_data0 = 0; // data0 is encoded as addr
bits<1> has_offset = 1; // has "offset" that should be split to offset0,1 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1
bits<1> has_offset0 = 1; bits<1> has_offset0 = 1;
bits<1> has_offset1 = 1; bits<1> has_offset1 = 1;
bits<1> has_gds = 1; bits<1> has_gds = 1;
bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
bits<1> has_m0_read = 1; bits<1> has_m0_read = 1;
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class DS_GWS_0D <string opName> class DS_GWS_0D <string opName>
: DS_GWS<opName, : DS_GWS<opName,
(ins offset:$offset, gds:$gds), "$offset gds">; (ins offset:$offset, gds:$gds), "$offset gds">;
class DS_GWS_1D <string opName> class DS_GWS_1D <string opName>
: DS_GWS<opName, : DS_GWS<opName,
(ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> { (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
let has_data0 = 1; let has_gws_data0 = 1;
} }
class DS_VOID <string opName> : DS_Pseudo<opName, class DS_VOID <string opName> : DS_Pseudo<opName,
(outs), (ins), ""> { (outs), (ins), ""> {
let mayLoad = 0; let mayLoad = 0;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 1; let hasSideEffects = 1;
let UseNamedOperandTable = 0; let UseNamedOperandTable = 0;
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class Base_DS_Real_gfx6_gfx7_gfx10<bits<8> op, DS_Pseudo ps, int ef> : class Base_DS_Real_gfx6_gfx7_gfx10<bits<8> op, DS_Pseudo ps, int ef> :
DS_Real<ps>, SIMCInstr <ps.Mnemonic, ef> { DS_Real<ps>, SIMCInstr <ps.Mnemonic, ef> {
let Inst{7-0} = !if(ps.has_offset0, offset0, 0); let Inst{7-0} = !if(ps.has_offset0, offset0, 0);
let Inst{15-8} = !if(ps.has_offset1, offset1, 0); let Inst{15-8} = !if(ps.has_offset1, offset1, 0);
let Inst{17} = !if(ps.has_gds, gds, ps.gdsValue); let Inst{17} = !if(ps.has_gds, gds, ps.gdsValue);
let Inst{25-18} = op; let Inst{25-18} = op;
let Inst{31-26} = 0x36; let Inst{31-26} = 0x36;
let Inst{39-32} = !if(ps.has_addr, addr, 0); let Inst{39-32} = !if(ps.has_addr, addr, !if(ps.has_gws_data0, data0, 0));
let Inst{47-40} = !if(ps.has_data0, data0, 0); let Inst{47-40} = !if(ps.has_data0, data0, 0);
let Inst{55-48} = !if(ps.has_data1, data1, 0); let Inst{55-48} = !if(ps.has_data1, data1, 0);
let Inst{63-56} = !if(ps.has_vdst, vdst, 0); let Inst{63-56} = !if(ps.has_vdst, vdst, 0);
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// GFX10. // GFX10.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 202 Lines • ▼ Show 20 Linesclass DS_Real_vi <bits<8> op, DS_Pseudo ds> :
let DecoderNamespace = "GFX8"; let DecoderNamespace = "GFX8";
// encoding // encoding
let Inst{7-0} = !if(ds.has_offset0, offset0, 0); let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
let Inst{15-8} = !if(ds.has_offset1, offset1, 0); let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue); let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue);
let Inst{24-17} = op; let Inst{24-17} = op;
let Inst{31-26} = 0x36; // ds prefix let Inst{31-26} = 0x36; // ds prefix
let Inst{39-32} = !if(ds.has_addr, addr, 0); let Inst{39-32} = !if(ds.has_addr, addr, !if(ds.has_gws_data0, data0, 0));
let Inst{47-40} = !if(ds.has_data0, data0, 0); let Inst{47-40} = !if(ds.has_data0, data0, 0);
let Inst{55-48} = !if(ds.has_data1, data1, 0); let Inst{55-48} = !if(ds.has_data1, data1, 0);
let Inst{63-56} = !if(ds.has_vdst, vdst, 0); let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
} }
def DS_ADD_U32_vi : DS_Real_vi<0x0, DS_ADD_U32>; def DS_ADD_U32_vi : DS_Real_vi<0x0, DS_ADD_U32>;
def DS_SUB_U32_vi : DS_Real_vi<0x1, DS_SUB_U32>; def DS_SUB_U32_vi : DS_Real_vi<0x1, DS_SUB_U32>;
def DS_RSUB_U32_vi : DS_Real_vi<0x2, DS_RSUB_U32>; def DS_RSUB_U32_vi : DS_Real_vi<0x2, DS_RSUB_U32>;
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test/MC/AMDGPU/ds.s

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// SICI: ds_min_f32 v2, v4 ; encoding: [0x00,0x00,0x48,0xd8,0x02,0x04,0x00,0x00] // SICI: ds_min_f32 v2, v4 ; encoding: [0x00,0x00,0x48,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_min_f32 v2, v4 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x00,0x00] // VI: ds_min_f32 v2, v4 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x00,0x00]
ds_max_f32 v2, v4 ds_max_f32 v2, v4
// SICI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x4c,0xd8,0x02,0x04,0x00,0x00] // SICI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x4c,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x00,0x00] // VI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x00,0x00]
ds_gws_init v2 gds ds_gws_init v2 gds
// SICI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x66,0xd8,0x00,0x02,0x00,0x00] // SICI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x00,0x00,0x00]
// VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00] // VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x02,0x00,0x00,0x00]
ds_gws_init v3 offset:12345 gds ds_gws_init v3 offset:12345 gds
// SICI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x66,0xd8,0x00,0x03,0x00,0x00] // SICI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x66,0xd8,0x03,0x00,0x00,0x00]
// VI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x33,0xd9,0x00,0x03,0x00,0x00] // VI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x33,0xd9,0x03,0x00,0x00,0x00]
ds_gws_sema_v gds ds_gws_sema_v gds
// SICI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00] // SICI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
// VI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00] // VI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
ds_gws_sema_v offset:257 gds ds_gws_sema_v offset:257 gds
// SICI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x6a,0xd8,0x00,0x00,0x00,0x00] // SICI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x6a,0xd8,0x00,0x00,0x00,0x00]
// VI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x35,0xd9,0x00,0x00,0x00,0x00] // VI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x35,0xd9,0x00,0x00,0x00,0x00]
ds_gws_sema_br v2 gds ds_gws_sema_br v2 gds
// SICI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x6e,0xd8,0x00,0x02,0x00,0x00] // SICI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x6e,0xd8,0x02,0x00,0x00,0x00]
// VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd9,0x00,0x02,0x00,0x00] // VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd9,0x02,0x00,0x00,0x00]
ds_gws_sema_p gds ds_gws_sema_p gds
// SICI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00] // SICI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
// VI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00] // VI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
ds_gws_barrier v2 gds ds_gws_barrier v2 gds
// SICI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x76,0xd8,0x00,0x02,0x00,0x00] // SICI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x76,0xd8,0x02,0x00,0x00,0x00]
// VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd9,0x00,0x02,0x00,0x00] // VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd9,0x02,0x00,0x00,0x00]
ds_write_b8 v2, v4 ds_write_b8 v2, v4
// SICI: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x78,0xd8,0x02,0x04,0x00,0x00] // SICI: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x78,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x3c,0xd8,0x02,0x04,0x00,0x00] // VI: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x3c,0xd8,0x02,0x04,0x00,0x00]
ds_write_b16 v2, v4 ds_write_b16 v2, v4
// SICI: ds_write_b16 v2, v4 ; encoding: [0x00,0x00,0x7c,0xd8,0x02,0x04,0x00,0x00] // SICI: ds_write_b16 v2, v4 ; encoding: [0x00,0x00,0x7c,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_write_b16 v2, v4 ; encoding: [0x00,0x00,0x3e,0xd8,0x02,0x04,0x00,0x00] // VI: ds_write_b16 v2, v4 ; encoding: [0x00,0x00,0x3e,0xd8,0x02,0x04,0x00,0x00]
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test/MC/AMDGPU/expressions.s

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// Parse a global expression // Parse a global expression
s_mov_b32 s0, global s_mov_b32 s0, global
// VI: s_mov_b32 s0, global ; encoding: [0xff,0x00,0x80,0xbe,A,A,A,A] // VI: s_mov_b32 s0, global ; encoding: [0xff,0x00,0x80,0xbe,A,A,A,A]
// VI-NEXT: ; fixup A - offset: 4, value: global, kind: FK_PCRel_4 // VI-NEXT: ; fixup A - offset: 4, value: global, kind: FK_PCRel_4
// Use a token with the same name as a global // Use a token with the same name as a global
ds_gws_init v2 gds ds_gws_init v2 gds
// VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00] // VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x02,0x00,0x00,0x00]
// Use a global with the same name as a token // Use a global with the same name as a token
s_mov_b32 s0, gds s_mov_b32 s0, gds
// VI: s_mov_b32 s0, gds ; encoding: [0xff,0x00,0x80,0xbe,A,A,A,A] // VI: s_mov_b32 s0, gds ; encoding: [0xff,0x00,0x80,0xbe,A,A,A,A]
// VI-NEXT: ; fixup A - offset: 4, value: gds, kind: FK_PCRel_4 // VI-NEXT: ; fixup A - offset: 4, value: gds, kind: FK_PCRel_4
// Use a binary expression // Use a binary expression
s_mov_b32 s0, gds+4 s_mov_b32 s0, gds+4
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test/MC/Disassembler/AMDGPU/ds_vi.txt

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0x00 0x00 0x22 0xd8 0x02 0x04 0x06 0x00 0x00 0x00 0x22 0xd8 0x02 0x04 0x06 0x00
# VI: ds_min_f32 v2, v4 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x00,0x00] # VI: ds_min_f32 v2, v4 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x00,0x00]
0x00 0x00 0x24 0xd8 0x02 0x04 0x00 0x00 0x00 0x00 0x24 0xd8 0x02 0x04 0x00 0x00
# VI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x00,0x00] # VI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x00,0x00]
0x00 0x00 0x26 0xd8 0x02 0x04 0x00 0x00 0x00 0x00 0x26 0xd8 0x02 0x04 0x00 0x00
# VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00] # VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x02,0x00,0x00,0x00]
0x00 0x00 0x33 0xd9 0x00 0x02 0x00,0x00 0x00 0x00 0x33 0xd9 0x02 0x00 0x00,0x00
# VI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x33,0xd9,0x00,0x03,0x00,0x00] # VI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x33,0xd9,0x03,0x00,0x00,0x00]
0x39 0x30 0x33 0xd9 0x00 0x03 0x00 0x00 0x39 0x30 0x33 0xd9 0x03 0x00 0x00 0x00
# VI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00] # VI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
0x00 0x00 0x35 0xd9 0x00 0x00 0x00 0x00 0x00 0x00 0x35 0xd9 0x00 0x00 0x00 0x00
# VI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x35,0xd9,0x00,0x00,0x00,0x00] # VI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x35,0xd9,0x00,0x00,0x00,0x00]
0x01 0x01 0x35 0xd9 0x00 0x00 0x00 0x00 0x01 0x01 0x35 0xd9 0x00 0x00 0x00 0x00
# VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd9,0x00,0x02,0x00,0x00] # VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd9,0x02,0x00,0x00,0x00]
0x00 0x00 0x37 0xd9 0x00 0x02 0x00 0x00 0x00 0x00 0x37 0xd9 0x02 0x00 0x00 0x00
# VI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00] # VI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
0x00 0x00 0x39 0xd9 0x00 0x00 0x00 0x00 0x00 0x00 0x39 0xd9 0x00 0x00 0x00 0x00
# VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd9,0x00,0x02,0x00,0x00] # VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd9,0x02,0x00,0x00,0x00]
0x00 0x00 0x3b 0xd9 0x00 0x02 0x00 0x00 0x00 0x00 0x3b 0xd9 0x02 0x00 0x00 0x00
# VI: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x3c,0xd8,0x02,0x04,0x00,0x00] # VI: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x3c,0xd8,0x02,0x04,0x00,0x00]
0x00 0x00 0x3c 0xd8 0x02 0x04 0x00 0x00 0x00 0x00 0x3c 0xd8 0x02 0x04 0x00 0x00
# VI: ds_write_b16 v2, v4 ; encoding: [0x00,0x00,0x3e,0xd8,0x02,0x04,0x00,0x00] # VI: ds_write_b16 v2, v4 ; encoding: [0x00,0x00,0x3e,0xd8,0x02,0x04,0x00,0x00]
0x00 0x00 0x3e 0xd8 0x02 0x04 0x00 0x00 0x00 0x00 0x3e 0xd8 0x02 0x04 0x00 0x00
# VI: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x40,0xd8,0x02,0x04,0x00,0x08] # VI: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x40,0xd8,0x02,0x04,0x00,0x08]
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