[AMDGPU] Skip calculating callee saved registers for entry function.

[arsenm]

What is this supposed to solve?

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

979–980

Why wouldn't this skip the base call?

1049–1051

SGPR version should also be skipped?

[hliao]

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

979–980

to resize the SavedVGPRs to the proper size in case any code may break on that

[hliao]

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

1049–1051

sure

[hliao]

skip determining callee saved scalar register as well.

[hliao]

In D64596#1581524, @arsenm wrote:

What is this supposed to solve?

the issue happens when we need to spill FP when all SGRPs used. However, register scavenger is only allocated when necessary for entry function. The newly created frame object when we determine whether FP needs to be spilled breaks later process as RS is not allocated at the beginning.

[arsenm]

LGTM

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

void SIFrameLowering::processFunctionBeforeFrameFinalized(
   }
 }
 
 // Only report VGPRs to generic code.
 void SIFrameLowering::determineCalleeSaves(MachineFunction &MF,
                                            BitVector &SavedVGPRs,
                                            RegScavenger *RS) const {
   TargetFrameLowering::determineCalleeSaves(MF, SavedVGPRs, RS);
-
   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
+  if (MFI->isEntryFunction())
+    return;
+
   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   const SIRegisterInfo *TRI = ST.getRegisterInfo();
 
   // Ignore the SGPRs the default implementation found.
   SavedVGPRs.clearBitsNotInMask(TRI->getAllVGPRRegMask());
 
   // hasFP only knows about stack objects that already exist. We're now
LLVM_DEBUG(
       dbgs() << "FP requires fallback spill to " << printReg(Spill.VGPR, TRI)
              << ':' << Spill.Lane << '\n';);
   } else {
     LLVM_DEBUG(dbgs() << "Saving FP with copy to " <<
                printReg(MFI->SGPRForFPSaveRestoreCopy, TRI) << '\n');
   }
 }
 
 void SIFrameLowering::determineCalleeSavesSGPR(MachineFunction &MF,
                                                BitVector &SavedRegs,
                                                RegScavenger *RS) const {
   TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
+  if (MFI->isEntryFunction())
+    return;
 
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   const SIRegisterInfo *TRI = ST.getRegisterInfo();
 
   // The SP is specifically managed and we don't want extra spills of it.
   SavedRegs.reset(MFI->getStackPtrOffsetReg());
   SavedRegs.clearBitsInMask(TRI->getAllVGPRRegMask());
 }

llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir

+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck %s
+
+# CHECK-LABEL: all_sgpr_used
+# CHECK: V_CMP_LT_U32_e64
+--- |
+  define amdgpu_kernel void @all_sgpr_used() #0 {
+    ret void
+  }
+  attributes #0 = { "amdgpu-num-sgpr"="8" "frame-pointer"="all"}
+...
+---
+name:            all_sgpr_used
+tracksRegLiveness: true
+liveins:         
+  - { reg: '$vgpr0' }
+  - { reg: '$vgpr1' }
+  - { reg: '$vgpr2' }
+  - { reg: '$sgpr4_sgpr5' }
+  - { reg: '$sgpr6_sgpr7' }
+  - { reg: '$sgpr8' }
+  - { reg: '$sgpr9' }
+machineFunctionInfo: 
+  explicitKernArgSize: 84
+  maxKernArgAlign: 8
+  ldsSize:         20496
+  isEntryFunction: true
+  waveLimiter:     true
+  scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
+  scratchWaveOffsetReg: '$sgpr101'
+  frameOffsetReg:  '$sgpr101'
+  stackPtrOffsetReg: '$sgpr32'
+  argumentInfo:    
+    privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
+    dispatchPtr:     { reg: '$sgpr4_sgpr5' }
+    kernargSegmentPtr: { reg: '$sgpr6_sgpr7' }
+    workGroupIDX:    { reg: '$sgpr8' }
+    workGroupIDY:    { reg: '$sgpr9' }
+    privateSegmentWaveByteOffset: { reg: '$sgpr10' }
+    workItemIDX:     { reg: '$vgpr0' }
+    workItemIDY:     { reg: '$vgpr1' }
+    workItemIDZ:     { reg: '$vgpr2' }
+body:             |
+  bb.0:
+    liveins: $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7
+    $sgpr0 = S_MOV_B32 0
+    $sgpr1 = S_MOV_B32 0
+    $sgpr2 = S_MOV_B32 0
+    $sgpr3 = S_MOV_B32 0
+    $sgpr4 = S_MOV_B32 0
+    $sgpr5 = S_MOV_B32 0
+    $sgpr6 = S_MOV_B32 0
+    $sgpr7 = S_MOV_B32 0
+    $vcc = V_CMP_LT_U32_e64 $sgpr8, $vgpr1, implicit $exec
+...