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[AMDGPU] Skip calculating callee saved registers for entry function.
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Authored by hliao on Jul 11 2019, 2:10 PM.

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hliao created this revision.Jul 11 2019, 2:10 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 11 2019, 2:10 PM

What is this supposed to solve?

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
985–986 ↗(On Diff #209328)

Why wouldn't this skip the base call?

1055–1057 ↗(On Diff #209328)

SGPR version should also be skipped?

hliao marked an inline comment as done.Jul 11 2019, 2:16 PM
hliao added inline comments.
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
985–986 ↗(On Diff #209328)

to resize the SavedVGPRs to the proper size in case any code may break on that

hliao marked an inline comment as done.Jul 11 2019, 2:17 PM
hliao added inline comments.
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
1055–1057 ↗(On Diff #209328)

sure

hliao updated this revision to Diff 209332.Jul 11 2019, 2:19 PM

skip determining callee saved scalar register as well.

hliao added a comment.Jul 11 2019, 2:26 PM

What is this supposed to solve?

the issue happens when we need to spill FP when all SGRPs used. However, register scavenger is only allocated when necessary for entry function. The newly created frame object when we determine whether FP needs to be spilled breaks later process as RS is not allocated at the beginning.

arsenm accepted this revision.Jul 11 2019, 3:25 PM

LGTM

This revision is now accepted and ready to land.Jul 11 2019, 3:25 PM
This revision was automatically updated to reflect the committed changes.