[AMDGPU] gfx908 v_pk_fmac_f16 support

[arsenm]

LGTM, but it is missing selecting of it

[rampitec]

In D64433#1577206, @arsenm wrote:

LGTM, but it is missing selecting of it

It was yet in GFX10, so selection already exists.

lib/Target/AMDGPU/AMDGPU.td

def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
    FeatureCIInsts, Feature16BitInsts,
    FeatureSMemRealTime, FeatureInv2PiInlineImm,
    FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
    FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
    FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
    FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
    FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
    FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
-   FeatureVOP3Literal, FeatureDPP8, FeatureNoDataDepHazard,
-   FeatureDoesNotSupportSRAMECC
+   FeatureVOP3Literal, FeatureDPP8,
+   FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC
   ]
 >;
 
 class FeatureSet<list<SubtargetFeature> Features_> {
   list<SubtargetFeature> Features = Features_;
 }
 
 def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,

lib/Target/AMDGPU/VOP2Instructions.td

 
 let Constraints = "$vdst = $src2",
     DisableEncoding="$src2",
     isConvertibleToThreeAddress = 1,
     isCommutable = 1 in {
 defm V_FMAC_F16 : VOP2Inst <"v_fmac_f16", VOP_MAC_F16>;
 }
 
-defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>;
-
 } // End SubtargetPredicate = isGFX10Plus
 
+let SubtargetPredicate = HasPkFmacF16Inst in {
+defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>;
+} // End SubtargetPredicate = HasPkFmacF16Inst
+
 // Note: 16-bit instructions produce a 0 result in the high 16-bits
 // on GFX8 and GFX9 and preserve high 16 bits on GFX10+
 def ClearHI16 : OutPatFrag<(ops node:$op),
                            (V_AND_B32_e64 $op, (V_MOV_B32_e32 (i32 0xffff)))>;
 
 multiclass Arithmetic_i16_Pats <SDPatternOperator op, Instruction inst,
                                 bit PreservesHI16 = 0> {
 

 }
 
 let SubtargetPredicate = HasDot4Insts in {
   defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>;
 }
 let SubtargetPredicate = HasDot3Insts in {
   defm V_DOT8C_I32_I4  : VOP2_Real_DOT_ACC_gfx9<0x3a>;
 }
+
+let SubtargetPredicate = HasPkFmacF16Inst in {
+defm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>;
+} // End SubtargetPredicate = HasPkFmacF16Inst

test/MC/AMDGPU/xdl-insts-gfx908.s

 // CHECK: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x0f]
 v_dot8c_i32_i4_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
 
 // CHECK: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x0f]
 v_dot8c_i32_i4_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
 
 // CHECK: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00]
 v_dot8c_i32_i4_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+
+// CHECK: encoding: [0x01,0x05,0x0a,0x78]
+v_pk_fmac_f16 v5, v1, v2
+
+// CHECK: encoding: [0x01,0x05,0xfe,0x79]
+v_pk_fmac_f16 v255, v1, v2
+
+// CHECK: encoding: [0xff,0x05,0x0a,0x78]
+v_pk_fmac_f16 v5, v255, v2
+
+// CHECK: encoding: [0x01,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, s1, v2
+
+// CHECK: encoding: [0x6a,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, vcc_lo, v2
+
+// CHECK: encoding: [0x6b,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, vcc_hi, v2
+
+// CHECK: encoding: [0x77,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, ttmp11, v2
+
+// CHECK: encoding: [0x7c,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, m0, v2
+
+// CHECK: encoding: [0x7e,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, exec_lo, v2
+
+// CHECK: encoding: [0x7f,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, exec_hi, v2
+
+// CHECK: encoding: [0x80,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, 0, v2
+
+// CHECK: encoding: [0xc1,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, -1, v2
+
+// CHECK: encoding: [0xf0,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, 0.5, v2
+
+// CHECK: encoding: [0xf7,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, -4.0, v2
+
+// CHECK: encoding: [0x01,0xff,0x0b,0x78]
+v_pk_fmac_f16 v5, v1, v255

test/MC/Disassembler/AMDGPU/xdl-insts-gfx908.txt

 # CHECK: v_dot8c_i32_i4_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x03
 
 # CHECK: v_dot8c_i32_i4_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x0f
 
 # CHECK: v_dot8c_i32_i4_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00
+
+# CHECK: v_pk_fmac_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x78]
+0x01,0x05,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x79]
+0x01,0x05,0xfe,0x79
+
+# CHECK: v_pk_fmac_f16_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x78]
+0xff,0x05,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x78]
+0x01,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x78]
+0x6a,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x78]
+0x6b,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, ttmp11, v2 ; encoding: [0x77,0x04,0x0a,0x78]
+0x77,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, m0, v2 ; encoding: [0x7c,0x04,0x0a,0x78]
+0x7c,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x78]
+0x7e,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x78]
+0x7f,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, 0, v2 ; encoding: [0x80,0x04,0x0a,0x78]
+0x80,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x78]
+0xc1,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x78]
+0xf0,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, -4.0, v2 ; encoding: [0xf7,0x04,0x0a,0x78]
+0xf7,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, v1, v255 ; encoding: [0x01,0xff,0x0b,0x78]
+0x01,0xff,0x0b,0x78