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Differential D64211

[AArch64] Fix vector vuqadd intrinsics operands
ClosedPublic

Authored by dnsampaio on Jul 4 2019, 8:46 AM.

Details

Reviewers
LukeCheeseman
ostannard
Commits
rG71cac61d0188: [AArch64] Fix vector vuqadd intrinsics operands
rL365609: [AArch64] Fix vector vuqadd intrinsics operands
rC365609: [AArch64] Fix vector vuqadd intrinsics operands
Summary

Change the vuqadd vector instrinsics to have the second argument as unsigned values, not signed,
accordingly to https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics

Diff Detail

Event Timeline

dnsampaio created this revision.Jul 4 2019, 8:46 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 4 2019, 8:46 AM
Herald added subscribers: cfe-commits, kristof.beyls, javed.absar. · View Herald Transcript
Harbormaster completed remote builds in B34387: Diff 208052.Jul 4 2019, 8:46 AM
LukeCheeseman added a comment.Jul 4 2019, 8:50 AM

Are there some changes/addition to tests attached to this?

dnsampaio updated this revision to Diff 208127.Jul 5 2019, 2:33 AM
  • Added tests
Harbormaster completed remote builds in B34413: Diff 208127.Jul 5 2019, 2:33 AM
dnsampaio retitled this revision from [ARM] Fix vector vuqadd intrinsics operands to [AArch64] Fix vector vuqadd intrinsics operands.Jul 5 2019, 3:45 AM
ostannard accepted this revision.Jul 10 2019, 2:33 AM
This revision is now accepted and ready to land.Jul 10 2019, 2:33 AM
Closed by commit rL365609: [AArch64] Fix vector vuqadd intrinsics operands (authored by dnsampaio). · Explain WhyJul 10 2019, 2:58 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptJul 10 2019, 2:58 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript

Revision Contents

PathSize
include/
clang/
Basic/
2 lines

Diff 208052

include/clang/Basic/arm_neon.td

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// saturating absolute/negate // saturating absolute/negate
def ABS : SInst<"vabs", "dd", "dQdlQl">; def ABS : SInst<"vabs", "dd", "dQdlQl">;
def QABS : SInst<"vqabs", "dd", "lQl">; def QABS : SInst<"vqabs", "dd", "lQl">;
def NEG : SOpInst<"vneg", "dd", "dlQdQl", OP_NEG>; def NEG : SOpInst<"vneg", "dd", "dlQdQl", OP_NEG>;
def QNEG : SInst<"vqneg", "dd", "lQl">; def QNEG : SInst<"vqneg", "dd", "lQl">;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Signed Saturating Accumulated of Unsigned Value // Signed Saturating Accumulated of Unsigned Value
def SUQADD : SInst<"vuqadd", "ddd", "csilQcQsQiQl">; def SUQADD : SInst<"vuqadd", "ddu", "csilQcQsQiQl">;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Unsigned Saturating Accumulated of Signed Value // Unsigned Saturating Accumulated of Signed Value
def USQADD : SInst<"vsqadd", "ddx", "UcUsUiUlQUcQUsQUiQUl">; def USQADD : SInst<"vsqadd", "ddx", "UcUsUiUlQUcQUsQUiQUl">;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Reciprocal/Sqrt // Reciprocal/Sqrt
def FRECPS : IInst<"vrecps", "ddd", "dQd">; def FRECPS : IInst<"vrecps", "ddd", "dQd">;
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