[NFC][AArch64] Fix vector vsqadd intrinsics operands

[dnsampaio]

Summary

Change the vsqadd vector instrinsics to have the second argument as signed values, not unsigned,
accordingly to https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics

[LukeCheeseman]

Are there some changes/addition to tests attached to this?

[dnsampaio]

In D64210#1570515, @LukeCheeseman wrote:

Are there some changes/addition to tests attached to this?

Hi,
I can see no difference in the CodeGen test in tools/clang/test/CodeGen/aarch64-neon-intrinsics.c, which already tests tests these intrinsics with the correct arguments. So technically speaking, it is a NFC.

include/clang/Basic/arm_neon.td

 def QNEG   : SInst<"vqneg", "dd", "lQl">;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Signed Saturating Accumulated of Unsigned Value
 def SUQADD : SInst<"vuqadd", "ddd", "csilQcQsQiQl">;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Unsigned Saturating Accumulated of Signed Value
-def USQADD : SInst<"vsqadd", "ddd", "UcUsUiUlQUcQUsQUiQUl">;
+def USQADD : SInst<"vsqadd", "ddx", "UcUsUiUlQUcQUsQUiQUl">;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Reciprocal/Sqrt
 def FRECPS  : IInst<"vrecps", "ddd", "dQd">;
 def FRSQRTS : IInst<"vrsqrts", "ddd", "dQd">;
 def FRECPE  : SInst<"vrecpe", "dd", "dQd">;
 def FRSQRTE : SInst<"vrsqrte", "dd", "dQd">;
 def FSQRT   : SInst<"vsqrt", "dd", "fdQfQd">;