This is an archive of the discontinued LLVM Phabricator instance.

Differential D64177

GlobalISel: fewerElementsVector for G_TRUNC
AbandonedPublic

Authored by arsenm on Jul 3 2019, 5:24 PM.

Details

Reviewers
dsanders
paquette
aemerson
aditya_nandakumar
Summary

Start defining AMDGPU legalize rules for G_TRUNC.

Diff Detail

Event Timeline

arsenm created this revision.Jul 3 2019, 5:24 PM
Herald added subscribers: Petar.Avramovic, volkan, tschuett and 5 others. · View Herald TranscriptJul 3 2019, 5:24 PM
aemerson added inline comments.Jul 8 2019, 4:42 PM
test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
64

Test still worthwhile having given it's now just a scalar artifact combine?

arsenm marked an inline comment as done.Jul 8 2019, 4:49 PM
arsenm added inline comments.
test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
64

I'm not even sure this patch is the right way to go. I'm still not 100% sure how to get the artifacts into the end state I want while maintaining valid MIR at every step. I had to drop this patch and make all vector truncates legal to get my G_BUILD_VECTOR lowerings to not infinite loop. Declaring every vector truncate legal almost kind of works assuming every use is legalized, but fails in some degenerate cases (like an implicit use on a target instruction)

arsenm marked an inline comment as done.Jul 10 2019, 7:25 AM
arsenm added inline comments.
test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
64

I think D64436 avoids these issues, so scalarizing trunc should work

arsenm marked an inline comment as done.Jul 10 2019, 7:51 AM
arsenm added inline comments.
test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
64

Maybe not, I'm still seeing some of these loops in another one of my branches

arsenm abandoned this revision.Feb 18 2020, 6:54 AM

Posted newer, better version

Herald added a subscriber: kerbowa. · View Herald TranscriptFeb 18 2020, 6:54 AM

Revision Contents

PathSize
lib/
CodeGen/
GlobalISel/
1 line
Target/
AMDGPU/
6 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
7 lines
27 lines
12 lines
69 lines
117 lines
68 lines
69 lines
88 lines
169 lines
69 lines

Diff 207935

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 2,262 Lines • ▼ Show 20 LinesLegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
case G_LSHR: case G_LSHR:
case G_ASHR: case G_ASHR:
case G_CTLZ: case G_CTLZ:
case G_CTLZ_ZERO_UNDEF: case G_CTLZ_ZERO_UNDEF:
case G_CTTZ: case G_CTTZ:
case G_CTTZ_ZERO_UNDEF: case G_CTTZ_ZERO_UNDEF:
case G_CTPOP: case G_CTPOP:
case G_FCOPYSIGN: case G_FCOPYSIGN:
case G_TRUNC:
return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy); return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
case G_ZEXT: case G_ZEXT:
case G_SEXT: case G_SEXT:
case G_ANYEXT: case G_ANYEXT:
case G_FPEXT: case G_FPEXT:
case G_FPTRUNC: case G_FPTRUNC:
case G_SITOFP: case G_SITOFP:
case G_UITOFP: case G_UITOFP:
▲ Show 20 Lines • Show All 900 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Lines auto GetAddrSpacePtr = [&TM](unsigned AS) {
return LLT::pointer(AS, TM.getPointerSizeInBits(AS)); return LLT::pointer(AS, TM.getPointerSizeInBits(AS));
}; };
const LLT S1 = LLT::scalar(1); const LLT S1 = LLT::scalar(1);
const LLT S8 = LLT::scalar(8); const LLT S8 = LLT::scalar(8);
const LLT S16 = LLT::scalar(16); const LLT S16 = LLT::scalar(16);
const LLT S32 = LLT::scalar(32); const LLT S32 = LLT::scalar(32);
const LLT S64 = LLT::scalar(64); const LLT S64 = LLT::scalar(64);
const LLT S96 = LLT::scalar(96);
const LLT S128 = LLT::scalar(128); const LLT S128 = LLT::scalar(128);
const LLT S256 = LLT::scalar(256); const LLT S256 = LLT::scalar(256);
const LLT S512 = LLT::scalar(512); const LLT S512 = LLT::scalar(512);
const LLT V2S16 = LLT::vector(2, 16); const LLT V2S16 = LLT::vector(2, 16);
const LLT V4S16 = LLT::vector(4, 16); const LLT V4S16 = LLT::vector(4, 16);
const LLT V2S32 = LLT::vector(2, 32); const LLT V2S32 = LLT::vector(2, 32);
▲ Show 20 Lines • Show All 190 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT}) getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
.legalFor({{S64, S32}, {S32, S16}, {S64, S16}, .legalFor({{S64, S32}, {S32, S16}, {S64, S16},
{S32, S1}, {S64, S1}, {S16, S1}, {S32, S1}, {S64, S1}, {S16, S1},
// FIXME: Hack // FIXME: Hack
{S64, LLT::scalar(33)}, {S64, LLT::scalar(33)},
{S32, S8}, {S128, S32}, {S128, S64}, {S32, LLT::scalar(24)}}) {S32, S8}, {S128, S32}, {S128, S64}, {S32, LLT::scalar(24)}})
.scalarize(0); .scalarize(0);
getActionDefinitionsBuilder(G_TRUNC)
.legalIf(typeInSet(1, {S32, S64, S96, S128, S256, S512}))
.scalarize(0);
getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
.legalFor({{S32, S32}, {S64, S32}}) .legalFor({{S32, S32}, {S64, S32}})
.lowerFor({{S32, S64}}) .lowerFor({{S32, S64}})
.customFor({{S64, S64}}) .customFor({{S64, S64}})
.scalarize(0); .scalarize(0);
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
.legalFor({{S32, S32}, {S32, S64}}) .legalFor({{S32, S32}, {S32, S64}})
▲ Show 20 Lines • Show All 931 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir

Show All 39 Lines
--- ---
name: test_anyext_trunc_v2s32_to_v2s8_to_v2s16 name: test_anyext_trunc_v2s32_to_v2s8_to_v2s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_anyext_trunc_v2s32_to_v2s8_to_v2s16 ; CHECK-LABEL: name: test_anyext_trunc_v2s32_to_v2s8_to_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: $vgpr0 = COPY [[TRUNC]](<2 x s16>) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s8>) = G_TRUNC %0 %1:_(<2 x s8>) = G_TRUNC %0
%2:_(<2 x s16>) = G_ANYEXT %1 %2:_(<2 x s16>) = G_ANYEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_anyext_trunc_v3s32_to_v3s16_to_v3s32 name: test_anyext_trunc_v3s32_to_v3s16_to_v3s32
Show All 13 Lines

test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
--- ---
name: test_sext_trunc_v2s32_to_v2s8_to_v2s16 name: test_sext_trunc_v2s32_to_v2s8_to_v2s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s8_to_v2s16 ; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s8_to_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
aemersonUnsubmitted
Not Done
ReplyInline Actions

Test still worthwhile having given it's now just a scalar artifact combine?

aemerson: Test still worthwhile having given it's now just a scalar artifact combine?
arsenmAuthorUnsubmitted
Done
ReplyInline Actions

I'm not even sure this patch is the right way to go. I'm still not 100% sure how to get the artifacts into the end state I want while maintaining valid MIR at every step. I had to drop this patch and make all vector truncates legal to get my G_BUILD_VECTOR lowerings to not infinite loop. Declaring every vector truncate legal almost kind of works assuming every use is legalized, but fails in some degenerate cases (like an implicit use on a target instruction)

arsenm: I'm not even sure this patch is the right way to go. I'm still not 100% sure how to get the…
arsenmAuthorUnsubmitted
Done
ReplyInline Actions

I think D64436 avoids these issues, so scalarizing trunc should work

arsenm: I think D64436 avoids these issues, so scalarizing trunc should work
arsenmAuthorUnsubmitted
Done
ReplyInline Actions

Maybe not, I'm still seeing some of these loops in another one of my branches

arsenm: Maybe not, I'm still seeing some of these loops in another one of my branches
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[TRUNC]], [[BUILD_VECTOR]](<2 x s16>) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s16>) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: $vgpr0 = COPY [[ASHR]](<2 x s16>) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[ZEXT]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[ZEXT1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC1]](s16)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT]], [[ZEXT2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC2]](s16)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT1]], [[ZEXT3]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](s16), [[TRUNC4]](s16)
; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s8>) = G_TRUNC %0 %1:_(<2 x s8>) = G_TRUNC %0
%2:_(<2 x s16>) = G_SEXT %1 %2:_(<2 x s16>) = G_SEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_sext_trunc_v3s32_to_v3s16_to_v3s32 name: test_sext_trunc_v3s32_to_v3s16_to_v3s32
Show All 22 Lines

test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
--- ---
name: test_zext_trunc_v2s32_to_v2s8_to_v2s16 name: test_zext_trunc_v2s32_to_v2s8_to_v2s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_zext_trunc_v2s32_to_v2s8_to_v2s16 ; CHECK-LABEL: name: test_zext_trunc_v2s32_to_v2s8_to_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC]](s16)
; CHECK: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[TRUNC]], [[BUILD_VECTOR]] ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](s16), [[TRUNC2]](s16)
; CHECK: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
; CHECK: $vgpr0 = COPY [[AND]](<2 x s16>) ; CHECK: $vgpr0 = COPY [[AND]](<2 x s16>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s8>) = G_TRUNC %0 %1:_(<2 x s8>) = G_TRUNC %0
%2:_(<2 x s16>) = G_ZEXT %1 %2:_(<2 x s16>) = G_ZEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
Show All 25 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir

Show First 20 Lines • Show All 394 Lines • ▼ Show 20 Lines
--- ---
name: test_and_v5s16 name: test_and_v5s16
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_and_v5s16 ; CHECK-LABEL: name: test_and_v5s16
; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF]](<6 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<6 x s32>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[TRUNC]](<6 x s16>), 0 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV4]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV5]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16), [[TRUNC4]](s16), [[TRUNC5]](s16)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[BUILD_VECTOR]](<6 x s16>), 0
; CHECK: [[DEF1:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC1:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF1]](<6 x s32>) ; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<6 x s32>)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[TRUNC1]](<6 x s16>), 0 ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[UV6]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[UV8]](s32)
; CHECK: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[UV9]](s32)
; CHECK: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[UV10]](s32)
; CHECK: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[UV11]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC6]](s16), [[TRUNC7]](s16), [[TRUNC8]](s16), [[TRUNC9]](s16), [[TRUNC10]](s16), [[TRUNC11]](s16)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[BUILD_VECTOR1]](<6 x s16>), 0
; CHECK: [[DEF2:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF2:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC2:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF2]](<6 x s32>) ; CHECK: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF2]](<6 x s32>)
; CHECK: [[INSERT:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[TRUNC2]], [[EXTRACT]](<5 x s16>), 0 ; CHECK: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[UV12]](s32)
; CHECK: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[UV13]](s32)
; CHECK: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[UV14]](s32)
; CHECK: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[UV15]](s32)
; CHECK: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[UV16]](s32)
; CHECK: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[UV17]](s32)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC12]](s16), [[TRUNC13]](s16), [[TRUNC14]](s16), [[TRUNC15]](s16), [[TRUNC16]](s16), [[TRUNC17]](s16)
; CHECK: [[INSERT:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[BUILD_VECTOR2]], [[EXTRACT]](<5 x s16>), 0
; CHECK: [[DEF3:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF3:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC3:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF3]](<6 x s32>) ; CHECK: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF3]](<6 x s32>)
; CHECK: [[INSERT1:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[TRUNC3]], [[EXTRACT1]](<5 x s16>), 0 ; CHECK: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[UV18]](s32)
; CHECK: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[INSERT]](<6 x s16>) ; CHECK: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[UV19]](s32)
; CHECK: [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<6 x s16>) ; CHECK: [[TRUNC20:%[0-9]+]]:_(s16) = G_TRUNC [[UV20]](s32)
; CHECK: [[TRUNC21:%[0-9]+]]:_(s16) = G_TRUNC [[UV21]](s32)
; CHECK: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[UV22]](s32)
; CHECK: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[UV23]](s32)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC18]](s16), [[TRUNC19]](s16), [[TRUNC20]](s16), [[TRUNC21]](s16), [[TRUNC22]](s16), [[TRUNC23]](s16)
; CHECK: [[INSERT1:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[BUILD_VECTOR3]], [[EXTRACT1]](<5 x s16>), 0
; CHECK: [[UV24:%[0-9]+]]:_(<3 x s16>), [[UV25:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[INSERT]](<6 x s16>)
; CHECK: [[UV26:%[0-9]+]]:_(<3 x s16>), [[UV27:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<6 x s16>)
; CHECK: [[DEF4:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF4:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF4]], [[UV]](<3 x s16>), 0 ; CHECK: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF4]], [[UV24]](<3 x s16>), 0
; CHECK: [[DEF5:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF5:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF5]], [[UV2]](<3 x s16>), 0 ; CHECK: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF5]], [[UV26]](<3 x s16>), 0
; CHECK: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[INSERT2]], [[INSERT3]] ; CHECK: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[INSERT2]], [[INSERT3]]
; CHECK: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[AND]](<4 x s16>), 0 ; CHECK: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[AND]](<4 x s16>), 0
; CHECK: [[DEF6:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF6:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT4:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF6]], [[UV1]](<3 x s16>), 0 ; CHECK: [[INSERT4:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF6]], [[UV25]](<3 x s16>), 0
; CHECK: [[DEF7:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF7:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT5:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF7]], [[UV3]](<3 x s16>), 0 ; CHECK: [[INSERT5:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF7]], [[UV27]](<3 x s16>), 0
; CHECK: [[AND1:%[0-9]+]]:_(<4 x s16>) = G_AND [[INSERT4]], [[INSERT5]] ; CHECK: [[AND1:%[0-9]+]]:_(<4 x s16>) = G_AND [[INSERT4]], [[INSERT5]]
; CHECK: [[EXTRACT3:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[AND1]](<4 x s16>), 0 ; CHECK: [[EXTRACT3:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[AND1]](<4 x s16>), 0
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT2]](<3 x s16>), [[EXTRACT3]](<3 x s16>) ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT2]](<3 x s16>), [[EXTRACT3]](<3 x s16>)
; CHECK: [[EXTRACT4:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0 ; CHECK: [[EXTRACT4:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
; CHECK: [[DEF8:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF8:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC4:%[0-9]+]]:_(<8 x s16>) = G_TRUNC [[DEF8]](<8 x s32>) ; CHECK: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF8]](<8 x s32>)
; CHECK: [[INSERT6:%[0-9]+]]:_(<8 x s16>) = G_INSERT [[TRUNC4]], [[EXTRACT4]](<5 x s16>), 0 ; CHECK: [[TRUNC24:%[0-9]+]]:_(s16) = G_TRUNC [[UV28]](s32)
; CHECK: [[TRUNC25:%[0-9]+]]:_(s16) = G_TRUNC [[UV29]](s32)
; CHECK: [[TRUNC26:%[0-9]+]]:_(s16) = G_TRUNC [[UV30]](s32)
; CHECK: [[TRUNC27:%[0-9]+]]:_(s16) = G_TRUNC [[UV31]](s32)
; CHECK: [[TRUNC28:%[0-9]+]]:_(s16) = G_TRUNC [[UV32]](s32)
; CHECK: [[TRUNC29:%[0-9]+]]:_(s16) = G_TRUNC [[UV33]](s32)
; CHECK: [[TRUNC30:%[0-9]+]]:_(s16) = G_TRUNC [[UV34]](s32)
; CHECK: [[TRUNC31:%[0-9]+]]:_(s16) = G_TRUNC [[UV35]](s32)
; CHECK: [[BUILD_VECTOR4:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[TRUNC24]](s16), [[TRUNC25]](s16), [[TRUNC26]](s16), [[TRUNC27]](s16), [[TRUNC28]](s16), [[TRUNC29]](s16), [[TRUNC30]](s16), [[TRUNC31]](s16)
; CHECK: [[INSERT6:%[0-9]+]]:_(<8 x s16>) = G_INSERT [[BUILD_VECTOR4]], [[EXTRACT4]](<5 x s16>), 0
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT6]](<8 x s16>) ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT6]](<8 x s16>)
%0:_(<5 x s16>) = G_IMPLICIT_DEF %0:_(<5 x s16>) = G_IMPLICIT_DEF
%1:_(<5 x s16>) = G_IMPLICIT_DEF %1:_(<5 x s16>) = G_IMPLICIT_DEF
%2:_(<5 x s16>) = G_AND %0, %1 %2:_(<5 x s16>) = G_AND %0, %1
%3:_(<8 x s16>) = G_IMPLICIT_DEF %3:_(<8 x s16>) = G_IMPLICIT_DEF
%4:_(<8 x s16>) = G_INSERT %3, %2, 0 %4:_(<8 x s16>) = G_INSERT %3, %2, 0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4
... ...
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir

Show First 20 Lines • Show All 441 Lines • ▼ Show 20 Lines
... ...
--- ---
name: extract_s8_v4s8_offset0 name: extract_s8_v4s8_offset0
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: extract_s8_v4s8_offset0 ; CHECK-LABEL: name: extract_s8_v4s8_offset0
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF]](<4 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC]](<4 x s8>) ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[ANYEXT]](<4 x s16>), 0 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[EXTRACT]](s16) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s8) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[UV3]](s32)
; CHECK: $vgpr0 = COPY [[ANYEXT1]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s8>) = G_BUILD_VECTOR [[TRUNC]](s8), [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8)
; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s8>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s8)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV5]](s8)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[ANYEXT3]](s16)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[BUILD_VECTOR1]](<4 x s16>), 0
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT4]](s32)
%0:_(<4 x s8>) = G_IMPLICIT_DEF %0:_(<4 x s8>) = G_IMPLICIT_DEF
%1:_(s8) = G_EXTRACT %0, 0 %1:_(s8) = G_EXTRACT %0, 0
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: extract_s8_v4s8_offset8 name: extract_s8_v4s8_offset8
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: extract_s8_v4s8_offset8 ; CHECK-LABEL: name: extract_s8_v4s8_offset8
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF]](<4 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC]](<4 x s8>) ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[ANYEXT]](<4 x s16>), 16 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[EXTRACT]](s16) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s8) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[UV3]](s32)
; CHECK: $vgpr0 = COPY [[ANYEXT1]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s8>) = G_BUILD_VECTOR [[TRUNC]](s8), [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8)
; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s8>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s8)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV5]](s8)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[ANYEXT3]](s16)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[BUILD_VECTOR1]](<4 x s16>), 16
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT4]](s32)
%0:_(<4 x s8>) = G_IMPLICIT_DEF %0:_(<4 x s8>) = G_IMPLICIT_DEF
%1:_(s8) = G_EXTRACT %0, 8 %1:_(s8) = G_EXTRACT %0, 8
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: extract_s8_v4s8_offset16 name: extract_s8_v4s8_offset16
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: extract_s8_v4s8_offset16 ; CHECK-LABEL: name: extract_s8_v4s8_offset16
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF]](<4 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC]](<4 x s8>) ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[ANYEXT]](<4 x s16>), 32 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[EXTRACT]](s16) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s8) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[UV3]](s32)
; CHECK: $vgpr0 = COPY [[ANYEXT1]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s8>) = G_BUILD_VECTOR [[TRUNC]](s8), [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8)
; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s8>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s8)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV5]](s8)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[ANYEXT3]](s16)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[BUILD_VECTOR1]](<4 x s16>), 32
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT4]](s32)
%0:_(<4 x s8>) = G_IMPLICIT_DEF %0:_(<4 x s8>) = G_IMPLICIT_DEF
%1:_(s8) = G_EXTRACT %0, 16 %1:_(s8) = G_EXTRACT %0, 16
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: extract_s8_v4s8_offset24 name: extract_s8_v4s8_offset24
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: extract_s8_v4s8_offset24 ; CHECK-LABEL: name: extract_s8_v4s8_offset24
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF]](<4 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC]](<4 x s8>) ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[ANYEXT]](<4 x s16>), 48 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[EXTRACT]](s16) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s8) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[UV3]](s32)
; CHECK: $vgpr0 = COPY [[ANYEXT1]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s8>) = G_BUILD_VECTOR [[TRUNC]](s8), [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8)
; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s8>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s8)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV5]](s8)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[ANYEXT3]](s16)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[BUILD_VECTOR1]](<4 x s16>), 48
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT4]](s32)
%0:_(<4 x s8>) = G_IMPLICIT_DEF %0:_(<4 x s8>) = G_IMPLICIT_DEF
%1:_(s8) = G_EXTRACT %0, 24 %1:_(s8) = G_EXTRACT %0, 24
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: extract_s8_v3s8_offset16 name: extract_s8_v3s8_offset16
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
... ...
--- ---
name: extract_v2s16_v6s16_offset32 name: extract_v2s16_v6s16_offset32
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: extract_v2s16_v6s16_offset32 ; CHECK-LABEL: name: extract_v2s16_v6s16_offset32
; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF]](<6 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<6 x s32>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[TRUNC]](<6 x s16>), 32 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV4]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV5]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16), [[TRUNC4]](s16), [[TRUNC5]](s16)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[BUILD_VECTOR]](<6 x s16>), 32
; CHECK: $vgpr0 = COPY [[EXTRACT]](<2 x s16>) ; CHECK: $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
%0:_(<6 x s16>) = G_IMPLICIT_DEF %0:_(<6 x s16>) = G_IMPLICIT_DEF
%1:_(<2 x s16>) = G_EXTRACT %0, 32 %1:_(<2 x s16>) = G_EXTRACT %0, 32
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: test_extract_s8_s16_offset0 name: test_extract_s8_s16_offset0
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
--- ---
name: extract_v2s16_v5s16_offset0 name: extract_v2s16_v5s16_offset0
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: extract_v2s16_v5s16_offset0 ; CHECK-LABEL: name: extract_v2s16_v5s16_offset0
; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF]](<6 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<6 x s32>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[TRUNC]](<6 x s16>), 0 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV4]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV5]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16), [[TRUNC4]](s16), [[TRUNC5]](s16)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[BUILD_VECTOR]](<6 x s16>), 0
; CHECK: [[DEF1:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC1:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF1]](<6 x s32>) ; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<6 x s32>)
; CHECK: [[INSERT:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[TRUNC1]], [[EXTRACT]](<5 x s16>), 0 ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[UV6]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[UV8]](s32)
; CHECK: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[UV9]](s32)
; CHECK: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[UV10]](s32)
; CHECK: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[UV11]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC6]](s16), [[TRUNC7]](s16), [[TRUNC8]](s16), [[TRUNC9]](s16), [[TRUNC10]](s16), [[TRUNC11]](s16)
; CHECK: [[INSERT:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[BUILD_VECTOR1]], [[EXTRACT]](<5 x s16>), 0
; CHECK: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<6 x s16>), 0 ; CHECK: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<6 x s16>), 0
; CHECK: $vgpr0 = COPY [[EXTRACT1]](<2 x s16>) ; CHECK: $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
%0:_(<5 x s16>) = G_IMPLICIT_DEF %0:_(<5 x s16>) = G_IMPLICIT_DEF
%1:_(<2 x s16>) = G_EXTRACT %0, 0 %1:_(<2 x s16>) = G_EXTRACT %0, 0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...

test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir

Show First 20 Lines • Show All 408 Lines • ▼ Show 20 Lines
--- ---
name: test_implicit_def_v5s16 name: test_implicit_def_v5s16
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_implicit_def_v5s16 ; CHECK-LABEL: name: test_implicit_def_v5s16
; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF]](<6 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<6 x s32>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[TRUNC]](<6 x s16>), 0 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV4]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV5]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16), [[TRUNC4]](s16), [[TRUNC5]](s16)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[BUILD_VECTOR]](<6 x s16>), 0
; CHECK: [[DEF1:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC1:%[0-9]+]]:_(<8 x s16>) = G_TRUNC [[DEF1]](<8 x s32>) ; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
; CHECK: [[INSERT:%[0-9]+]]:_(<8 x s16>) = G_INSERT [[TRUNC1]], [[EXTRACT]](<5 x s16>), 0 ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[UV6]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[UV8]](s32)
; CHECK: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[UV9]](s32)
; CHECK: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[UV10]](s32)
; CHECK: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[UV11]](s32)
; CHECK: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[UV12]](s32)
; CHECK: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[UV13]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[TRUNC6]](s16), [[TRUNC7]](s16), [[TRUNC8]](s16), [[TRUNC9]](s16), [[TRUNC10]](s16), [[TRUNC11]](s16), [[TRUNC12]](s16), [[TRUNC13]](s16)
; CHECK: [[INSERT:%[0-9]+]]:_(<8 x s16>) = G_INSERT [[BUILD_VECTOR1]], [[EXTRACT]](<5 x s16>), 0
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](<8 x s16>) ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](<8 x s16>)
%0:_(<5 x s16>) = G_IMPLICIT_DEF %0:_(<5 x s16>) = G_IMPLICIT_DEF
%1:_(<8 x s16>) = G_IMPLICIT_DEF %1:_(<8 x s16>) = G_IMPLICIT_DEF
%2:_(<8 x s16>) = G_INSERT %1, %0, 0 %2:_(<8 x s16>) = G_INSERT %1, %0, 0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
... ...
--- ---
name: test_implicit_def_v6s16 name: test_implicit_def_v6s16
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_implicit_def_v6s16 ; CHECK-LABEL: name: test_implicit_def_v6s16
; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF]](<6 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<6 x s32>)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV4]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV5]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16), [[TRUNC4]](s16), [[TRUNC5]](s16)
; CHECK: [[DEF1:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC1:%[0-9]+]]:_(<8 x s16>) = G_TRUNC [[DEF1]](<8 x s32>) ; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
; CHECK: [[INSERT:%[0-9]+]]:_(<8 x s16>) = G_INSERT [[TRUNC1]], [[TRUNC]](<6 x s16>), 0 ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[UV6]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[UV8]](s32)
; CHECK: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[UV9]](s32)
; CHECK: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[UV10]](s32)
; CHECK: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[UV11]](s32)
; CHECK: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[UV12]](s32)
; CHECK: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[UV13]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[TRUNC6]](s16), [[TRUNC7]](s16), [[TRUNC8]](s16), [[TRUNC9]](s16), [[TRUNC10]](s16), [[TRUNC11]](s16), [[TRUNC12]](s16), [[TRUNC13]](s16)
; CHECK: [[INSERT:%[0-9]+]]:_(<8 x s16>) = G_INSERT [[BUILD_VECTOR1]], [[BUILD_VECTOR]](<6 x s16>), 0
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](<8 x s16>) ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT]](<8 x s16>)
%0:_(<6 x s16>) = G_IMPLICIT_DEF %0:_(<6 x s16>) = G_IMPLICIT_DEF
%1:_(<8 x s16>) = G_IMPLICIT_DEF %1:_(<8 x s16>) = G_IMPLICIT_DEF
%2:_(<8 x s16>) = G_INSERT %1, %0, 0 %2:_(<8 x s16>) = G_INSERT %1, %0, 0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
... ...
--- ---
name: test_implicit_def_v8s16 name: test_implicit_def_v8s16
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_implicit_def_v8s16 ; CHECK-LABEL: name: test_implicit_def_v8s16
; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s16>) = G_TRUNC [[DEF]](<8 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[TRUNC]](<8 x s16>) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV4]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV5]](s32)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[UV6]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16), [[TRUNC4]](s16), [[TRUNC5]](s16), [[TRUNC6]](s16), [[TRUNC7]](s16)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<8 x s16>)
%0:_(<8 x s16>) = G_IMPLICIT_DEF %0:_(<8 x s16>) = G_IMPLICIT_DEF
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %0 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %0
... ...
--- ---
name: test_implicit_def_v2s64 name: test_implicit_def_v2s64
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_implicit_def_v2s64 ; CHECK-LABEL: name: test_implicit_def_v2s64
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[DEF]](<2 x s64>) ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[DEF]](<2 x s64>)
%0:_(<2 x s64>) = G_IMPLICIT_DEF %0:_(<2 x s64>) = G_IMPLICIT_DEF
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %0 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %0
... ...
--- ---
name: test_implicit_def_v4s8 name: test_implicit_def_v4s8
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_implicit_def_v4s8 ; CHECK-LABEL: name: test_implicit_def_v4s8
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF]](<4 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
; CHECK: $vgpr0 = COPY [[TRUNC]](<4 x s8>) ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[UV3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s8>) = G_BUILD_VECTOR [[TRUNC]](s8), [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8)
; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<4 x s8>)
%0:_(<4 x s8>) = G_IMPLICIT_DEF %0:_(<4 x s8>) = G_IMPLICIT_DEF
$vgpr0 = COPY %0 $vgpr0 = COPY %0
... ...
--- ---
name: test_implicit_def_p0 name: test_implicit_def_p0
body: | body: |
bb.0: bb.0:
▲ Show 20 Lines • Show All 79 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir

Show First 20 Lines • Show All 394 Lines • ▼ Show 20 Lines
--- ---
name: test_or_v5s16 name: test_or_v5s16
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_or_v5s16 ; CHECK-LABEL: name: test_or_v5s16
; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF]](<6 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<6 x s32>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[TRUNC]](<6 x s16>), 0 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV4]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV5]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16), [[TRUNC4]](s16), [[TRUNC5]](s16)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[BUILD_VECTOR]](<6 x s16>), 0
; CHECK: [[DEF1:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC1:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF1]](<6 x s32>) ; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<6 x s32>)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[TRUNC1]](<6 x s16>), 0 ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[UV6]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[UV8]](s32)
; CHECK: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[UV9]](s32)
; CHECK: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[UV10]](s32)
; CHECK: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[UV11]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC6]](s16), [[TRUNC7]](s16), [[TRUNC8]](s16), [[TRUNC9]](s16), [[TRUNC10]](s16), [[TRUNC11]](s16)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[BUILD_VECTOR1]](<6 x s16>), 0
; CHECK: [[DEF2:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF2:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC2:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF2]](<6 x s32>) ; CHECK: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF2]](<6 x s32>)
; CHECK: [[INSERT:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[TRUNC2]], [[EXTRACT]](<5 x s16>), 0 ; CHECK: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[UV12]](s32)
; CHECK: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[UV13]](s32)
; CHECK: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[UV14]](s32)
; CHECK: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[UV15]](s32)
; CHECK: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[UV16]](s32)
; CHECK: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[UV17]](s32)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC12]](s16), [[TRUNC13]](s16), [[TRUNC14]](s16), [[TRUNC15]](s16), [[TRUNC16]](s16), [[TRUNC17]](s16)
; CHECK: [[INSERT:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[BUILD_VECTOR2]], [[EXTRACT]](<5 x s16>), 0
; CHECK: [[DEF3:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF3:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC3:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF3]](<6 x s32>) ; CHECK: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF3]](<6 x s32>)
; CHECK: [[INSERT1:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[TRUNC3]], [[EXTRACT1]](<5 x s16>), 0 ; CHECK: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[UV18]](s32)
; CHECK: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[INSERT]](<6 x s16>) ; CHECK: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[UV19]](s32)
; CHECK: [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<6 x s16>) ; CHECK: [[TRUNC20:%[0-9]+]]:_(s16) = G_TRUNC [[UV20]](s32)
; CHECK: [[TRUNC21:%[0-9]+]]:_(s16) = G_TRUNC [[UV21]](s32)
; CHECK: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[UV22]](s32)
; CHECK: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[UV23]](s32)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC18]](s16), [[TRUNC19]](s16), [[TRUNC20]](s16), [[TRUNC21]](s16), [[TRUNC22]](s16), [[TRUNC23]](s16)
; CHECK: [[INSERT1:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[BUILD_VECTOR3]], [[EXTRACT1]](<5 x s16>), 0
; CHECK: [[UV24:%[0-9]+]]:_(<3 x s16>), [[UV25:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[INSERT]](<6 x s16>)
; CHECK: [[UV26:%[0-9]+]]:_(<3 x s16>), [[UV27:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<6 x s16>)
; CHECK: [[DEF4:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF4:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF4]], [[UV]](<3 x s16>), 0 ; CHECK: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF4]], [[UV24]](<3 x s16>), 0
; CHECK: [[DEF5:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF5:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF5]], [[UV2]](<3 x s16>), 0 ; CHECK: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF5]], [[UV26]](<3 x s16>), 0
; CHECK: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[INSERT2]], [[INSERT3]] ; CHECK: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[INSERT2]], [[INSERT3]]
; CHECK: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[OR]](<4 x s16>), 0 ; CHECK: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[OR]](<4 x s16>), 0
; CHECK: [[DEF6:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF6:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT4:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF6]], [[UV1]](<3 x s16>), 0 ; CHECK: [[INSERT4:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF6]], [[UV25]](<3 x s16>), 0
; CHECK: [[DEF7:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF7:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT5:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF7]], [[UV3]](<3 x s16>), 0 ; CHECK: [[INSERT5:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF7]], [[UV27]](<3 x s16>), 0
; CHECK: [[OR1:%[0-9]+]]:_(<4 x s16>) = G_OR [[INSERT4]], [[INSERT5]] ; CHECK: [[OR1:%[0-9]+]]:_(<4 x s16>) = G_OR [[INSERT4]], [[INSERT5]]
; CHECK: [[EXTRACT3:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[OR1]](<4 x s16>), 0 ; CHECK: [[EXTRACT3:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[OR1]](<4 x s16>), 0
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT2]](<3 x s16>), [[EXTRACT3]](<3 x s16>) ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT2]](<3 x s16>), [[EXTRACT3]](<3 x s16>)
; CHECK: [[EXTRACT4:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0 ; CHECK: [[EXTRACT4:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
; CHECK: [[DEF8:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF8:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC4:%[0-9]+]]:_(<8 x s16>) = G_TRUNC [[DEF8]](<8 x s32>) ; CHECK: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF8]](<8 x s32>)
; CHECK: [[INSERT6:%[0-9]+]]:_(<8 x s16>) = G_INSERT [[TRUNC4]], [[EXTRACT4]](<5 x s16>), 0 ; CHECK: [[TRUNC24:%[0-9]+]]:_(s16) = G_TRUNC [[UV28]](s32)
; CHECK: [[TRUNC25:%[0-9]+]]:_(s16) = G_TRUNC [[UV29]](s32)
; CHECK: [[TRUNC26:%[0-9]+]]:_(s16) = G_TRUNC [[UV30]](s32)
; CHECK: [[TRUNC27:%[0-9]+]]:_(s16) = G_TRUNC [[UV31]](s32)
; CHECK: [[TRUNC28:%[0-9]+]]:_(s16) = G_TRUNC [[UV32]](s32)
; CHECK: [[TRUNC29:%[0-9]+]]:_(s16) = G_TRUNC [[UV33]](s32)
; CHECK: [[TRUNC30:%[0-9]+]]:_(s16) = G_TRUNC [[UV34]](s32)
; CHECK: [[TRUNC31:%[0-9]+]]:_(s16) = G_TRUNC [[UV35]](s32)
; CHECK: [[BUILD_VECTOR4:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[TRUNC24]](s16), [[TRUNC25]](s16), [[TRUNC26]](s16), [[TRUNC27]](s16), [[TRUNC28]](s16), [[TRUNC29]](s16), [[TRUNC30]](s16), [[TRUNC31]](s16)
; CHECK: [[INSERT6:%[0-9]+]]:_(<8 x s16>) = G_INSERT [[BUILD_VECTOR4]], [[EXTRACT4]](<5 x s16>), 0
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT6]](<8 x s16>) ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT6]](<8 x s16>)
%0:_(<5 x s16>) = G_IMPLICIT_DEF %0:_(<5 x s16>) = G_IMPLICIT_DEF
%1:_(<5 x s16>) = G_IMPLICIT_DEF %1:_(<5 x s16>) = G_IMPLICIT_DEF
%2:_(<5 x s16>) = G_OR %0, %1 %2:_(<5 x s16>) = G_OR %0, %1
%3:_(<8 x s16>) = G_IMPLICIT_DEF %3:_(<8 x s16>) = G_IMPLICIT_DEF
%4:_(<8 x s16>) = G_INSERT %3, %2, 0 %4:_(<8 x s16>) = G_INSERT %3, %2, 0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4
... ...
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir

Show First 20 Lines • Show All 226 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4 liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
; CHECK-LABEL: name: test_select_v2s8 ; CHECK-LABEL: name: test_select_v2s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr1_vgpr2 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr3_vgpr4 ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr3_vgpr4
; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s8>) = G_TRUNC [[COPY1]](<2 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[TRUNC1:%[0-9]+]]:_(<2 x s8>) = G_TRUNC [[COPY2]](<2 x s32>) ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s8>) = G_BUILD_VECTOR [[TRUNC]](s8), [[TRUNC1]](s8)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[UV3]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s8>) = G_BUILD_VECTOR [[TRUNC2]](s8), [[TRUNC3]](s8)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](<2 x s8>) ; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s8>)
; CHECK: [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC1]](<2 x s8>) ; CHECK: [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<2 x s8>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s8)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8) ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT]], [[ANYEXT1]] ; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT]], [[ANYEXT1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT]](s16) ; CHECK: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8) ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV5]](s8)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s8) ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8)
; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT2]], [[ANYEXT3]] ; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT2]], [[ANYEXT3]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT1]](s16) ; CHECK: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT1]](s16)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s8>) = G_BUILD_VECTOR [[TRUNC2]](s8), [[TRUNC3]](s8) ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s8>) = G_BUILD_VECTOR [[TRUNC4]](s8), [[TRUNC5]](s8)
; CHECK: [[ANYEXT4:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT [[BUILD_VECTOR]](<2 x s8>) ; CHECK: [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<2 x s8>)
; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT4]](<2 x s32>) ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV9]](s8)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT4]](s32), [[ANYEXT5]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR3]](<2 x s32>)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 0 %1:_(s32) = G_CONSTANT i32 0
%2:_(<2 x s32>) = COPY $vgpr1_vgpr2 %2:_(<2 x s32>) = COPY $vgpr1_vgpr2
%3:_(<2 x s32>) = COPY $vgpr3_vgpr4 %3:_(<2 x s32>) = COPY $vgpr3_vgpr4
%4:_(<2 x s8>) = G_TRUNC %2 %4:_(<2 x s8>) = G_TRUNC %2
%5:_(<2 x s8>) = G_TRUNC %3 %5:_(<2 x s8>) = G_TRUNC %3
%6:_(s1) = G_ICMP intpred(ne), %0, %1 %6:_(s1) = G_ICMP intpred(ne), %0, %1
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8 liveins: $vgpr0, $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK-LABEL: name: test_select_v4s8 ; CHECK-LABEL: name: test_select_v4s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8 ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[COPY1]](<4 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[COPY2]](<4 x s32>) ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[UV3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s8>) = G_BUILD_VECTOR [[TRUNC]](s8), [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8)
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[UV4]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[UV5]](s32)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[UV6]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[UV7]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s8>) = G_BUILD_VECTOR [[TRUNC4]](s8), [[TRUNC5]](s8), [[TRUNC6]](s8), [[TRUNC7]](s8)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](<4 x s8>) ; CHECK: [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s8>)
; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC1]](<4 x s8>) ; CHECK: [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s8>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV8]](s8)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s8) ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV12]](s8)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT]], [[ANYEXT1]] ; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT]], [[ANYEXT1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT]](s16) ; CHECK: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8) ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV9]](s8)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV5]](s8) ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV13]](s8)
; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT2]], [[ANYEXT3]] ; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT2]], [[ANYEXT3]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT1]](s16) ; CHECK: [[TRUNC9:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT1]](s16)
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8) ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s16) = G_ANYEXT [[UV10]](s8)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8) ; CHECK: [[ANYEXT5:%[0-9]+]]:_(s16) = G_ANYEXT [[UV14]](s8)
; CHECK: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT4]], [[ANYEXT5]] ; CHECK: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT4]], [[ANYEXT5]]
; CHECK: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT2]](s16) ; CHECK: [[TRUNC10:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT2]](s16)
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s8) ; CHECK: [[ANYEXT6:%[0-9]+]]:_(s16) = G_ANYEXT [[UV11]](s8)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8) ; CHECK: [[ANYEXT7:%[0-9]+]]:_(s16) = G_ANYEXT [[UV15]](s8)
; CHECK: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT6]], [[ANYEXT7]] ; CHECK: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT6]], [[ANYEXT7]]
; CHECK: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT3]](s16) ; CHECK: [[TRUNC11:%[0-9]+]]:_(s8) = G_TRUNC [[SELECT3]](s16)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s8>) = G_BUILD_VECTOR [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[TRUNC5]](s8) ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s8>) = G_BUILD_VECTOR [[TRUNC8]](s8), [[TRUNC9]](s8), [[TRUNC10]](s8), [[TRUNC11]](s8)
; CHECK: [[ANYEXT8:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[BUILD_VECTOR]](<4 x s8>) ; CHECK: [[UV16:%[0-9]+]]:_(s8), [[UV17:%[0-9]+]]:_(s8), [[UV18:%[0-9]+]]:_(s8), [[UV19:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<4 x s8>)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[ANYEXT8]](<4 x s32>) ; CHECK: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[UV16]](s8)
; CHECK: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[UV17]](s8)
; CHECK: [[ANYEXT10:%[0-9]+]]:_(s32) = G_ANYEXT [[UV18]](s8)
; CHECK: [[ANYEXT11:%[0-9]+]]:_(s32) = G_ANYEXT [[UV19]](s8)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ANYEXT8]](s32), [[ANYEXT9]](s32), [[ANYEXT10]](s32), [[ANYEXT11]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR3]](<4 x s32>)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 0 %1:_(s32) = G_CONSTANT i32 0
%2:_(<4 x s32>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4 %2:_(<4 x s32>) = COPY $vgpr1_vgpr2_vgpr3_vgpr4
%3:_(<4 x s32>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8 %3:_(<4 x s32>) = COPY $vgpr5_vgpr6_vgpr7_vgpr8
%4:_(<4 x s8>) = G_TRUNC %2 %4:_(<4 x s8>) = G_TRUNC %2
%5:_(<4 x s8>) = G_TRUNC %3 %5:_(<4 x s8>) = G_TRUNC %3
%6:_(s1) = G_ICMP intpred(ne), %0, %1 %6:_(s1) = G_ICMP intpred(ne), %0, %1
▲ Show 20 Lines • Show All 841 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_trunc_s64_to_s32
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_trunc_s64_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_TRUNC %0
$vgpr0 = COPY %1
...
---
name: test_trunc_v2s64_to_v2s32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-LABEL: name: test_trunc_v2s64_to_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[TRUNC]](s32), [[TRUNC1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s32>) = G_TRUNC %0
$vgpr0_vgpr1 = COPY %1
...
---
name: test_trunc_v2s32_to_v2s16
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_trunc_v2s32_to_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = G_TRUNC %0
$vgpr0 = COPY %1
...
---
name: test_trunc_s32_to_s1
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_trunc_s32_to_s1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
; CHECK: S_NOP 0, implicit [[TRUNC]](s1)
%0:_(s32) = COPY $vgpr0
%1:_(s1) = G_TRUNC %0
S_NOP 0, implicit %1
...
---
name: test_trunc_s32_to_s2
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_trunc_s32_to_s2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s2) = G_TRUNC [[COPY]](s32)
; CHECK: S_NOP 0, implicit [[TRUNC]](s2)
%0:_(s32) = COPY $vgpr0
%1:_(s2) = G_TRUNC %0
S_NOP 0, implicit %1
...
---
name: test_trunc_s32_to_s16
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_trunc_s32_to_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: S_NOP 0, implicit [[TRUNC]](s16)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
S_NOP 0, implicit %1
...
---
name: test_trunc_s64_to_s16
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_trunc_s64_to_s16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
; CHECK: S_NOP 0, implicit [[TRUNC]](s16)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_TRUNC %0
S_NOP 0, implicit %1
...
---
name: test_trunc_s96_to_s32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2
; CHECK-LABEL: name: test_trunc_s96_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s96)
; CHECK: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_TRUNC %0
$vgpr0 = COPY %1
...
---
name: test_trunc_s128_to_s32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-LABEL: name: test_trunc_s128_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
; CHECK: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_TRUNC %0
$vgpr0 = COPY %1
...
---
name: test_trunc_s256_to_s128
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-LABEL: name: test_trunc_s256_to_s128
; CHECK: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s256)
; CHECK: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:_(s32) = G_TRUNC %0
$vgpr0 = COPY %1
...
---
name: test_trunc_s512_to_s256
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
%0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
%1:_(s256) = G_TRUNC %0
S_NOP 0, implicit %1
...

test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir

Show First 20 Lines • Show All 394 Lines • ▼ Show 20 Lines
--- ---
name: test_xor_v5s16 name: test_xor_v5s16
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_xor_v5s16 ; CHECK-LABEL: name: test_xor_v5s16
; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF]](<6 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<6 x s32>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[TRUNC]](<6 x s16>), 0 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV4]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV5]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16), [[TRUNC4]](s16), [[TRUNC5]](s16)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[BUILD_VECTOR]](<6 x s16>), 0
; CHECK: [[DEF1:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC1:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF1]](<6 x s32>) ; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<6 x s32>)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[TRUNC1]](<6 x s16>), 0 ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[UV6]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[UV8]](s32)
; CHECK: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[UV9]](s32)
; CHECK: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[UV10]](s32)
; CHECK: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[UV11]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC6]](s16), [[TRUNC7]](s16), [[TRUNC8]](s16), [[TRUNC9]](s16), [[TRUNC10]](s16), [[TRUNC11]](s16)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[BUILD_VECTOR1]](<6 x s16>), 0
; CHECK: [[DEF2:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF2:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC2:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF2]](<6 x s32>) ; CHECK: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF2]](<6 x s32>)
; CHECK: [[INSERT:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[TRUNC2]], [[EXTRACT]](<5 x s16>), 0 ; CHECK: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[UV12]](s32)
; CHECK: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[UV13]](s32)
; CHECK: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[UV14]](s32)
; CHECK: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[UV15]](s32)
; CHECK: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[UV16]](s32)
; CHECK: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[UV17]](s32)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC12]](s16), [[TRUNC13]](s16), [[TRUNC14]](s16), [[TRUNC15]](s16), [[TRUNC16]](s16), [[TRUNC17]](s16)
; CHECK: [[INSERT:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[BUILD_VECTOR2]], [[EXTRACT]](<5 x s16>), 0
; CHECK: [[DEF3:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF3:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC3:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF3]](<6 x s32>) ; CHECK: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF3]](<6 x s32>)
; CHECK: [[INSERT1:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[TRUNC3]], [[EXTRACT1]](<5 x s16>), 0 ; CHECK: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[UV18]](s32)
; CHECK: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[INSERT]](<6 x s16>) ; CHECK: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[UV19]](s32)
; CHECK: [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<6 x s16>) ; CHECK: [[TRUNC20:%[0-9]+]]:_(s16) = G_TRUNC [[UV20]](s32)
; CHECK: [[TRUNC21:%[0-9]+]]:_(s16) = G_TRUNC [[UV21]](s32)
; CHECK: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[UV22]](s32)
; CHECK: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[UV23]](s32)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[TRUNC18]](s16), [[TRUNC19]](s16), [[TRUNC20]](s16), [[TRUNC21]](s16), [[TRUNC22]](s16), [[TRUNC23]](s16)
; CHECK: [[INSERT1:%[0-9]+]]:_(<6 x s16>) = G_INSERT [[BUILD_VECTOR3]], [[EXTRACT1]](<5 x s16>), 0
; CHECK: [[UV24:%[0-9]+]]:_(<3 x s16>), [[UV25:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[INSERT]](<6 x s16>)
; CHECK: [[UV26:%[0-9]+]]:_(<3 x s16>), [[UV27:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<6 x s16>)
; CHECK: [[DEF4:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF4:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF4]], [[UV]](<3 x s16>), 0 ; CHECK: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF4]], [[UV24]](<3 x s16>), 0
; CHECK: [[DEF5:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF5:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF5]], [[UV2]](<3 x s16>), 0 ; CHECK: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF5]], [[UV26]](<3 x s16>), 0
; CHECK: [[XOR:%[0-9]+]]:_(<4 x s16>) = G_XOR [[INSERT2]], [[INSERT3]] ; CHECK: [[XOR:%[0-9]+]]:_(<4 x s16>) = G_XOR [[INSERT2]], [[INSERT3]]
; CHECK: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[XOR]](<4 x s16>), 0 ; CHECK: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[XOR]](<4 x s16>), 0
; CHECK: [[DEF6:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF6:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT4:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF6]], [[UV1]](<3 x s16>), 0 ; CHECK: [[INSERT4:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF6]], [[UV25]](<3 x s16>), 0
; CHECK: [[DEF7:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF7:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT5:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF7]], [[UV3]](<3 x s16>), 0 ; CHECK: [[INSERT5:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF7]], [[UV27]](<3 x s16>), 0
; CHECK: [[XOR1:%[0-9]+]]:_(<4 x s16>) = G_XOR [[INSERT4]], [[INSERT5]] ; CHECK: [[XOR1:%[0-9]+]]:_(<4 x s16>) = G_XOR [[INSERT4]], [[INSERT5]]
; CHECK: [[EXTRACT3:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[XOR1]](<4 x s16>), 0 ; CHECK: [[EXTRACT3:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[XOR1]](<4 x s16>), 0
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT2]](<3 x s16>), [[EXTRACT3]](<3 x s16>) ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT2]](<3 x s16>), [[EXTRACT3]](<3 x s16>)
; CHECK: [[EXTRACT4:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0 ; CHECK: [[EXTRACT4:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
; CHECK: [[DEF8:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF8:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC4:%[0-9]+]]:_(<8 x s16>) = G_TRUNC [[DEF8]](<8 x s32>) ; CHECK: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF8]](<8 x s32>)
; CHECK: [[INSERT6:%[0-9]+]]:_(<8 x s16>) = G_INSERT [[TRUNC4]], [[EXTRACT4]](<5 x s16>), 0 ; CHECK: [[TRUNC24:%[0-9]+]]:_(s16) = G_TRUNC [[UV28]](s32)
; CHECK: [[TRUNC25:%[0-9]+]]:_(s16) = G_TRUNC [[UV29]](s32)
; CHECK: [[TRUNC26:%[0-9]+]]:_(s16) = G_TRUNC [[UV30]](s32)
; CHECK: [[TRUNC27:%[0-9]+]]:_(s16) = G_TRUNC [[UV31]](s32)
; CHECK: [[TRUNC28:%[0-9]+]]:_(s16) = G_TRUNC [[UV32]](s32)
; CHECK: [[TRUNC29:%[0-9]+]]:_(s16) = G_TRUNC [[UV33]](s32)
; CHECK: [[TRUNC30:%[0-9]+]]:_(s16) = G_TRUNC [[UV34]](s32)
; CHECK: [[TRUNC31:%[0-9]+]]:_(s16) = G_TRUNC [[UV35]](s32)
; CHECK: [[BUILD_VECTOR4:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[TRUNC24]](s16), [[TRUNC25]](s16), [[TRUNC26]](s16), [[TRUNC27]](s16), [[TRUNC28]](s16), [[TRUNC29]](s16), [[TRUNC30]](s16), [[TRUNC31]](s16)
; CHECK: [[INSERT6:%[0-9]+]]:_(<8 x s16>) = G_INSERT [[BUILD_VECTOR4]], [[EXTRACT4]](<5 x s16>), 0
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT6]](<8 x s16>) ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INSERT6]](<8 x s16>)
%0:_(<5 x s16>) = G_IMPLICIT_DEF %0:_(<5 x s16>) = G_IMPLICIT_DEF
%1:_(<5 x s16>) = G_IMPLICIT_DEF %1:_(<5 x s16>) = G_IMPLICIT_DEF
%2:_(<5 x s16>) = G_XOR %0, %1 %2:_(<5 x s16>) = G_XOR %0, %1
%4:_(<8 x s16>) = G_IMPLICIT_DEF %4:_(<8 x s16>) = G_IMPLICIT_DEF
%5:_(<8 x s16>) = G_INSERT %4, %2, 0 %5:_(<8 x s16>) = G_INSERT %4, %2, 0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5
... ...
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines