[ARM] Fix handling of zero offsets in LOB instructions.

[simon_tatham]

Summary

The BF and WLS/WLSTP instructions have various branch-offset fields
occupying different positions and lengths in the instruction encoding,
and all of them were decoded at disassembly time by the function
DecodeBFLabelOffset() which returned SoftFail if the offset was zero.

In fact, it's perfectly fine and not even a SoftFail for most of those
offset fields to be zero. The only one that can't be zero is the 4-bit
field labelled boff in the architecture spec, occupying bits {26-23}
of the BF instruction family. If that one is zero, the encoding
overlaps other instructions (WLS, DLS, LETP, VCTP), so it ought to be
a full Fail.

Fixed by adding an extra template parameter to DecodeBFLabelOffset
which controls whether a zero offset is accepted or rejected. Adjusted
existing tests (only in error messages for bad disassemblies); added
extra tests to demonstrate zero offsets being accepted in all the
right places, and a few demonstrating rejection of zero boff.

[DavidSpickett]

LGTM

llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

def addrmode_tbh : MemOperand {
   let PrintMethod = "printAddrModeTBH";
   let ParserMatchClass = addrmode_tbh_asmoperand;
   let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
 }
 
 // Define ARMv8.1-M specific addressing modes.
 
 // Label operands for BF/BFL/WLS/DLS/LE
-class BFLabelOp<string signed, string isNeg, string size, string fixup>
+class BFLabelOp<string signed, string isNeg, string zeroPermitted, string size,
+                string fixup>
   : Operand<OtherVT> {
   let EncoderMethod = !strconcat("getBFTargetOpValue<", isNeg, ", ",
                                  fixup, ">");
   let OperandType = "OPERAND_PCREL";
   let DecoderMethod = !strconcat("DecodeBFLabelOperand<", signed, ", ",
-                                 isNeg, ", ", size, ">");
+                                 isNeg, ", ", zeroPermitted, ", ", size, ">");
 }
-def bflabel_u4  : BFLabelOp<"false", "false", "4",  "ARM::fixup_bf_branch">;
-def bflabel_s12 : BFLabelOp<"true",  "false", "12", "ARM::fixup_bfc_target">;
-def bflabel_s16 : BFLabelOp<"true",  "false", "16", "ARM::fixup_bf_target">;
-def bflabel_s18 : BFLabelOp<"true",  "false", "18", "ARM::fixup_bfl_target">;
+def bflabel_u4  : BFLabelOp<"false", "false", "false", "4",  "ARM::fixup_bf_branch">;
+def bflabel_s12 : BFLabelOp<"true",  "false", "true",  "12", "ARM::fixup_bfc_target">;
+def bflabel_s16 : BFLabelOp<"true",  "false", "true",  "16", "ARM::fixup_bf_target">;
+def bflabel_s18 : BFLabelOp<"true",  "false", "true",  "18", "ARM::fixup_bfl_target">;
 
 def wlslabel_u11_asmoperand : AsmOperandClass {
   let Name = "WLSLabel";
   let RenderMethod = "addImmOperands";
   let PredicateMethod = "isUnsignedOffset<11, 1>";
   let DiagnosticString =
     "loop end is out of range or not a positive multiple of 2";
 }
-def wlslabel_u11 : BFLabelOp<"false", "false", "11", "ARM::fixup_wls"> {
+def wlslabel_u11 : BFLabelOp<"false", "false", "true",  "11", "ARM::fixup_wls"> {
   let ParserMatchClass = wlslabel_u11_asmoperand;
 }
 def lelabel_u11_asmoperand : AsmOperandClass {
   let Name = "LELabel";
   let RenderMethod = "addImmOperands";
   let PredicateMethod = "isLEOffset";
   let DiagnosticString =
     "loop start is out of range or not a negative multiple of 2";
 }
-def lelabel_u11 : BFLabelOp<"false", "true",  "11", "ARM::fixup_le"> {
+def lelabel_u11 : BFLabelOp<"false", "true",  "true",  "11", "ARM::fixup_le"> {
   let ParserMatchClass = lelabel_u11_asmoperand;
 }
 
 def bfafter_target : Operand<OtherVT> {
     let EncoderMethod = "getBFAfterTargetOpValue";
     let OperandType = "OPERAND_PCREL";
     let DecoderMethod = "DecodeBFAfterTargetOperand";
 }

llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

 
 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
                                             uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
                                          uint64_t Address, const void *Decoder);
 
-template <bool isSigned, bool isNeg, int size>
+template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
                                          uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
                                                uint64_t Address,
                                                const void *Decoder);
 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
                                           uint64_t Address,
                                           const void *Decoder);
if (featureBits[ARM::ModeThumb]) {
     unsigned pred = fieldFromInstruction(Val, 28, 4);
     if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
       return MCDisassembler::Fail;
   }
 
   return S;
 }
 
-template <bool isSigned, bool isNeg, int size>
+template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
                                          uint64_t Address,
                                          const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
-  if (Val == 0)
-    S = MCDisassembler::SoftFail;
+  if (Val == 0 && !zeroPermitted)
+    S = MCDisassembler::Fail;
 
   uint64_t DecVal;
   if (isSigned)
     DecVal = SignExtend32<size + 1>(Val << 1);
   else
     DecVal = (Val << 1);
 
   if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst,
unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
                  fieldFromInstruction(Insn, 1, 10) << 1;
   switch (Inst.getOpcode()) {
   case ARM::t2LEUpdate:
   case ARM::MVE_LETP:
     Inst.addOperand(MCOperand::createReg(ARM::LR));
     Inst.addOperand(MCOperand::createReg(ARM::LR));
     LLVM_FALLTHROUGH;
   case ARM::t2LE:
-    if (!Check(S, DecodeBFLabelOperand<false, true, 11>(Inst, Imm, Address,
-                                                        Decoder)))
+    if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>(
+                   Inst, Imm, Address, Decoder)))
       return MCDisassembler::Fail;
     break;
   case ARM::t2WLS:
   case ARM::MVE_WLSTP_8:
   case ARM::MVE_WLSTP_16:
   case ARM::MVE_WLSTP_32:
   case ARM::MVE_WLSTP_64:
     Inst.addOperand(MCOperand::createReg(ARM::LR));
     if (!Check(S,
                DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),
                                        Address, Decoder)) ||
-        !Check(S, DecodeBFLabelOperand<false, false, 11>(Inst, Imm, Address,
-                                                         Decoder)))
+        !Check(S, DecodeBFLabelOperand<false, false, true, 11>(
+                   Inst, Imm, Address, Decoder)))
       return MCDisassembler::Fail;
     break;
   case ARM::t2DLS:
   case ARM::MVE_DLSTP_8:
   case ARM::MVE_DLSTP_16:
   case ARM::MVE_DLSTP_32:
   case ARM::MVE_DLSTP_64:
     unsigned Rn = fieldFromInstruction(Insn, 16, 4);

llvm/trunk/test/MC/ARM/mve-misc.s

 # CHECK: wlstp.32     lr, r3, .Lendloop  @ encoding: [0x23'A',0xf0'A',0x01'A',0xc0'A']
 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 wlstp.32     lr, r3, .Lendloop
 
 # CHECK: wlstp.64     lr, r5, .Lendloop  @ encoding: [0x35'A',0xf0'A',0x01'A',0xc0'A']
 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 wlstp.64     lr, r5, .Lendloop
 
+# CHECK: wlstp.64     lr, r5, #0  @ encoding: [0x35,0xf0,0x01,0xc0]
+# ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
+wlstp.64     lr, r5, #0
+
 # CHECK: dlstp.8     lr, r5  @ encoding: [0x05,0xf0,0x01,0xe0]
 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 dlstp.8     lr, r5
 
 # CHECK: dlstp.16     lr, r5  @ encoding: [0x15,0xf0,0x01,0xe0]
 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 dlstp.16     lr, r5
 

llvm/trunk/test/MC/ARM/thumbv8.1m.s

 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
 bf #4, #65536
 
 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
 bf #4, #-65538
 
+// CHECK: bf #4, #0
+// CHECK-FP: bf #4, #0
+// ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
+bf #4, #0
+
 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
 bfl #4, #262144
 
 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch target out of range or not a multiple of 2
 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
 bfl #4, #-262146
 
+// CHECK: bfl #4, #0
+// CHECK-FP: bfl #4, #0
+// ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
+bfl #4, #0
+
 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
 bfcsel #-2, #10, #2, eq
 
 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: branch location out of range or not a multiple of 2
 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:

 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
 bfcsel #4, #-65538, #8, eq
 
 // ERROR: :[[@LINE+3]]:{{[0-9]+}}: error: else branch target must be 2 or 4 greater than the branch location
 // ERROR-FP: :[[@LINE+2]]:{{[0-9]+}}: error: else branch target must be 2 or 4 greater than the branch location
 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
 bfcsel #4, #65534, #10, eq
 
+// CHECK: bfcsel #4, #0, #8, eq
+// CHECK-FP: bfcsel #4, #0, #8, eq
+// ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:
+bfcsel #4, #0, #8, eq
+
 // CHECK: bf  .Lbranch, .Ltarget      @ encoding: [0x40'B',0xf0'B',0x01'B',0xe0'B']
 // CHECK-FP: bf  .Lbranch, .Ltarget      @ encoding: [0x40'B',0xf0'B',0x01'B',0xe0'B']
 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
 bf  .Lbranch, .Ltarget
 
 // CHECK: bfcsel  .Lbranch, .Lthen, .Lelse, ne @ encoding: [0x04'C',0xf0'C',0x01'C',0xe0'C']
 // CHECK-FP: bfcsel  .Lbranch, .Lthen, .Lelse, ne @ encoding: [0x04'C',0xf0'C',0x01'C',0xe0'C']
 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error:

 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
 bflx .Lbranch, r7
 
 // CHECK: wls lr, r2, .Lend           @ encoding: [0x42'A',0xf0'A',0x01'A',0xc0'A']
 // CHECK-FP: wls lr, r2, .Lend           @ encoding: [0x42'A',0xf0'A',0x01'A',0xc0'A']
 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
 wls lr, r2, .Lend
 
+// CHECK: wls lr, r2, #0
+// CHECK-FP: wls lr, r2, #0
+// ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
+wls lr, r2, #0
+
 // CHECK: dls lr, r2                  @ encoding: [0x42,0xf0,0x01,0xe0]
 // CHECK-FP: dls lr, r2                  @ encoding: [0x42,0xf0,0x01,0xe0]
 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob
 dls lr, r2
 
 // CHECK: le lr, .Lstart              @ encoding: [0x0f'A',0xf0'A',0x01'A',0xc0'A']
 // CHECK-FP: le lr, .Lstart              @ encoding: [0x0f'A',0xf0'A',0x01'A',0xc0'A']
 // ERROR-NOLOB: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires: lob

llvm/trunk/test/MC/Disassembler/ARM/mve-misc.txt

 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2> %t | FileCheck %s
 # RUN: FileCheck --check-prefix=ERROR < %t %s
 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
 # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
 
 # CHECK: vpsel   q0, q5, q2  @ encoding: [0x3b,0xfe,0x05,0x0f]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x3b,0xfe,0x05,0x0f]
 
 # CHECK: vpnot  @ encoding: [0x31,0xfe,0x4d,0x0f]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x31,0xfe,0x4d,0x0f]
 
 # CHECK: wlstp.8     lr, r0, #1668  @ encoding: [0x00,0xf0,0x43,0xc3]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x00,0xf0,0x43,0xc3]
 
 # CHECK: wlstp.16     lr, r0, #1668  @ encoding: [0x10,0xf0,0x43,0xc3]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x10,0xf0,0x43,0xc3]
 
 # CHECK: wlstp.32     lr, r4, #2706  @ encoding: [0x24,0xf0,0x49,0xcd]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x24,0xf0,0x49,0xcd]
 
 # CHECK: wlstp.64     lr, lr, #3026  @ encoding: [0x3e,0xf0,0xe9,0xcd]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x3e,0xf0,0xe9,0xcd]
 
 # CHECK: wlstp.8     lr, r5, #3436  @ encoding: [0x05,0xf0,0xb7,0xc6]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x05,0xf0,0xb7,0xc6]
 
 # CHECK: wlstp.16     lr, r1, #1060  @ encoding: [0x11,0xf0,0x13,0xc2]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x11,0xf0,0x13,0xc2]
 
 # CHECK: wlstp.32     lr, r7, #4036  @ encoding: [0x27,0xf0,0xe3,0xc7]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x27,0xf0,0xe3,0xc7]
 
 # CHECK: wlstp.8     lr, r1, #538  @ encoding: [0x01,0xf0,0x0d,0xc9]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x01,0xf0,0x0d,0xc9]
 
 # CHECK: wlstp.8     lr, r10, #1404  @ encoding: [0x0a,0xf0,0xbf,0xc2]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x0a,0xf0,0xbf,0xc2]
 
 # CHECK: wlstp.8     lr, r10, #1408  @ encoding: [0x0a,0xf0,0xc1,0xc2]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x0a,0xf0,0xc1,0xc2]
 
 # CHECK: wlstp.8     lr, r10, #2358  @ encoding: [0x0a,0xf0,0x9b,0xcc]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x0a,0xf0,0x9b,0xcc]
 
 # CHECK: wlstp.8     lr, r10, #4086  @ encoding: [0x0a,0xf0,0xfb,0xcf]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x0a,0xf0,0xfb,0xcf]
 
 # CHECK: wlstp.8     lr, r11, #1442  @ encoding: [0x0b,0xf0,0xd1,0xca]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x0b,0xf0,0xd1,0xca]
 
+# CHECK: wlstp.64    lr, r5, #0      @ encoding: [0x35,0xf0,0x01,0xc0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xf0,0x01,0xc0]
+
 # CHECK: dlstp.8     lr, r5  @ encoding: [0x05,0xf0,0x01,0xe0]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x05,0xf0,0x01,0xe0]
 
 # CHECK: dlstp.16     lr, r5  @ encoding: [0x15,0xf0,0x01,0xe0]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x15,0xf0,0x01,0xe0]
 
 # CHECK: dlstp.32     lr, r7  @ encoding: [0x27,0xf0,0x01,0xe0]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x27,0xf0,0x01,0xe0]
 
 # CHECK: dlstp.64     lr, r2  @ encoding: [0x32,0xf0,0x01,0xe0]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x32,0xf0,0x01,0xe0]
 
 # CHECK: letp lr, #-2 @ encoding: [0x1f,0xf0,0x01,0xc8]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x1f,0xf0,0x01,0xc8]
 
 # CHECK: letp lr, #-8 @ encoding: [0x1f,0xf0,0x05,0xc0]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x1f,0xf0,0x05,0xc0]
 
 # CHECK: letp lr, #-4094 @ encoding: [0x1f,0xf0,0xff,0xcf]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x1f,0xf0,0xff,0xcf]
 
 # CHECK: lctp @ encoding: [0x0f,0xf0,0x01,0xe0]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x0f,0xf0,0x01,0xe0]
 
 # ERROR: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
 [0x1f,0xf0,0x01,0xe0]
 
 # ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x4f,0xf0,0x01,0xe0]
 
 # The following tests have to go last because of the NOMVE-NOT checks.
 
 # CHECK: it eq @ encoding: [0x08,0xbf]
 # CHECK-NOMVE: it eq @ encoding: [0x08,0xbf]
 [0x08,0xbf]
 # CHECK: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
 # CHECK-NOMVE-NOT: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
 [0x0f,0xf0,0x01,0xe0]

llvm/trunk/test/MC/Disassembler/ARM/mve-qdest-rsrc.txt

 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x1b,0xee,0xee,0x1f]
 
 # CHECK: vddup.u32 q2, r0, #8  @ encoding: [0x21,0xee,0xef,0x5f]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x21,0xee,0xef,0x5f]
 
 # CHECK: vctp.8 lr  @ encoding: [0x0e,0xf0,0x01,0xe8]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x0e,0xf0,0x01,0xe8]
 
 # CHECK: vctp.16 r0  @ encoding: [0x10,0xf0,0x01,0xe8]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x10,0xf0,0x01,0xe8]
 
 # CHECK: vctp.32 r10  @ encoding: [0x2a,0xf0,0x01,0xe8]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x2a,0xf0,0x01,0xe8]
 
 # CHECK: vctp.64 r1  @ encoding: [0x31,0xf0,0x01,0xe8]
-# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x31,0xf0,0x01,0xe8]

llvm/trunk/test/MC/Disassembler/ARM/thumb2-v8.1m.txt

 # CHECK: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
 [0x50,0xea,0x01,0x80]
 
 # ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x50,0xea,0xe0,0x80]
 
 # ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x50,0xea,0xf0,0x80]
+
+# CHECK: bf #4, #0 @ encoding: [0x40,0xf1,0x01,0xe0]
+[0x40,0xf1,0x01,0xe0]
+
+# CHECK: bfl #4, #0 @ encoding: [0x00,0xf1,0x01,0xc0]
+[0x00,0xf1,0x01,0xc0]
+
+# CHECK: bfcsel #4, #0, #8, eq @ encoding: [0x02,0xf1,0x01,0xe0]
+[0x02,0xf1,0x01,0xe0]
+
+# CHECK: wls lr, r2, #0 @ encoding: [0x42,0xf0,0x01,0xc0]
+[0x42,0xf0,0x01,0xc0]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x60,0xf0,0x01,0xe0]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x70,0xf0,0x01,0xe0]