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[ARM] Tighten restrictions on use of SP in v8.1-M CSEL.
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Authored by simon_tatham on Jun 27 2019, 2:49 AM.

Details

Summary

In the CSEL Rd,Rm,Rn instruction family (also including CSINC, CSINV
and CSNEG), the architecture lists it as CONSTRAINED UNPREDICTABLE
(i.e. SoftFail) to use SP in the Rd or Rm slot, but outright illegal
to use it in the Rn slot, not least because some encodings of that
form are used by MVE instructions such as UQRSHLL.

MC was treating all three slots the same, as SoftFail. So the only
reason UQRSHLL was disassembled correctly at all was because the MVE
decode table is separate from the Thumb2 one and takes priority; if
you turned off MVE, then encodings such as [0x5f,0xea,0x0d,0x83]
would disassemble as spurious CSELs.

Fixed by inventing another version of the GPRwithZR register class,
which disallows SP completely instead of just SoftFailing it.

Diff Detail

Repository
rL LLVM

Event Timeline

simon_tatham created this revision.Jun 27 2019, 2:49 AM
DavidSpickett added inline comments.Jun 27 2019, 3:42 AM
llvm/test/MC/Disassembler/ARM/thumbv8.1m.s
1 ↗(On Diff #206804)

How did this work to begin with?

simon_tatham marked an inline comment as done.Jun 27 2019, 4:58 AM
simon_tatham added inline comments.
llvm/test/MC/Disassembler/ARM/thumbv8.1m.s
1 ↗(On Diff #206804)

No test in this file previously generated the message "warning: invalid instruction encoding". Two of the new ones do.

Apparently that message, representing MCDisassembler::Fail as opposed to SoftFail, causes the exit status of llvm-mc to become failure, in spite of the word "warning" on the front!

DavidSpickett accepted this revision.Jun 27 2019, 5:12 AM
This revision is now accepted and ready to land.Jun 27 2019, 5:12 AM
This revision was automatically updated to reflect the committed changes.