[PowerPC] Sign extend the select instr operands if it is any_extend

[steven.zhang]

Summary

Though we have the patch https://reviews.llvm.org/D63318 to fold the aext + select in DAGCombine, PowerPC still have own combine rule to do this. However, it didn't handle the any extend well. For now, we will do the zero extend if the select operands are constant and it is fed by any_extend.

    t1: i8 = select t0, Constant:i8<-1>, Constant:i8<0>
    t2: i64 = any_extend t1
-->
    t3: i64 = select t0, Constant:i64<255>, Constant:i64<0>

The zero extend break the special pattern of "-1" and it might hurt some performance opportunity if they are caring about the sign bit.

This is what we want to do:

    t1: i8 = select t0, Constant:i8<-1>, Constant:i8<0>
    t2: i64 = any_extend t1
-->
    t3: i64 = select t0, Constant:i64<-1>, Constant:i64<0>
-->
    t4: i64 = sign_extend_inreg t3

[steven.zhang]

Hi, @hfinkel
As this was added by you in https://reviews.llvm.org/rL202451, would you please help me review this patch ? And I also commit another patch(https://reviews.llvm.org/D63318) to fold this pattern in DAGCombine. Would you please take a look together ? Thank you!

[hfinkel]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

12325

This seems like we're working around a problem elsewhere. Why does forcing any_extend to become a sign_extend produce better code than just producing an any_extend?

llvm/test/CodeGen/PowerPC/bool-math.ll

9

Is this a regression - it looks like we're going from two instructions to three?

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

12325

For any_extend, it is handled as zero extend if it is constant. For example,

t1: i8 = select t0, Constant:i8<-1>, Constant:i8<0>
t2: i64 = any_extend t1

It will be combined as follows, for now:

t3: i64 = select t0, Constant:i64<255>, Constant:i64<0>

And the literal "255" is just a normal constant, therefore, the combine to inreg rule won't apply. This is what we expected:

t3: i64 = select t0, Constant:i64<-1>, Constant:i64<0>

So that, the combine to inreg rule would apply and it is combined as:
t4: i64 = sign_extend_inreg t3

Doing zero extend will hurt some opportunities, while sign extend indeed helps. And we haven't seen the downside yet.

llvm/test/CodeGen/PowerPC/bool-math.ll

9

No, both are three instructions.

[hfinkel]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

12325

Doing zero extend will hurt some opportunities, while sign extend indeed helps. And we haven't seen the downside yet.

What happens if we always prefer to lower any_extend to sign_extend instead of just doing it in this special case? Given that, on PPC, immediates are generally sign extended, etc., maybe that should be the default?

llvm/test/CodeGen/PowerPC/bool-math.ll

9

Ah, indeed. Thanks.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

12325

Yes, I tried. For powerpc, I didn't see any problems by doing this, but also no benefit from the sanity test and benchmark 2017, but for X86, I indeed see many bad changes. I guess they have some assumption on this. So, I decide to just do it for aext + select.

[hfinkel]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

12325

Is this the code that's going it:

case ISD::ANY_EXTEND:
case ISD::ZERO_EXTEND:
  return getConstant(Val.zextOrTrunc(VT.getSizeInBits()), DL, VT,
                     C->isTargetOpcode(), C->isOpaque());

(in SelectionDAG::getNode)?

Also, maybe we should override TLI.isSExtCheaperThanZExt and propose tying this behavior to the result of that callback? It seems like we should be able to change this on PPC without affecting x86.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

12325

Sounds work. However, I still have some concern that, sext really is cheaper than zext in PowerPC ? The reason why we want to do signed extend is that, if will break some pattern for select combine rule, not because of it is cheaper...

Anyway, I will try it first.
Inside SelectionDAG::getNode, call hook TLI.isSExtCheaperThanZExt to decide how to promote the any extend constant.

[hfinkel]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

12325

Sounds work. However, I still have some concern that, sext really is cheaper than zext in PowerPC ?

I think that it depends on the context; but any_extend is supposed to allow us to do something smart (and target influenced), and so let's see if we can make it a little smarter and get a broader benefit.

[steven.zhang]

Abandon this revision, as most opportunity has been fixed by https://reviews.llvm.org/rL202451.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

while (!PromOpHandles.empty()) {
 
     // If this node has constant inputs, then they'll need to be promoted here.
     for (unsigned i = 0; i < 2; ++i) {
       if (!isa<ConstantSDNode>(Ops[C+i]))
         continue;
       if (Ops[C+i].getValueType() == N->getValueType(0))
         continue;
 
-      if (N->getOpcode() == ISD::SIGN_EXTEND)
+      if (N->getOpcode() == ISD::SIGN_EXTEND ||
+          // Sign extend the operands if it is any_extend, to keep the signess
+          // of the operands that, the other combine rule would apply. i.e.
+          //
+          // t1: i8 = select t0, Constant:i8<-1>, Constant:i8<0>
+          // t2: i64 = any_extend t1
+          // -->
+          // t3: i64 = select t0, Constant:i64<-1>, Constant:i64<0>
+          // -->
+          // t4: i64 = sign_extend_inreg t3
+          N->getOpcode() == ISD::ANY_EXTEND)
         Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
       else if (N->getOpcode() == ISD::ZERO_EXTEND)
         Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
       else
-        Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
+        llvm_unreachable("Unexpected opcode!");
     }
 
     // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
     // truncate them again to the original value type.
     if (PromOp.getOpcode() == ISD::SELECT ||
         PromOp.getOpcode() == ISD::SELECT_CC) {
       auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
       if (SI0 != SelectTruncOp[0].end())

llvm/test/CodeGen/PowerPC/bool-math.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64le-- -verify-machineinstrs | FileCheck %s
 
 define i32 @sub_zext_cmp_mask_same_size_result(i32 %x) {
 ; CHECK-LABEL: sub_zext_cmp_mask_same_size_result:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, -28
 ; CHECK-NEXT:    clrldi 3, 3, 63
-; CHECK-NEXT:    ori 3, 3, 65508
-; CHECK-NEXT:    oris 3, 3, 65535
+; CHECK-NEXT:    or 3, 3, 4
 ; CHECK-NEXT:    blr
   %a = and i32 %x, 1
   %c = icmp eq i32 %a, 0
   %z = zext i1 %c to i32
   %r = sub i32 -27, %z
   ret i32 %r
 }
 

llvm/test/CodeGen/PowerPC/select_const.ll

 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 1, i32 0
   ret i32 %sel
 }
 
 ; select Cond, 0, -1 --> sext (!Cond)
 
 define i32 @select_0_or_neg1(i1 %cond) {
-; ISEL-LABEL: select_0_or_neg1:
-; ISEL:       # %bb.0:
-; ISEL-NEXT:    li 4, 0
-; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    oris 3, 4, 65535
-; ISEL-NEXT:    ori 3, 3, 65535
-; ISEL-NEXT:    isel 3, 0, 3, 1
-; ISEL-NEXT:    blr
-;
-; NO_ISEL-LABEL: select_0_or_neg1:
-; NO_ISEL:       # %bb.0:
-; NO_ISEL-NEXT:    li 4, 0
-; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    oris 3, 4, 65535
-; NO_ISEL-NEXT:    ori 3, 3, 65535
-; NO_ISEL-NEXT:    bc 12, 1, .LBB6_1
-; NO_ISEL-NEXT:    blr
-; NO_ISEL-NEXT:  .LBB6_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
-; NO_ISEL-NEXT:    blr
+; ALL-LABEL: select_0_or_neg1:
+; ALL:       # %bb.0:
+; ALL-NEXT:    not 3, 3
+; ALL-NEXT:    clrldi 3, 3, 63
+; ALL-NEXT:    neg 3, 3
+; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 0, i32 -1
   ret i32 %sel
 }
 
 define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {
-; ISEL-LABEL: select_0_or_neg1_zeroext:
-; ISEL:       # %bb.0:
-; ISEL-NEXT:    li 4, 0
-; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    oris 3, 4, 65535
-; ISEL-NEXT:    ori 3, 3, 65535
-; ISEL-NEXT:    isel 3, 0, 3, 1
-; ISEL-NEXT:    blr
-;
-; NO_ISEL-LABEL: select_0_or_neg1_zeroext:
-; NO_ISEL:       # %bb.0:
-; NO_ISEL-NEXT:    li 4, 0
-; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    oris 3, 4, 65535
-; NO_ISEL-NEXT:    ori 3, 3, 65535
-; NO_ISEL-NEXT:    bc 12, 1, .LBB7_1
-; NO_ISEL-NEXT:    blr
-; NO_ISEL-NEXT:  .LBB7_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
-; NO_ISEL-NEXT:    blr
+; ALL-LABEL: select_0_or_neg1_zeroext:
+; ALL:       # %bb.0:
+; ALL-NEXT:    xori 3, 3, 1
+; ALL-NEXT:    neg 3, 3
+; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 0, i32 -1
   ret i32 %sel
 }
 
 define i32 @select_0_or_neg1_signext(i1 signext %cond) {
-; ISEL-LABEL: select_0_or_neg1_signext:
-; ISEL:       # %bb.0:
-; ISEL-NEXT:    li 4, 0
-; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    oris 3, 4, 65535
-; ISEL-NEXT:    ori 3, 3, 65535
-; ISEL-NEXT:    isel 3, 0, 3, 1
-; ISEL-NEXT:    blr
-;
-; NO_ISEL-LABEL: select_0_or_neg1_signext:
-; NO_ISEL:       # %bb.0:
-; NO_ISEL-NEXT:    li 4, 0
-; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    oris 3, 4, 65535
-; NO_ISEL-NEXT:    ori 3, 3, 65535
-; NO_ISEL-NEXT:    bc 12, 1, .LBB8_1
-; NO_ISEL-NEXT:    blr
-; NO_ISEL-NEXT:  .LBB8_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
-; NO_ISEL-NEXT:    blr
+; ALL-LABEL: select_0_or_neg1_signext:
+; ALL:       # %bb.0:
+; ALL-NEXT:    not 3, 3
+; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 0, i32 -1
   ret i32 %sel
 }
 
 ; select Cond, -1, 0 --> sext (Cond)
 
 define i32 @select_neg1_or_0(i1 %cond) {
-; ISEL-LABEL: select_neg1_or_0:
-; ISEL:       # %bb.0:
-; ISEL-NEXT:    li 4, 0
-; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    oris 3, 4, 65535
-; ISEL-NEXT:    ori 3, 3, 65535
-; ISEL-NEXT:    isel 3, 3, 4, 1
-; ISEL-NEXT:    blr
-;
-; NO_ISEL-LABEL: select_neg1_or_0:
-; NO_ISEL:       # %bb.0:
-; NO_ISEL-NEXT:    li 4, 0
-; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    oris 3, 4, 65535
-; NO_ISEL-NEXT:    ori 3, 3, 65535
-; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # %bb.1:
-; NO_ISEL-NEXT:    ori 3, 4, 0
-; NO_ISEL-NEXT:    blr
+; ALL-LABEL: select_neg1_or_0:
+; ALL:       # %bb.0:
+; ALL-NEXT:    clrldi 3, 3, 63
+; ALL-NEXT:    neg 3, 3
+; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 -1, i32 0
   ret i32 %sel
 }
 
 define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {
-; ISEL-LABEL: select_neg1_or_0_zeroext:
-; ISEL:       # %bb.0:
-; ISEL-NEXT:    li 4, 0
-; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    oris 3, 4, 65535
-; ISEL-NEXT:    ori 3, 3, 65535
-; ISEL-NEXT:    isel 3, 3, 4, 1
-; ISEL-NEXT:    blr
-;
-; NO_ISEL-LABEL: select_neg1_or_0_zeroext:
-; NO_ISEL:       # %bb.0:
-; NO_ISEL-NEXT:    li 4, 0
-; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    oris 3, 4, 65535
-; NO_ISEL-NEXT:    ori 3, 3, 65535
-; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # %bb.1:
-; NO_ISEL-NEXT:    ori 3, 4, 0
-; NO_ISEL-NEXT:    blr
+; ALL-LABEL: select_neg1_or_0_zeroext:
+; ALL:       # %bb.0:
+; ALL-NEXT:    neg 3, 3
+; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 -1, i32 0
   ret i32 %sel
 }
 
 define i32 @select_neg1_or_0_signext(i1 signext %cond) {
-; ISEL-LABEL: select_neg1_or_0_signext:
-; ISEL:       # %bb.0:
-; ISEL-NEXT:    li 4, 0
-; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    oris 3, 4, 65535
-; ISEL-NEXT:    ori 3, 3, 65535
-; ISEL-NEXT:    isel 3, 3, 4, 1
-; ISEL-NEXT:    blr
-;
-; NO_ISEL-LABEL: select_neg1_or_0_signext:
-; NO_ISEL:       # %bb.0:
-; NO_ISEL-NEXT:    li 4, 0
-; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    oris 3, 4, 65535
-; NO_ISEL-NEXT:    ori 3, 3, 65535
-; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # %bb.1:
-; NO_ISEL-NEXT:    ori 3, 4, 0
-; NO_ISEL-NEXT:    blr
+; ALL-LABEL: select_neg1_or_0_signext:
+; ALL:       # %bb.0:
+; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 -1, i32 0
   ret i32 %sel
 }
 
 ; select Cond, C+1, C --> add (zext Cond), C
 
 define i32 @select_Cplus1_C(i1 %cond) {
 ; ALL-LABEL: select_Cplus1_C:
; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = add i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_sub_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_sub_constant:
 ; ISEL:       # %bb.0:
-; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    oris 3, 4, 65535
-; ISEL-NEXT:    li 4, 18
-; ISEL-NEXT:    ori 3, 3, 65527
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    li 4, -9
+; ISEL-NEXT:    li 3, 18
+; ISEL-NEXT:    isel 3, 4, 3, 1
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sub_constant:
 ; NO_ISEL:       # %bb.0:
-; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    oris 3, 4, 65535
-; NO_ISEL-NEXT:    li 4, 18
-; NO_ISEL-NEXT:    ori 3, 3, 65527
-; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # %bb.1:
-; NO_ISEL-NEXT:    ori 3, 4, 0
+; NO_ISEL-NEXT:    li 4, -9
+; NO_ISEL-NEXT:    li 3, 18
+; NO_ISEL-NEXT:    bc 12, 1, .LBB22_1
+; NO_ISEL-NEXT:    blr
+; NO_ISEL-NEXT:  .LBB22_1:
+; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = sub i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_sub_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: sel_constants_sub_constant_sel_constants:
; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 3
   %bo = sub i8 5, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_mul_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_mul_constant:
 ; ISEL:       # %bb.0:
-; ISEL-NEXT:    lis 4, 16383
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    ori 3, 4, 65531
-; ISEL-NEXT:    li 4, 115
-; ISEL-NEXT:    sldi 3, 3, 2
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    li 4, -20
+; ISEL-NEXT:    li 3, 115
+; ISEL-NEXT:    isel 3, 4, 3, 1
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_mul_constant:
 ; NO_ISEL:       # %bb.0:
-; NO_ISEL-NEXT:    lis 4, 16383
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    ori 3, 4, 65531
-; NO_ISEL-NEXT:    li 4, 115
-; NO_ISEL-NEXT:    sldi 3, 3, 2
-; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # %bb.1:
-; NO_ISEL-NEXT:    ori 3, 4, 0
+; NO_ISEL-NEXT:    li 4, -20
+; NO_ISEL-NEXT:    li 3, 115
+; NO_ISEL-NEXT:    bc 12, 1, .LBB24_1
+; NO_ISEL-NEXT:    blr
+; NO_ISEL-NEXT:  .LBB24_1:
+; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = mul i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_sdiv_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_sdiv_constant:
; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = udiv i8 120, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_srem_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_srem_constant:
 ; ISEL:       # %bb.0:
-; ISEL-NEXT:    lis 4, 16383
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    ori 3, 4, 65535
-; ISEL-NEXT:    li 4, 3
-; ISEL-NEXT:    sldi 3, 3, 2
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    li 4, -4
+; ISEL-NEXT:    li 3, 3
+; ISEL-NEXT:    isel 3, 4, 3, 1
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_srem_constant:
 ; NO_ISEL:       # %bb.0:
-; NO_ISEL-NEXT:    lis 4, 16383
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    ori 3, 4, 65535
-; NO_ISEL-NEXT:    li 4, 3
-; NO_ISEL-NEXT:    sldi 3, 3, 2
-; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # %bb.1:
-; NO_ISEL-NEXT:    ori 3, 4, 0
+; NO_ISEL-NEXT:    li 4, -4
+; NO_ISEL-NEXT:    li 3, 3
+; NO_ISEL-NEXT:    bc 12, 1, .LBB29_1
+; NO_ISEL-NEXT:    blr
+; NO_ISEL-NEXT:  .LBB29_1:
+; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = srem i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @srem_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: srem_constant_sel_constants:
; ALL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = and i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_or_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_or_constant:
 ; ISEL:       # %bb.0:
-; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    oris 3, 4, 65535
-; ISEL-NEXT:    li 4, 23
-; ISEL-NEXT:    ori 3, 3, 65533
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    li 4, -3
+; ISEL-NEXT:    li 3, 23
+; ISEL-NEXT:    isel 3, 4, 3, 1
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_or_constant:
 ; NO_ISEL:       # %bb.0:
-; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    oris 3, 4, 65535
-; NO_ISEL-NEXT:    li 4, 23
-; NO_ISEL-NEXT:    ori 3, 3, 65533
-; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # %bb.1:
-; NO_ISEL-NEXT:    ori 3, 4, 0
+; NO_ISEL-NEXT:    li 4, -3
+; NO_ISEL-NEXT:    li 3, 23
+; NO_ISEL-NEXT:    bc 12, 1, .LBB34_1
+; NO_ISEL-NEXT:    blr
+; NO_ISEL-NEXT:  .LBB34_1:
+; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = or i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_xor_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_xor_constant:
 ; ISEL:       # %bb.0:
-; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    oris 3, 4, 65535
-; ISEL-NEXT:    li 4, 18
-; ISEL-NEXT:    ori 3, 3, 65529
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    li 4, -7
+; ISEL-NEXT:    li 3, 18
+; ISEL-NEXT:    isel 3, 4, 3, 1
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_xor_constant:
 ; NO_ISEL:       # %bb.0:
-; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    oris 3, 4, 65535
-; NO_ISEL-NEXT:    li 4, 18
-; NO_ISEL-NEXT:    ori 3, 3, 65529
-; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # %bb.1:
-; NO_ISEL-NEXT:    ori 3, 4, 0
+; NO_ISEL-NEXT:    li 4, -7
+; NO_ISEL-NEXT:    li 3, 18
+; NO_ISEL-NEXT:    bc 12, 1, .LBB35_1
+; NO_ISEL-NEXT:    blr
+; NO_ISEL-NEXT:  .LBB35_1:
+; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = xor i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_shl_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_shl_constant:
 ; ISEL:       # %bb.0:
-; ISEL-NEXT:    lis 4, 2047
-; ISEL-NEXT:    lis 5, 511
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    ori 3, 4, 65535
-; ISEL-NEXT:    ori 4, 5, 65535
-; ISEL-NEXT:    sldi 3, 3, 5
-; ISEL-NEXT:    sldi 4, 4, 7
+; ISEL-NEXT:    li 4, -128
+; ISEL-NEXT:    li 3, -32
 ; ISEL-NEXT:    isel 3, 4, 3, 1
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_shl_constant:
 ; NO_ISEL:       # %bb.0:
-; NO_ISEL-NEXT:    lis 4, 2047
-; NO_ISEL-NEXT:    lis 5, 511
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    ori 3, 4, 65535
-; NO_ISEL-NEXT:    ori 4, 5, 65535
-; NO_ISEL-NEXT:    sldi 3, 3, 5
-; NO_ISEL-NEXT:    sldi 4, 4, 7
+; NO_ISEL-NEXT:    li 4, -128
+; NO_ISEL-NEXT:    li 3, -32
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB36_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB36_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = shl i8 %sel, 5
   ret i8 %bo