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Differential D63541

[MIPS GlobalISel] Select floating point to integer conversions
ClosedPublic

Authored by Petar.Avramovic on Jun 19 2019, 4:42 AM.

Details

Reviewers
atanasyan
petarj
Commits
rG4b4dae1c768d: [MIPS GlobalISel] Select floating point to integer conversions
rL363911: [MIPS GlobalISel] Select floating point to integer conversions
Summary

Select G_FPTOSI and G_FPTOUI for MIPS32.

Diff Detail

Event Timeline

Petar.Avramovic created this revision.Jun 19 2019, 4:42 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 19 2019, 4:42 AM
Herald added subscribers: llvm-commits, volkan, jrtc27 and 4 others. · View Herald Transcript
atanasyan accepted this revision.Jun 19 2019, 7:50 AM

LGTM with a couple nits.

lib/Target/Mips/MipsInstructionSelector.cpp
371

Maybe use the same terms as in the LegalizerHelper: FromSize and ToSize? Just for uniformity.

373

In the MipsRegisterBankInfo::getInstrMapping the same checking made by a couple of assert. Let's either split this check or merge the check in the MipsRegisterBankInfo::getInstrMapping. As well for uniformity

This revision is now accepted and ready to land.Jun 19 2019, 7:50 AM
Petar.Avramovic updated this revision to Diff 205748.Jun 20 2019, 1:39 AM

Addressed review comments.

Petar.Avramovic marked 2 inline comments as done.Jun 20 2019, 1:40 AM
Closed by commit rL363911: [MIPS GlobalISel] Select floating point to integer conversions (authored by Petar.Avramovic). · Explain WhyJun 20 2019, 1:51 AM
This revision was automatically updated to reflect the committed changes.
MaskRay mentioned this in rL364003: [MIPS GlobalISel] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds….Jun 20 2019, 6:50 PM
MaskRay mentioned this in rGddd056c98477: [MIPS GlobalISel] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds….

Revision Contents

PathSize
lib/
CodeGen/
GlobalISel/
5 lines
Target/
Mips/
27 lines
10 lines
12 lines
test/
CodeGen/
Mips/
GlobalISel/
instruction-select/
69 lines
legalizer/
369 lines
llvm-ir/
155 lines
regbankselect/
63 lines

Diff 205550

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 414 Lines • ▼ Show 20 Lines if (Status != Legalized)
return Status; return Status;
break; break;
} }
case TargetOpcode::G_FPTOSI: case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI: { case TargetOpcode::G_FPTOUI: {
// FIXME: Support other types // FIXME: Support other types
unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
if (ToSize != 32 || (FromSize != 32 && FromSize != 64)) if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
return UnableToLegalize; return UnableToLegalize;
LegalizeResult Status = conversionLibcall( LegalizeResult Status = conversionLibcall(
MI, MIRBuilder, Type::getInt32Ty(Ctx), MI, MIRBuilder,
ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx)); FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
if (Status != Legalized) if (Status != Legalized)
return Status; return Status;
break; break;
} }
case TargetOpcode::G_SITOFP: case TargetOpcode::G_SITOFP:
case TargetOpcode::G_UITOFP: { case TargetOpcode::G_UITOFP: {
// FIXME: Support other types // FIXME: Support other types
▲ Show 20 Lines • Show All 2,677 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstructionSelector.cpp

Show First 20 Lines • Show All 361 Lines • ▼ Show 20 Lines case G_FABS: {
unsigned FABSOpcode = unsigned FABSOpcode =
Size == 32 ? Mips::FABS_S Size == 32 ? Mips::FABS_S
: STI.isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32; : STI.isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32;
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode)) MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode))
.add(I.getOperand(0)) .add(I.getOperand(0))
.add(I.getOperand(1)); .add(I.getOperand(1));
break; break;
} }
case G_FPTOSI: {
unsigned SizeInt = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
atanasyanUnsubmitted
Done
ReplyInline Actions

Maybe use the same terms as in the LegalizerHelper: FromSize and ToSize? Just for uniformity.

atanasyan: Maybe use the same terms as in the LegalizerHelper: FromSize and ToSize? Just for uniformity.
unsigned SizeFP = MRI.getType(I.getOperand(1).getReg()).getSizeInBits();
assert((SizeInt == 32 && (SizeFP == 32 || SizeFP == 64)) &&
atanasyanUnsubmitted
Done
ReplyInline Actions

In the MipsRegisterBankInfo::getInstrMapping the same checking made by a couple of assert. Let's either split this check or merge the check in the MipsRegisterBankInfo::getInstrMapping. As well for uniformity

atanasyan: In the `MipsRegisterBankInfo::getInstrMapping` the same checking made by a couple of assert.
"Unsupported operand size for G_FPTOSI");
unsigned Opcode;
if (SizeFP == 32)
Opcode = Mips::TRUNC_W_S;
else
Opcode = STI.isFP64bit() ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32;
unsigned ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass);
MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
.addDef(ResultInFPR)
.addUse(I.getOperand(1).getReg());
if (!constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI))
return false;
MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1))
.addDef(I.getOperand(0).getReg())
.addUse(ResultInFPR);
if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
return false;
I.eraseFromParent();
return true;
}
case G_GLOBAL_VALUE: { case G_GLOBAL_VALUE: {
const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal(); const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal();
if (MF.getTarget().isPositionIndependent()) { if (MF.getTarget().isPositionIndependent()) {
MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
.addDef(I.getOperand(0).getReg()) .addDef(I.getOperand(0).getReg())
.addReg(MF.getInfo<MipsFunctionInfo>() .addReg(MF.getInfo<MipsFunctionInfo>()
->getGlobalBaseRegForGlobalISel()) ->getGlobalBaseRegForGlobalISel())
.addGlobalAddress(GVal); .addGlobalAddress(GVal);
▲ Show 20 Lines • Show All 221 Lines • Show Last 20 Lines

lib/Target/Mips/MipsLegalizerInfo.cpp

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR})
.libcallFor({s32, s64}); .libcallFor({s32, s64});
getActionDefinitionsBuilder(G_FPEXT) getActionDefinitionsBuilder(G_FPEXT)
.legalFor({{s64, s32}}); .legalFor({{s64, s32}});
getActionDefinitionsBuilder(G_FPTRUNC) getActionDefinitionsBuilder(G_FPTRUNC)
.legalFor({{s32, s64}}); .legalFor({{s32, s64}});
// FP to int conversion instructions
getActionDefinitionsBuilder(G_FPTOSI)
.legalForCartesianProduct({s32}, {s64, s32})
.libcallForCartesianProduct({s64}, {s64, s32})
.minScalar(0, s32);
getActionDefinitionsBuilder(G_FPTOUI)
.libcallForCartesianProduct({s64}, {s64, s32})
.minScalar(0, s32);
computeTables(); computeTables();
verify(*ST.getInstrInfo()); verify(*ST.getInstrInfo());
} }
bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI, bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
MachineRegisterInfo &MRI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder, MachineIRBuilder &MIRBuilder,
GISelChangeObserver &Observer) const { GISelChangeObserver &Observer) const {
using namespace TargetOpcode; using namespace TargetOpcode;
MIRBuilder.setInstr(MI); MIRBuilder.setInstr(MI);
return false; return false;
} }

lib/Target/Mips/MipsRegisterBankInfo.cpp

Show First 20 Lines • Show All 164 Lines • ▼ Show 20 LinesMipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case G_FPEXT: case G_FPEXT:
OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::DPRIdx], OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::DPRIdx],
&Mips::ValueMappings[Mips::SPRIdx]}); &Mips::ValueMappings[Mips::SPRIdx]});
break; break;
case G_FPTRUNC: case G_FPTRUNC:
OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::SPRIdx], OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::SPRIdx],
&Mips::ValueMappings[Mips::DPRIdx]}); &Mips::ValueMappings[Mips::DPRIdx]});
break; break;
case G_FPTOSI: {
unsigned SizeInt = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
unsigned SizeFP = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
assert((SizeInt == 32) && "Unsupported integer size");
assert((SizeFP == 32 || SizeFP == 64) && "Unsupported floating point size");
OperandsMapping = getOperandsMapping({
&Mips::ValueMappings[Mips::GPRIdx],
SizeFP == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
: &Mips::ValueMappings[Mips::DPRIdx],
});
break;
}
case G_CONSTANT: case G_CONSTANT:
case G_FRAME_INDEX: case G_FRAME_INDEX:
case G_GLOBAL_VALUE: case G_GLOBAL_VALUE:
case G_BRCOND: case G_BRCOND:
OperandsMapping = OperandsMapping =
getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr}); getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr});
break; break;
case G_ICMP: case G_ICMP:
Show All 19 Lines

test/CodeGen/Mips/GlobalISel/instruction-select/fptosi_and_fptoui.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @f32toi32() {entry: ret void}
define void @f64toi32() {entry: ret void}
...
---
name: f32toi32
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: f32toi32
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[TRUNC_W_S:%[0-9]+]]:fgr32 = TRUNC_W_S [[COPY]]
; FP32: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_S]]
; FP32: $v0 = COPY [[MFC1_]]
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32toi32
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[TRUNC_W_S:%[0-9]+]]:fgr32 = TRUNC_W_S [[COPY]]
; FP64: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_S]]
; FP64: $v0 = COPY [[MFC1_]]
; FP64: RetRA implicit $v0
%0:fprb(s32) = COPY $f12
%1:gprb(s32) = G_FPTOSI %0(s32)
$v0 = COPY %1(s32)
RetRA implicit $v0
...
---
name: f64toi32
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: f64toi32
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[TRUNC_W_D32_:%[0-9]+]]:fgr32 = TRUNC_W_D32 [[COPY]]
; FP32: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_D32_]]
; FP32: $v0 = COPY [[MFC1_]]
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64toi32
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[TRUNC_W_D64_:%[0-9]+]]:fgr32 = TRUNC_W_D64 [[COPY]]
; FP64: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_D64_]]
; FP64: $v0 = COPY [[MFC1_]]
; FP64: RetRA implicit $v0
%0:fprb(s64) = COPY $d6
%1:gprb(s32) = G_FPTOSI %0(s64)
$v0 = COPY %1(s32)
RetRA implicit $v0
...

test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @f32toi64() {entry: ret void}
define void @f32toi32() {entry: ret void}
define void @f32toi16() {entry: ret void}
define void @f32toi8() {entry: ret void}
define void @f64toi64() {entry: ret void}
define void @f64toi32() {entry: ret void}
define void @f64toi16() {entry: ret void}
define void @f64toi8() {entry: ret void}
define void @f32tou64() {entry: ret void}
define void @f64tou64() {entry: ret void}
...
---
name: f32toi64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: f32toi64
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32: $f12 = COPY [[COPY]](s32)
; FP32: JAL &__fixsfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP32: $v0 = COPY [[COPY1]](s32)
; FP32: $v1 = COPY [[COPY2]](s32)
; FP32: RetRA implicit $v0, implicit $v1
; FP64-LABEL: name: f32toi64
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64: $f12 = COPY [[COPY]](s32)
; FP64: JAL &__fixsfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP64: $v0 = COPY [[COPY1]](s32)
; FP64: $v1 = COPY [[COPY2]](s32)
; FP64: RetRA implicit $v0, implicit $v1
%0:_(s32) = COPY $f12
%1:_(s64) = G_FPTOSI %0(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
$v0 = COPY %2(s32)
$v1 = COPY %3(s32)
RetRA implicit $v0, implicit $v1
...
---
name: f32toi32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: f32toi32
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP32: $v0 = COPY [[FPTOSI]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32toi32
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP64: $v0 = COPY [[FPTOSI]](s32)
; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
%1:_(s32) = G_FPTOSI %0(s32)
$v0 = COPY %1(s32)
RetRA implicit $v0
...
---
name: f32toi16
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: f32toi16
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP32: $v0 = COPY [[ASHR]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32toi16
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: $v0 = COPY [[ASHR]](s32)
; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
%1:_(s16) = G_FPTOSI %0(s32)
%2:_(s32) = G_SEXT %1(s16)
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: f32toi8
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: f32toi8
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP32: $v0 = COPY [[ASHR]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32toi8
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: $v0 = COPY [[ASHR]](s32)
; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
%1:_(s8) = G_FPTOSI %0(s32)
%2:_(s32) = G_SEXT %1(s8)
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: f64toi64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: f64toi64
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32: $d6 = COPY [[COPY]](s64)
; FP32: JAL &__fixdfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $v0, implicit-def $v1
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP32: $v0 = COPY [[COPY1]](s32)
; FP32: $v1 = COPY [[COPY2]](s32)
; FP32: RetRA implicit $v0, implicit $v1
; FP64-LABEL: name: f64toi64
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64: $d12_64 = COPY [[COPY]](s64)
; FP64: JAL &__fixdfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit-def $v0, implicit-def $v1
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP64: $v0 = COPY [[COPY1]](s32)
; FP64: $v1 = COPY [[COPY2]](s32)
; FP64: RetRA implicit $v0, implicit $v1
%0:_(s64) = COPY $d6
%1:_(s64) = G_FPTOSI %0(s64)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
$v0 = COPY %2(s32)
$v1 = COPY %3(s32)
RetRA implicit $v0, implicit $v1
...
---
name: f64toi32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: f64toi32
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP32: $v0 = COPY [[FPTOSI]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64toi32
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP64: $v0 = COPY [[FPTOSI]](s32)
; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
%1:_(s32) = G_FPTOSI %0(s64)
$v0 = COPY %1(s32)
RetRA implicit $v0
...
---
name: f64toi16
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: f64toi16
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP32: $v0 = COPY [[ASHR]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64toi16
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: $v0 = COPY [[ASHR]](s32)
; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
%1:_(s16) = G_FPTOSI %0(s64)
%2:_(s32) = G_SEXT %1(s16)
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: f64toi8
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: f64toi8
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP32: $v0 = COPY [[ASHR]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64toi8
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: $v0 = COPY [[ASHR]](s32)
; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
%1:_(s8) = G_FPTOSI %0(s64)
%2:_(s32) = G_SEXT %1(s8)
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: f32tou64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: f32tou64
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32: $f12 = COPY [[COPY]](s32)
; FP32: JAL &__fixunssfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP32: $v0 = COPY [[COPY1]](s32)
; FP32: $v1 = COPY [[COPY2]](s32)
; FP32: RetRA implicit $v0, implicit $v1
; FP64-LABEL: name: f32tou64
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64: $f12 = COPY [[COPY]](s32)
; FP64: JAL &__fixunssfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP64: $v0 = COPY [[COPY1]](s32)
; FP64: $v1 = COPY [[COPY2]](s32)
; FP64: RetRA implicit $v0, implicit $v1
%0:_(s32) = COPY $f12
%1:_(s64) = G_FPTOUI %0(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
$v0 = COPY %2(s32)
$v1 = COPY %3(s32)
RetRA implicit $v0, implicit $v1
...
---
name: f64tou64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: f64tou64
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32: $d6 = COPY [[COPY]](s64)
; FP32: JAL &__fixunsdfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $v0, implicit-def $v1
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP32: $v0 = COPY [[COPY1]](s32)
; FP32: $v1 = COPY [[COPY2]](s32)
; FP32: RetRA implicit $v0, implicit $v1
; FP64-LABEL: name: f64tou64
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64: $d12_64 = COPY [[COPY]](s64)
; FP64: JAL &__fixunsdfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit-def $v0, implicit-def $v1
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP64: $v0 = COPY [[COPY1]](s32)
; FP64: $v1 = COPY [[COPY2]](s32)
; FP64: RetRA implicit $v0, implicit $v1
%0:_(s64) = COPY $d6
%1:_(s64) = G_FPTOUI %0(s64)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
$v0 = COPY %2(s32)
$v1 = COPY %3(s32)
RetRA implicit $v0, implicit $v1
...

test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
define i64 @f32toi64(float %a) {
; MIPS32-LABEL: f32toi64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: jal __fixsfdi
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fptosi float %a to i64
ret i64 %conv
}
define i32 @f32toi32(float %a) {
; MIPS32-LABEL: f32toi32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.s $f0, $f12
; MIPS32-NEXT: mfc1 $2, $f0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fptosi float %a to i32
ret i32 %conv
}
define signext i16 @f32toi16(float %a) {
; MIPS32-LABEL: f32toi16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.s $f0, $f12
; MIPS32-NEXT: mfc1 $1, $f0
; MIPS32-NEXT: sll $1, $1, 16
; MIPS32-NEXT: sra $2, $1, 16
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fptosi float %a to i16
ret i16 %conv
}
define signext i8 @f32toi8(float %a) {
; MIPS32-LABEL: f32toi8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.s $f0, $f12
; MIPS32-NEXT: mfc1 $1, $f0
; MIPS32-NEXT: sll $1, $1, 24
; MIPS32-NEXT: sra $2, $1, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fptosi float %a to i8
ret i8 %conv
}
define i64 @f64toi64(double %a) {
; MIPS32-LABEL: f64toi64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: jal __fixdfdi
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fptosi double %a to i64
ret i64 %conv
}
define i32 @f64toi32(double %a) {
; MIPS32-LABEL: f64toi32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.d $f0, $f12
; MIPS32-NEXT: mfc1 $2, $f0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fptosi double %a to i32
ret i32 %conv
}
define signext i16 @f64toi16(double %a) {
; MIPS32-LABEL: f64toi16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.d $f0, $f12
; MIPS32-NEXT: mfc1 $1, $f0
; MIPS32-NEXT: sll $1, $1, 16
; MIPS32-NEXT: sra $2, $1, 16
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fptosi double %a to i16
ret i16 %conv
}
define signext i8 @f64toi8(double %a) {
; MIPS32-LABEL: f64toi8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.d $f0, $f12
; MIPS32-NEXT: mfc1 $1, $f0
; MIPS32-NEXT: sll $1, $1, 24
; MIPS32-NEXT: sra $2, $1, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fptosi double %a to i8
ret i8 %conv
}
define i64 @f32tou64(float %a) {
; MIPS32-LABEL: f32tou64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: jal __fixunssfdi
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fptoui float %a to i64
ret i64 %conv
}
define i64 @f64tou64(double %a) {
; MIPS32-LABEL: f64tou64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: jal __fixunsdfdi
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fptoui double %a to i64
ret i64 %conv
}

test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @f32toi32() {entry: ret void}
define void @f64toi32() {entry: ret void}
...
---
name: f32toi32
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: f32toi32
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; FP32: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s32)
; FP32: $v0 = COPY [[FPTOSI]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32toi32
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; FP64: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s32)
; FP64: $v0 = COPY [[FPTOSI]](s32)
; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
%1:_(s32) = G_FPTOSI %0(s32)
$v0 = COPY %1(s32)
RetRA implicit $v0
...
---
name: f64toi32
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: f64toi32
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
; FP32: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s64)
; FP32: $v0 = COPY [[FPTOSI]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64toi32
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
; FP64: [[FPTOSI:%[0-9]+]]:gprb(s32) = G_FPTOSI [[COPY]](s64)
; FP64: $v0 = COPY [[FPTOSI]](s32)
; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
%1:_(s32) = G_FPTOSI %0(s64)
$v0 = COPY %1(s32)
RetRA implicit $v0
...