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Differential D63413

AMDGPU/GlobalISel: RegBankSelect for WWM/WQM
ClosedPublic

Authored by arsenm on Jun 17 2019, 4:43 AM.

Details

Reviewers
nhaehnle
tpr
sheredom
tstellar

Diff Detail

Event Timeline

arsenm created this revision.Jun 17 2019, 4:43 AM
Herald added subscribers: Petar.Avramovic, t-tye, dstuttard and 6 others. · View Herald TranscriptJun 17 2019, 4:43 AM
arsenm added a comment.Jun 24 2019, 9:18 AM

ping

nhaehnle accepted this revision.Jul 1 2019, 2:41 AM

LGTM

This revision is now accepted and ready to land.Jul 1 2019, 2:41 AM
arsenm closed this revision.Jul 1 2019, 6:30 AM

r364763

Revision Contents

PathSize
lib/
Target/
AMDGPU/
2 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
31 lines
31 lines

Diff 205031

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 1,574 Lines • ▼ Show 20 Lines case AMDGPU::G_INTRINSIC: {
case Intrinsic::amdgcn_fdot2: case Intrinsic::amdgcn_fdot2:
case Intrinsic::amdgcn_sdot2: case Intrinsic::amdgcn_sdot2:
case Intrinsic::amdgcn_udot2: case Intrinsic::amdgcn_udot2:
case Intrinsic::amdgcn_sdot4: case Intrinsic::amdgcn_sdot4:
case Intrinsic::amdgcn_udot4: case Intrinsic::amdgcn_udot4:
case Intrinsic::amdgcn_sdot8: case Intrinsic::amdgcn_sdot8:
case Intrinsic::amdgcn_udot8: case Intrinsic::amdgcn_udot8:
case Intrinsic::amdgcn_fdiv_fast: case Intrinsic::amdgcn_fdiv_fast:
case Intrinsic::amdgcn_wwm:
case Intrinsic::amdgcn_wqm:
return getDefaultMappingVOP(MI); return getDefaultMappingVOP(MI);
case Intrinsic::amdgcn_ds_permute: case Intrinsic::amdgcn_ds_permute:
case Intrinsic::amdgcn_ds_bpermute: case Intrinsic::amdgcn_ds_bpermute:
return getDefaultMappingAllVGPR(MI); return getDefaultMappingAllVGPR(MI);
case Intrinsic::amdgcn_kernarg_segment_ptr: case Intrinsic::amdgcn_kernarg_segment_ptr:
case Intrinsic::amdgcn_s_memtime: case Intrinsic::amdgcn_s_memtime:
case Intrinsic::amdgcn_s_memrealtime: case Intrinsic::amdgcn_s_memrealtime:
case Intrinsic::amdgcn_s_getpc: case Intrinsic::amdgcn_s_getpc:
▲ Show 20 Lines • Show All 238 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
---
name: wqm_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: wqm_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), [[COPY]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), %0
...
---
name: wqm_v
legalized: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: wqm_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), %0
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
---
name: wwm_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: wwm_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wwm), [[COPY]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wwm), %0
...
---
name: wwm_v
legalized: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: wwm_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wwm), [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wwm), %0
...