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Differential D62863

[AArch64] Handle ISD::LRINT and ISD::LLRINT for float16
ClosedPublic

Authored by zatrazz on Jun 4 2019, 9:18 AM.

Details

Reviewers
efriedma
SjoerdMeijer
javed.absar
evandro
Commits
rG559e69a821bc: AArch64] Handle ISD::LRINT and ISD::LLRINT for float16
rL362700: AArch64] Handle ISD::LRINT and ISD::LLRINT for float16
Summary

This patch is a follow up for D62018 to add lrint/llrint support for float16.

Diff Detail

Repository
rL LLVM

Event Timeline

zatrazz created this revision.Jun 4 2019, 9:18 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald TranscriptJun 4 2019, 9:18 AM
SjoerdMeijer accepted this revision.Jun 5 2019, 1:38 AM

Thanks for following up. This looks good to me.

This revision is now accepted and ready to land.Jun 5 2019, 1:38 AM
Closed by commit rL362700: AArch64] Handle ISD::LRINT and ISD::LLRINT for float16 (authored by azanella). · Explain WhyJun 6 2019, 5:39 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AArch64/
8 lines
test/
CodeGen/
AArch64/
35 lines
36 lines
35 lines

Diff 203334

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,162 Lines • ▼ Show 20 Lines
let Predicates = [HasFRInt3264] in { let Predicates = [HasFRInt3264] in {
defm FRINT32Z : FRIntNNT<0b00, "frint32z">; defm FRINT32Z : FRIntNNT<0b00, "frint32z">;
defm FRINT64Z : FRIntNNT<0b10, "frint64z">; defm FRINT64Z : FRIntNNT<0b10, "frint64z">;
defm FRINT32X : FRIntNNT<0b01, "frint32x">; defm FRINT32X : FRIntNNT<0b01, "frint32x">;
defm FRINT64X : FRIntNNT<0b11, "frint64x">; defm FRINT64X : FRIntNNT<0b11, "frint64x">;
} // HasFRInt3264 } // HasFRInt3264
let Predicates = [HasFullFP16] in {
def : Pat<(i32 (lrint f16:$Rn)),
(FCVTZSUWHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>;
def : Pat<(i64 (lrint f16:$Rn)),
(FCVTZSUXHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>;
def : Pat<(i64 (llrint f16:$Rn)),
(FCVTZSUXHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>;
}
def : Pat<(i32 (lrint f32:$Rn)), def : Pat<(i32 (lrint f32:$Rn)),
(FCVTZSUWSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>; (FCVTZSUWSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
def : Pat<(i32 (lrint f64:$Rn)), def : Pat<(i32 (lrint f64:$Rn)),
(FCVTZSUWDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>; (FCVTZSUWDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
def : Pat<(i64 (lrint f32:$Rn)), def : Pat<(i64 (lrint f32:$Rn)),
(FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>; (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
def : Pat<(i64 (lrint f64:$Rn)), def : Pat<(i64 (lrint f64:$Rn)),
(FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>; (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
▲ Show 20 Lines • Show All 3,708 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/llrint-conv-fp16.ll

; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
; CHECK-LABEL: testmhhs:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs x0, h0
; CHECK: ret
define i16 @testmhhs(half %x) {
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
%conv = trunc i64 %0 to i16
ret i16 %conv
}
; CHECK-LABEL: testmhws:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs x0, h0
; CHECK: ret
define i32 @testmhws(half %x) {
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: testmhxs:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs x0, h0
; CHECK: ret
define i64 @testmhxs(half %x) {
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
ret i64 %0
}
declare i64 @llvm.llrint.i64.f16(half) nounwind readnone

llvm/trunk/test/CodeGen/AArch64/lrint-conv-fp16-win.ll

; RUN: llc < %s -mtriple=aarch64-windows -mattr=+fullfp16 | FileCheck %s
; CHECK-LABEL: testmhhs:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs w0, h0
; CHECK-NEXT: ret
define i16 @testmhhs(half %x) {
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
%conv = trunc i32 %0 to i16
ret i16 %conv
}
; CHECK-LABEL: testmhws:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs w0, h0
; CHECK-NEXT: ret
define i32 @testmhws(half %x) {
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
ret i32 %0
}
; CHECK-LABEL: testmhxs:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs w8, h0
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
define i64 @testmhxs(half %x) {
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
%conv = sext i32 %0 to i64
ret i64 %conv
}
declare i32 @llvm.lrint.i32.f16(half) nounwind readnone

llvm/trunk/test/CodeGen/AArch64/lrint-conv-fp16.ll

; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
; CHECK-LABEL: testmhhs:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs x0, h0
; CHECK: ret
define i16 @testmhhs(half %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
%conv = trunc i64 %0 to i16
ret i16 %conv
}
; CHECK-LABEL: testmhws:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs x0, h0
; CHECK: ret
define i32 @testmhws(half %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: testmhxs:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs x0, h0
; CHECK: ret
define i64 @testmhxs(half %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
ret i64 %0
}
declare i64 @llvm.lrint.i64.f16(half) nounwind readnone