[AArch64] Handle ISD::LROUND and ISD::LLROUND for float16

[zatrazz]

Summary

This patch is a follow up for D61391 to add lround/llround support for float16.

[SjoerdMeijer]

Thanks for following up, this one LGTM too.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 defm : FPToIntegerPats<fp_to_uint, fceil,  "FCVTPU">;
 defm : FPToIntegerPats<fp_to_sint, ffloor, "FCVTMS">;
 defm : FPToIntegerPats<fp_to_uint, ffloor, "FCVTMU">;
 defm : FPToIntegerPats<fp_to_sint, ftrunc, "FCVTZS">;
 defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">;
 defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">;
 defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">;
 
+let Predicates = [HasFullFP16] in {
+  def : Pat<(i32 (lround f16:$Rn)),
+            (!cast<Instruction>(FCVTASUWHr) f16:$Rn)>;
+  def : Pat<(i64 (lround f16:$Rn)),
+            (!cast<Instruction>(FCVTASUXHr) f16:$Rn)>;
+  def : Pat<(i64 (llround f16:$Rn)),
+            (!cast<Instruction>(FCVTASUXHr) f16:$Rn)>;
+}
 def : Pat<(i32 (lround f32:$Rn)),
           (!cast<Instruction>(FCVTASUWSr) f32:$Rn)>;
 def : Pat<(i32 (lround f64:$Rn)),
           (!cast<Instruction>(FCVTASUWDr) f64:$Rn)>;
 def : Pat<(i64 (lround f32:$Rn)),
           (!cast<Instruction>(FCVTASUXSr) f32:$Rn)>;
 def : Pat<(i64 (lround f64:$Rn)),
           (!cast<Instruction>(FCVTASUXDr) f64:$Rn)>;

llvm/test/CodeGen/AArch64/llround-conv-fp16.ll

+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
+
+; CHECK-LABEL: testmhhs:
+; CHECK:       fcvtas  x0, h0
+; CHECK:       ret
+define i16 @testmhhs(half %x) {
+entry:
+  %0 = tail call i64 @llvm.llround.i64.f16(half %x)
+  %conv = trunc i64 %0 to i16
+  ret i16 %conv
+}
+
+; CHECK-LABEL: testmhws:
+; CHECK:       fcvtas  x0, h0
+; CHECK:       ret
+define i32 @testmhws(half %x) {
+entry:
+  %0 = tail call i64 @llvm.llround.i64.f16(half %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmhxs:
+; CHECK:       fcvtas  x0, h0
+; CHECK-NEXT:  ret
+define i64 @testmhxs(half %x) {
+entry:
+  %0 = tail call i64 @llvm.llround.i64.f16(half %x)
+  ret i64 %0
+}
+
+declare i64 @llvm.llround.i64.f16(half) nounwind readnone

llvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll

+; RUN: llc < %s -mtriple=aarch64-windows -mattr=+fullfp16 | FileCheck %s
+
+; CHECK-LABEL: testmhhs:
+; CHECK:       fcvtas  w0, h0
+; CHECK:       ret
+define i16 @testmhhs(half %x) {
+entry:
+  %0 = tail call i32 @llvm.lround.i32.f16(half %x)
+  %conv = trunc i32 %0 to i16
+  ret i16 %conv
+}
+
+; CHECK-LABEL: testmhws:
+; CHECK:       fcvtas  w0, h0
+; CHECK:       ret
+define i32 @testmhws(half %x) {
+entry:
+  %0 = tail call i32 @llvm.lround.i32.f16(half %x)
+  ret i32 %0
+}
+
+; CHECK-LABEL: testmhxs:
+; CHECK:       fcvtas  w8, h0
+; CHECK-NEXT:  sxtw    x0, w8
+; CHECK-NEXT:  ret
+define i64 @testmhxs(half %x) {
+entry:
+  %0 = tail call i32 @llvm.lround.i32.f16(half %x)
+  %conv = sext i32 %0 to i64
+  ret i64 %conv
+}
+
+declare i32 @llvm.lround.i32.f16(half) nounwind readnone

llvm/test/CodeGen/AArch64/lround-conv-fp16.ll

+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
+
+; CHECK-LABEL: testmhhs:
+; CHECK:       fcvtas  x0, h0
+; CHECK:       ret
+define i16 @testmhhs(half %x) {
+entry:
+  %0 = tail call i64 @llvm.lround.i64.f16(half %x)
+  %conv = trunc i64 %0 to i16
+  ret i16 %conv
+}
+
+; CHECK-LABEL: testmhws:
+; CHECK:       fcvtas  x0, h0
+; CHECK:       ret
+define i32 @testmhws(half %x) {
+entry:
+  %0 = tail call i64 @llvm.lround.i64.f16(half %x)
+  %conv = trunc i64 %0 to i32
+  ret i32 %conv
+}
+
+; CHECK-LABEL: testmhxs:
+; CHECK:       fcvtas  x0, h0
+; CHECK-NEXT:  ret
+define i64 @testmhxs(half %x) {
+entry:
+  %0 = tail call i64 @llvm.lround.i64.f16(half %x)
+  ret i64 %0
+}
+
+declare i64 @llvm.lround.i64.f16(half) nounwind readnone