[PowerPC] reorder LSR and PPCCTRLoops pass

[shchenz]

Summary

Currently pass LSR runs before PPCCTRLoops, we meet some problem with this order because of the icmp inside loop which compares iteration indexed and loop trip count. In pass LSR, we always treat that icmp as a valid ICmpZero type LSRUse. But this is not true because in later pass PPCCTRLoops, we may replace this icmp with ctrloop instruction bdnz. So we may get suboptimal code based on this order.

Reordering LSR and PPCCTRLoops makes LSR know precisely whether the icmp replaced or kept in PPCCTRLoops

Get improvement for most benchmarks of SPEC CPU2017 on Power9. Biggest gain is xz, about 3.5%. No degradation found.

[hfinkel]

I'm really uneasy about this change. PPCCTRLoops inserts special loop intrinsics which the rest of the loop-optimization pipeline doesn't understand, and so logically, it should come last. It's pretty clear that LSR is interfering with PPCCTRLoops, is this because it transforms the loops into some form that SCEV doesn't understand? Could we adjust LSR to make it more friendly to hardware-assisted loops? In theory, if LSR had the right cost model, it could actually make *more* loops that PPCCTRLoops could handle, and not fewer?

[hfinkel]

Also, please make sure that you look at D62604.

[shchenz]

In D62847#1529703, @hfinkel wrote:

I'm really uneasy about this change. PPCCTRLoops inserts special loop intrinsics which the rest of the loop-optimization pipeline doesn't understand, and so logically, it should come last. It's pretty clear that LSR is interfering with PPCCTRLoops, is this because it transforms the loops into some form that SCEV doesn't understand? Could we adjust LSR to make it more friendly to hardware-assisted loops? In theory, if LSR had the right cost model, it could actually make *more* loops that PPCCTRLoops could handle, and not fewer?

Thanks for your comment Hal @hfinkel . I create this patch mostly because of the suboptimal loop instructions in some testcases. Making more hardware loops is not this patch's original intention. Seems reorder these two passes can generate more hardware loop. One suboptimal loop instructions example is in file test/CodeGen/PowerPC/lsr-ctrloop.ll, we see that there is one redundant instruction add 5, 3, 4 inside the loop. After investigate this issue, we found this is caused by ICmpZero LSRUse. After LSR gathers all formulaes for all LSRUse, for the case, all stores inside the loop is a user for both addrec reg({0,+,384} and reg({(192 + %0),+,384}), but ICmpZero LSRUse only has use for addrec reg({0,+,384}), so when LSR try to narrow down the search space, it selects addrec reg({0,+,384}) as a winner since its usage number is bigger than reg({(192 + %0),+,384}). But the issue is: by using reg({(192 + %0),+,384}), we can get better code in LSR. You can see the difference in the testcase.

Yes, I tried to add a target hook function in PPCTargetTransformationInfo class, let's say canConvertToHardwareLoop. This function should be called in LSR through TTI and in PPCCTRLoops to check if a loop can be converted to hardware loop. And it should come from current condition check code in PPCCTRLoops. But there is some disadvantage about this solution:
1: The condition check code in PPCCTRLoops pass uses many Analysis Pass result, like LoopInfo, SCEV, DominatorTree, AssumptionCache, DataLayout, TargetLibraryInfo, TargetTransformInfo and so on, we need to pass all these infos from LSR/PPCCTRLoops to the target hook funciton in PPCTargetTransformationInfo. When I implemented like this way, I am a little worried this maybe a little 'heavy' for a target hook compared with other exist functions in PPCTargetTransformationInfo? Seems now https://reviews.llvm.org/D62604 implements like this, but at that time when I did this, it is not so straightforward for me.
2: Most important reason is, all above Analysis Pass results may be different at the point LSR calling canConvertToHardwareLoop and the point PPCCTRLoops calling canConvertToHardwareLoop , so it is possible that canConvertToHardwareLoop returns different value to LSR and PPCCTRLoops, then the ICmpZero is still not accurate and LSR still generates suboptimal instructions.

For the loop intrinsics generated before LSR, as I can see, LSR can still recognize it as a loop and I saw PPCLoopPreIncPrep can also transform the loop with intrinsics to a pre-inc loop when I tested it. So I guess LoopInfoWrapperPass can still recognize it as a Loop? Maybe you mean the loop trip count can not be got by the loop since it is now in loop preheader by calling the intrinsics? I am not sure about the impact since some impartant loop passes depending on loop trip count like loop unroll, loop vectorize are all before LSR and PPCCTRLoops. It would be great if you can give more detail about the impact?

[shchenz]

Abandon this patch.

Change to another solution in https://reviews.llvm.org/D63477

llvm/lib/Target/PowerPC/PPCTargetMachine.cpp

if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
     // Call EarlyCSE pass to find and remove subexpressions in the lowered
     // result.
     addPass(createEarlyCSEPass());
     // Do loop invariant code motion in case part of the lowered result is
     // invariant.
     addPass(createLICMPass());
   }
 
+  // LSR Pass always generates ICmpZero LSRUse for a loop trip count compare.
+  // PPCCTRLoops pass may transform this loop trip count compare to a hardware
+  // loop.
+  // So putting PPCCTRLoops pass to front of LSR can make LSR more precisely
+  // about generating ICmpZero.
+  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
+    addPass(createPPCCTRLoops());
+
   TargetPassConfig::addIRPasses();
 }
 
 bool PPCPassConfig::addPreISel() {
   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
 
-  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
-    addPass(createPPCCTRLoops());
-
   return false;
 }
 
 bool PPCPassConfig::addILPOpts() {
   addPass(&EarlyIfConverterID);
 
   if (EnableMachineCombinerPass)
     addPass(&MachineCombinerID);

llvm/test/CodeGen/PowerPC/addi-licm.ll

entry:
   %1 = bitcast [2048 x float]* %y to i8*
   call void @llvm.lifetime.start.p0i8(i64 8192, i8* %1) #2
   br label %for.body.i
 
 ; CHECK-LABEL: @foo
 ; CHECK: addi [[REG1:[0-9]+]], 1,
 ; CHECK: addi [[REG2:[0-9]+]], 1,
 ; CHECK: %for.body.i
-; CHECK-DAG: lfsx {{[0-9]+}}, [[REG1]],
-; CHECK-DAG: lfsx {{[0-9]+}}, [[REG2]],
+; CHECK-DAG: lfs {{[0-9]+}}, 0([[REG1]])
+; CHECK-DAG: lfs {{[0-9]+}}, 0([[REG2]])
 ; CHECK: blr
 
 ; PIP-LABEL: @foo
 ; PIP: addi [[REG1:[0-9]+]], 1,
 ; PIP: addi [[REG2:[0-9]+]], 1,
 ; PIP: %for.body.i
 ; PIP-DAG: lfsu {{[0-9]+}}, 4([[REG1]])
 ; PIP-DAG: lfsu {{[0-9]+}}, 4([[REG2]])

llvm/test/CodeGen/PowerPC/ctrloop-le.ll

 ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
-; XFAIL: *
-; SE needs improvement
-
 ; CHECK: test_pos1_ir_sle
 ; CHECK: bdnz
 ; a < b
 define void @test_pos1_ir_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp sle i32 28395, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 

llvm/test/CodeGen/PowerPC/ctrloop-lt.ll

 ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
-; XFAIL: *
-; SE needs improvement
-
 ; CHECK: test_pos1_ir_slt
 ; CHECK: bdnz
 ; a < b
 define void @test_pos1_ir_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 8531, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 

 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 
 
 ; CHECK: test_pos2_ir_slt
-; FIXME: Support this loop!
 ; CHECK: bdnz
 ; a < b
 define void @test_pos2_ir_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 9152, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry

 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 
 
 ; CHECK: test_pos4_ir_slt
-; FIXME: Support this loop!
 ; CHECK: bdnz
 ; a < b
 define void @test_pos4_ir_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 18851, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry

llvm/test/CodeGen/PowerPC/ctrloop-ne.ll

 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 
 
 ; CHECK: test_pos2_ir_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
 ; a < b
 define void @test_pos2_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 29554, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry
   br label %for.body

 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 
 
 ; CHECK: test_pos4_ir_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
 ; a < b
 define void @test_pos4_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 15692, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry
   br label %for.body

 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 
 
 ; CHECK: test_pos8_ir_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
 ; a < b
 define void @test_pos8_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 10449, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry
   br label %for.body

 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 
 
 ; CHECK: test_pos16_ir_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
 ; a < b
 define void @test_pos16_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 32087, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry
   br label %for.body

 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 
 
 ; CHECK: test_pos2_ri_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
 ; a < b
 define void @test_pos2_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 %a, 8730
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry
   br label %for.body

 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 
 
 ; CHECK: test_pos4_ri_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
 ; a < b
 define void @test_pos4_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 %a, 1493
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry
   br label %for.body

 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 
 
 ; CHECK: test_pos8_ri_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
 ; a < b
 define void @test_pos8_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 %a, 1706
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry
   br label %for.body

 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 
 
 ; CHECK: test_pos16_ri_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
 ; a < b
 define void @test_pos16_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 %a, 1886
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry
   br label %for.body

 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 
 
 ; CHECK: test_pos2_rr_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
 ; a < b
 define void @test_pos2_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 %a, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry
   br label %for.body

 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 
 
 ; CHECK: test_pos4_rr_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
 ; a < b
 define void @test_pos4_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 %a, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry
   br label %for.body

 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 
 
 ; CHECK: test_pos8_rr_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
 ; a < b
 define void @test_pos8_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 %a, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry
   br label %for.body

 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 
 
 ; CHECK: test_pos16_rr_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
 ; a < b
 define void @test_pos16_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
 entry:
   %cmp3 = icmp slt i32 %a, %b
   br i1 %cmp3, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %entry
   br label %for.body

llvm/test/CodeGen/PowerPC/ctrloop-shortLoops.ll

for.body:                                         ; preds = %entry, %for.body
   %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %0, %Sum.05
   %indvars.iv.next = add nsw i64 %indvars.iv, -1
   %tobool = icmp eq i64 %indvars.iv, 0
   br i1 %tobool, label %for.cond.cleanup, label %for.body
 }
 
 ; Function Attrs: norecurse nounwind
+; On core a2q, IssueWidth is 1. On core pwr8, IssueWidth is 8.
+; a2q should use mtctr, but pwr8 should not use mtctr.
 define signext i32 @testTripCount2NonSmallLoop() {
 ; CHECK-LABEL: testTripCount2NonSmallLoop:
-; CHECK: bge
+; CHECK-A2Q: mtctr
+; CHECK-PWR8-NOT: mtctr
 ; CHECK: blr
 
 entry:
   %.pre = load i32, i32* @a, align 4
   br label %for.body
 
 for.body:                                         ; preds = %entry, %if.end
   %0 = phi i32 [ %.pre, %entry ], [ %1, %if.end ]

llvm/test/CodeGen/PowerPC/lsr-ctrloop.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
 ; void foo(float *data, float d) {
 ;   long i;
 ;   for (i = 0; i < 8000; i++)
 ;     data[i] = d;
 ; }
 ; 
 ; This loop will be unrolled by 96 and vectorized on power9.
 ; icmp for loop iteration index and loop trip count(384) has LSRUse for 'reg({0,+,384})'.
 ; Make sure above icmp does not impact LSR choose best formulae sets based on 'reg({(192 + %0),+,384})' 
 
 define void @foo(float* nocapture %data, float %d) {
 ; CHECK-LABEL: foo:
-; CHECK:  .LBB0_1: # %vector.body
-; CHECK:         add 5, 3, 4
-; CHECK-NEXT:    stxvx 0, 3, 4
+; CHECK:       .LBB0_1: # %vector.body
+; CHECK:         stxv 0, -192(4)
+; CHECK-NEXT:    stxv 0, -176(4)
+; CHECK-NEXT:    stxv 0, -160(4)
+; CHECK-NEXT:    stxv 0, -144(4)
+; CHECK-NEXT:    stxv 0, -128(4)
+; CHECK-NEXT:    stxv 0, -112(4)
+; CHECK-NEXT:    stxv 0, -96(4)
+; CHECK-NEXT:    stxv 0, -80(4)
+; CHECK-NEXT:    stxv 0, -64(4)
+; CHECK-NEXT:    stxv 0, -48(4)
+; CHECK-NEXT:    stxv 0, -32(4)
+; CHECK-NEXT:    stxv 0, -16(4)
+; CHECK-NEXT:    stxv 0, 0(4)
+; CHECK-NEXT:    stxv 0, 16(4)
+; CHECK-NEXT:    stxv 0, 32(4)
+; CHECK-NEXT:    stxv 0, 48(4)
+; CHECK-NEXT:    stxv 0, 64(4)
+; CHECK-NEXT:    stxv 0, 80(4)
+; CHECK-NEXT:    stxv 0, 96(4)
+; CHECK-NEXT:    stxv 0, 112(4)
+; CHECK-NEXT:    stxv 0, 128(4)
+; CHECK-NEXT:    stxv 0, 144(4)
+; CHECK-NEXT:    stxv 0, 160(4)
+; CHECK-NEXT:    stxv 0, 176(4)
 ; CHECK-NEXT:    addi 4, 4, 384
-; CHECK-NEXT:    stxv 0, 16(5)
-; CHECK-NEXT:    stxv 0, 32(5)
-; CHECK-NEXT:    stxv 0, 48(5)
-; CHECK-NEXT:    stxv 0, 64(5)
-; CHECK-NEXT:    stxv 0, 80(5)
-; CHECK-NEXT:    stxv 0, 96(5)
-; CHECK-NEXT:    stxv 0, 112(5)
-; CHECK-NEXT:    stxv 0, 128(5)
-; CHECK-NEXT:    stxv 0, 144(5)
-; CHECK-NEXT:    stxv 0, 160(5)
-; CHECK-NEXT:    stxv 0, 176(5)
-; CHECK-NEXT:    stxv 0, 192(5)
-; CHECK-NEXT:    stxv 0, 208(5)
-; CHECK-NEXT:    stxv 0, 224(5)
-; CHECK-NEXT:    stxv 0, 240(5)
-; CHECK-NEXT:    stxv 0, 256(5)
-; CHECK-NEXT:    stxv 0, 272(5)
-; CHECK-NEXT:    stxv 0, 288(5)
-; CHECK-NEXT:    stxv 0, 304(5)
-; CHECK-NEXT:    stxv 0, 320(5)
-; CHECK-NEXT:    stxv 0, 336(5)
-; CHECK-NEXT:    stxv 0, 352(5)
-; CHECK-NEXT:    stxv 0, 368(5)
 ; CHECK-NEXT:    bdnz .LBB0_1
 
 entry:
   %broadcast.splatinsert16 = insertelement <4 x float> undef, float %d, i32 0
   %broadcast.splat17 = shufflevector <4 x float> %broadcast.splatinsert16, <4 x float> undef, <4 x i32> zeroinitializer
   %broadcast.splatinsert18 = insertelement <4 x float> undef, float %d, i32 0
   %broadcast.splat19 = shufflevector <4 x float> %broadcast.splatinsert18, <4 x float> undef, <4 x i32> zeroinitializer
   %broadcast.splatinsert20 = insertelement <4 x float> undef, float %d, i32 0

llvm/test/CodeGen/PowerPC/stwu-sched.ll

 ; RUN: llc  -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s
 ; RUN: llc  -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s
-; RUN: llc  -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s \
-; RUN: --check-prefix=CHECK-ITIN
-; RUN: llc  -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s \
-; RUN: --check-prefix=CHECK-ITIN
+; RUN: llc  -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -disable-ppc-ctrloops < %s -verify-machineinstrs \
+; RUN: | FileCheck %s --check-prefix=CHECK-ITIN 
+; RUN: llc  -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -disable-ppc-ctrloops < %s -verify-machineinstrs \
+; RUN: | FileCheck %s --check-prefix=CHECK-ITIN
 
 
 %0 = type { i32, i32 }
 
 ; Function Attrs: norecurse nounwind writeonly
 define void @initCombList(%0* nocapture, i32 signext) local_unnamed_addr #0 {
 ; CHECK-LABEL: initCombList:
 ; CHECK: addi 4, 4, -8
-; CHECK: stwu 5, 64(3)
-
+; CHECK: stwu 4, 64(3) 
 ; CHECK-ITIN-LABEL: initCombList:
 ; CHECK-ITIN: stwu 5, 64(4)
 ; CHECK-ITIN-NEXT:   addi 3, 3, -8
 
-
   %3 = zext i32 %1 to i64
   br i1 undef, label %6, label %4
 
 ; <label>:4:                                      ; preds = %2
   store i32 0, i32* undef, align 4, !tbaa !1
   %5 = add nuw nsw i64 0, 1
   br label %6
 

llvm/test/CodeGen/PowerPC/unal-altivec.ll

vector.body:                                      ; preds = %vector.body, %vector.ph
   %8 = getelementptr float, float* %a, i64 %.sum12
   %9 = bitcast float* %8 to <4 x float>*
   store <4 x float> %5, <4 x float>* %9, align 4
   %index.next = add i64 %index, 8
   %10 = icmp eq i64 %index.next, 16000
   br i1 %10, label %for.end, label %vector.body
 
 ; CHECK: @foo
-; CHECK-DAG: li [[C0:[0-9]+]], 0
+; CHECK-DAG: li [[C16:[0-9]+]], 16
 ; CHECK-DAG: lvx [[CNST:[0-9]+]],
 ; CHECK: .LBB0_1:
-; CHECK-DAG: lvsl [[MASK1:[0-9]+]], [[B1:[0-9]+]], [[C0]]
-; CHECK-DAG: add [[B3:[0-9]+]], [[B1]], [[C0]]
-; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
-; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]],
-; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
-; CHECK-DAG: vaddfp {{[0-9]+}}, [[R1]], [[CNST]]
+; CHECK-DAG: lvx [[LD1:[0-9]+]], 0, [[C0:[0-9]+]]
+; CHECK-DAG: lvx [[LD2:[0-9]+]], [[C0]], [[C16]]
+; CHECK-DAG: lvsl [[MASK1:[0-9]+]], 0, [[C0]]
+; CHECK-DAG: vperm [[VR1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
+; CHECK-DAG: vaddfp {{[0-9]+}}, [[VR1]], [[CNST]]
 ; CHECK: blr
 
 for.end:                                          ; preds = %vector.body
   ret void
 }
 
 attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll

entry:
   ret void
 }
 
 ; ISEL matches address mode xaddrX4 and generates LI which can be moved outside of
 ; loop.
 define i64 @test_xaddrX4_loop(i8* %p) {
 ; CHECK-LABEL: test_xaddrX4_loop:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r5, 8
+; CHECK-NEXT:    mtctr r5
 ; CHECK-NEXT:    addi r4, r3, -8
-; CHECK-NEXT:    li r3, 8
-; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    li r5, 3
 ; loop instruction number is changed from 5 to 4, so its align is changed from 5 to 4.
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB4_1: # %for.body
 ; CHECK:         ldu r6, 8(r4)
 ; CHECK-NEXT:    ldx r7, r4, r5
 ; CHECK-NEXT:    maddld r3, r7, r6, r3