[X86] remove derived method w/ same impl as base

[nickdesaulniers]

Summary

While looking into issues with IfConverter, I noticed that
X86InstrInfo::isUnpredicatedTerminator matched its overriden
implementation in TargetInstrInfo::isUnpredicatedTerminator.

[nickdesaulniers]

Adding @hfinkel for review because I think we can go further. The only other override of TargetInstrInfo::isUnpredicatedTerminator is PPCInstrInfo::isUnpredicatedTerminator and it almost matches, modulo a check for whether the MachineInstr isPredicable. I'm not sure if that's intentional, or bug, but adding return TargetInstrInfo::isUnpredicatedTerminator(MI); as the first statement in PPCInstrInfo::isUnpredicatedTerminator doesn't cause any failures in existing tests.

[echristo]

This is ok. I think the other change is also fine, feel free to upload a diff. :)

[MaskRay]

Typo in the description:

matched its override base class'

overridden

llvm/lib/Target/X86/X86InstrInfo.h

public:
   /// results into instruction with adjusted opcode:
   ///     FMA231 #3, #2, #1
   unsigned
   getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
                                  unsigned SrcOpIdx2,
                                  const X86InstrFMA3Group &FMA3Group) const;
 
   // Branch analysis.
-  bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
   bool isUnconditionalTailCall(const MachineInstr &MI) const override;
   bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
                                   const MachineInstr &TailCall) const override;
   void replaceBranchWithTailCall(MachineBasicBlock &MBB,
                                  SmallVectorImpl<MachineOperand> &Cond,
                                  const MachineInstr &TailCall) const override;
 
   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,

llvm/lib/Target/X86/X86InstrInfo.cpp

case 0x01: case 0x02:
     // Need to toggle bits 3:0. Bit 4 stays the same.
     Imm ^= 0xf;
     break;
   }
 
   return Imm;
 }
 
-bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
-  if (!MI.isTerminator()) return false;
-
-  // Conditional branch is a special case.
-  if (MI.isBranch() && !MI.isBarrier())
-    return true;
-  if (!MI.isPredicable())
-    return true;
-  return !isPredicated(MI);
-}
-
 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   case X86::TCRETURNdi:
   case X86::TCRETURNri:
   case X86::TCRETURNmi:
   case X86::TCRETURNdi64:
   case X86::TCRETURNri64:
   case X86::TCRETURNmi64: