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Differential D62740

[MIR-Canon] Don't do vreg skip for independent instructions if there are none.
ClosedPublic

Authored by plotfi on May 31 2019, 9:22 AM.

Details

Reviewers
compnerd
bogner
Commits
rG3ea6b24f4147: [MIR-Canon] Don't do vreg skip for independent instructions if there are none.
rL362247: [MIR-Canon] Don't do vreg skip for independent instructions if there are none.
Summary

We don't want to create vregs if there is nothing to use them for. That causes verifier errors.

Diff Detail

Repository
rL LLVM

Event Timeline

plotfi created this revision.May 31 2019, 9:22 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 31 2019, 9:22 AM
Herald added subscribers: llvm-commits, hiraditya, nhaehnle, jvesely. · View Herald Transcript
compnerd accepted this revision.May 31 2019, 10:10 AM
This revision is now accepted and ready to land.May 31 2019, 10:10 AM
Closed by commit rL362247: [MIR-Canon] Don't do vreg skip for independent instructions if there are none. (authored by zer0). · Explain WhyMay 31 2019, 10:32 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
3 lines
test/
CodeGen/
MIR/
AMDGPU/
1 line

Diff 202458

llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp

Show First 20 Lines • Show All 737 Lines • ▼ Show 20 Linesstatic bool runOnBasicBlock(MachineBasicBlock *MBB,
auto VRegRenameMap = GetVRegRenameMap(VRegs, renamedInOtherBB, MRI, NVC); auto VRegRenameMap = GetVRegRenameMap(VRegs, renamedInOtherBB, MRI, NVC);
Changed |= doVRegRenaming(renamedInOtherBB, VRegRenameMap, MRI); Changed |= doVRegRenaming(renamedInOtherBB, VRegRenameMap, MRI);
// Here we renumber the def vregs for the idempotent instructions from the top // Here we renumber the def vregs for the idempotent instructions from the top
// of the MachineBasicBlock so that they are named in the order that we sorted // of the MachineBasicBlock so that they are named in the order that we sorted
// them alphabetically. Eventually we wont need SkipVRegs because we will use // them alphabetically. Eventually we wont need SkipVRegs because we will use
// named vregs instead. // named vregs instead.
if (IdempotentInstCount)
NVC.SkipVRegs(); NVC.SkipVRegs();
auto MII = MBB->begin(); auto MII = MBB->begin();
for (unsigned i = 0; i < IdempotentInstCount && MII != MBB->end(); ++i) { for (unsigned i = 0; i < IdempotentInstCount && MII != MBB->end(); ++i) {
MachineInstr &MI = *MII++; MachineInstr &MI = *MII++;
Changed = true; Changed = true;
unsigned vRegToRename = MI.getOperand(0).getReg(); unsigned vRegToRename = MI.getOperand(0).getReg();
auto Rename = NVC.createVirtualRegister(vRegToRename); auto Rename = NVC.createVirtualRegister(vRegToRename);
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir

# RUN: llc -march=amdgcn -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -run-pass mir-canonicalizer -verify-machineinstrs -o - %s
# Previously getReservedRegs was called before parsing # Previously getReservedRegs was called before parsing
# machineFunctionInfo, but the AMDGPU implementation depends on # machineFunctionInfo, but the AMDGPU implementation depends on
# setting register fields to reserve there. $sgpr50 would then not be # setting register fields to reserve there. $sgpr50 would then not be
# reserved, resulting in a verifier error from an undefined register. # reserved, resulting in a verifier error from an undefined register.
--- ---
# CHECK: machineFunctionInfo: # CHECK: machineFunctionInfo:
Show All 20 Lines