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Differential D62734

[AArch64] Check for simple type in FPToUInt
ClosedPublic

Authored by samparker on May 31 2019, 7:12 AM.

Details

Reviewers
silviu.baranga
t.p.northover
sbaranga
Commits
rGa0bd6f8a1ae7: [AArch64] Check for simple type in FPToUInt
rL362365: [AArch64] Check for simple type in FPToUInt
Summary

DAGCombiner was hitting a SimpleType assertion when trying to combine a v3f32 before type legalization.




bugzilla: https://bugs.llvm.org/show_bug.cgi?id=41916
Diff Detail
Event Timeline
samparker created this revision.May 31 2019, 7:12 AM
Herald added subscribers: kristof.beyls, javed.absar.  ·  View Herald TranscriptMay 31 2019, 7:12 AM
tpr added a subscriber: tpr.May 31 2019, 7:21 AM
sbaranga accepted this revision.May 31 2019, 8:17 AM
sbaranga added a subscriber: sbaranga.
Seems reasonable to me. LGTM
This revision is now accepted and ready to land.May 31 2019, 8:17 AM
Closed by commit rL362365: [AArch64] Check for simple type in FPToUInt (authored by sam_parker).  ·  Explain WhyJun 3 2019, 1:47 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project.  ·  View Herald TranscriptJun 3 2019, 1:47 AM
Revision Contents
PathSize
lib/
Target/
AArch64/
3 lines
test/
CodeGen/
AArch64/
17 lines
Diff 202430
lib/Target/AArch64/AArch64ISelLowering.cpp
Show First 20 Lines • Show All 492 Lines • ▼ Show 20 Lines
/// Fold a floating-point multiply by power of two into floating-point to
/// Fold a floating-point multiply by power of two into floating-point to

/// fixed-point conversion.
/// fixed-point conversion.

static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG,
static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG,

                                     TargetLowering::DAGCombinerInfo &DCI,
                                     TargetLowering::DAGCombinerInfo &DCI,

                                     const AArch64Subtarget *Subtarget) {
                                     const AArch64Subtarget *Subtarget) {

  if (!Subtarget->hasNEON())
  if (!Subtarget->hasNEON())

    return SDValue();
    return SDValue();




  if (!N->getValueType(0).isSimple())

    return SDValue();



  SDValue Op = N->getOperand(0);
  SDValue Op = N->getOperand(0);

  if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
  if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||

      Op.getOpcode() != ISD::FMUL)
      Op.getOpcode() != ISD::FMUL)

    return SDValue();
    return SDValue();




  SDValue ConstVec = Op->getOperand(1);
  SDValue ConstVec = Op->getOperand(1);

  if (!isa<BuildVectorSDNode>(ConstVec))
  if (!isa<BuildVectorSDNode>(ConstVec))

    return SDValue();
    return SDValue();

▲ Show 20 Lines • Show All 492 Lines • Show Last 20 Lines
test/CodeGen/AArch64/v3f-to-int.ll
  • This file was added.
; RUN: llc -mtriple=aarch64--linux-eabi %s -o - | FileCheck %s



; CHECK-LABEL: convert_v3f32

; CHECK: strb

; CHECK: strh

define void @convert_v3f32() {

entry:

  br label %bb



bb:

  %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>

  %1 = fmul reassoc nnan ninf nsz contract afn <3 x float> %0, <float 2.550000e+02, float 2.550000e+02, float 2.550000e+02>

  %2 = fptoui <3 x float> %1 to <3 x i8>

  %3 = bitcast i8* undef to <3 x i8>*

  store <3 x i8> %2, <3 x i8>* %3, align 1

  ret void

}