See bug 39292: https://bugs.llvm.org/show_bug.cgi?id=39292
I may be missing something, but these registers are already handled by AMDGPU::isSGPR() because they are defined in SReg_32RegClass.
The same is true for AMDGPUAsmParser::usesConstantBus.
I can add a check to SIInstrInfo::usesConstantBus() but is not it used by codegen only?
As codegen cannot utilize these registers right now, I do not see any use case and will be unable to add any relevant tests.
Right, isSGPR() uses SReg_32, so this is fine, and AsmParser is also fine. But SIInstrInfo::usesConstantBus() checks for SGPR_32 and SGPR_64, thus missing it. I am not sure if it is possible to write a test, but I would guess an inline asm could be written to violate constant bus limit. I would at least list them there to have no issues if codegen will start using these.
|3890–3895 ↗||(On Diff #202416)|
No, this was previously checked by this code:
if (isInlineValue(RegNo)) return !isCI() && !isSI() && !isVI();
As isInlineValue has changed I had to correct the check as well
|2834–2849 ↗||(On Diff #202416)|
I'll correct this, thanks!
|2832 ↗||(On Diff #202447)|
This statement asserts that only M0 and VCC use constant bus when implicit so all other registers are free (including exec). What am I missing here?