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I'd be open to opinions on if this optimization should be throttled for NaNs too. My understanding is that IEEE-754 does not specify the sign of NaN results for FSub, so it doesn't matter if an FNeg is performed on the result or not.
That said, in practice, whether this combine is performed or not could change the sign of a NaN....
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This matches the existing fold with 2 fsubs, and I agree with the comment in the description regarding IEEE-754 - fsub doesn't need to preserve the sign bit of a NaN. LGTM.