[ARM64, COFF] Add CodeView register mapping

[TomTan]

Summary

CodeView has its own register map which is defined in cvconst.h. Missing this mapping before saving register to CodeView causes debugger to show incorrect value for all register based variables, like variables in register and local variables addressed by register (stack pointer + offset).

This change added mapping between LLVM register and CodeView register so the correct register number will be stored to CodeView/PDB, but it doesn't fix the translation from CodeView register number to register name, because CodeView register numbers overlap between architectures. So the tools like llvm-pdbutil need extra fix in order to dump ARM64 registers correctly from PDB.

[efriedma]

include/llvm/DebugInfo/CodeView/CodeViewRegisters.def

354

It's worth taking a moment to figure out how this will generalize beyond the current patch.

Probably the right approach is to provide CV_REGISTER_ARM64, CV_REGISTER_X86, and CV_REGISTER_ALL as possibilities, where CV_REGISTER_X86 only provides the x86 entries, CV_REGISTER_ARM64 only provides the ARM64 entries, and CV_REGISTER_ALL provides the entries for all targets. That would make it clear in each place that includes CodeViewRegisters.def which registers are actually being used.

[mstorsjo]

include/llvm/DebugInfo/CodeView/CodeViewRegisters.def

430

Typo, statue/status

[TomTan]

Added CV_REGISTERS_{ARCH} macro for each architecture, and fixed typo.

[efriedma]

The code looks fine now. I'm okay with putting off fixes for dumping code that incorrectly assumes x86.

test/DebugInfo/COFF/register-variables-arm64.ll

88

Do you really need two functions here, given what you're testing?

Please try to clean up the testcase IR as much as you can. I know you probably don't want to manually edit debug metadata, since it's easy to accidentally write incorrect debug info that way, but please do what you can for the other irrelevant bits, like attributes and the llvm.ident metadata.

[TomTan]

Did a little cleanup as per Eli's comment (removed attributes and llvm.ident. Tried some others but got llc failure, so I'd like to be conservation on this. Also the test follows register-variables.ll in the same folder which keeps all the metadata.

[rnk]

In D62608#1521945, @efriedma wrote:

The code looks fine now. I'm okay with putting off fixes for dumping code that incorrectly assumes x86.

The dumping tools are the foundation of our testing strategy, so I think we should take the time to fix them early on. It should be a matter of changing getRegisterNames to accept a CPU type, switch, and return the appropriate (x86 or arm) enum table, maybe just returning x86 by default to preserve existing behavior. Both symbol dumpers already store the compilation CPU type from the S_COMPILE3 record, so this shouldn't be too complicated.

test/DebugInfo/COFF/register-variables-arm64.ll

27

So, you have to wild card the register here because the dumper assumes x86 registers. I think we should take the time to fix that now before we accumulate more tests.

[TomTan]

In D62608#1522078, @rnk wrote:

In D62608#1521945, @efriedma wrote:

The code looks fine now. I'm okay with putting off fixes for dumping code that incorrectly assumes x86.

The dumping tools are the foundation of our testing strategy, so I think we should take the time to fix them early on. It should be a matter of changing getRegisterNames to accept a CPU type, switch, and return the appropriate (x86 or arm) enum table, maybe just returning x86 by default to preserve existing behavior. Both symbol dumpers already store the compilation CPU type from the S_COMPILE3 record, so this shouldn't be too complicated.

Yes, I was thinking on passing CPU arch (as you mentioned from S_COMPILE3) to get correct register name. I am trying to find a way in each include site of "CodeViewRegisters.def" to get that information. At the mean time, the current issue affects debugging experience on Chromium and derived projects. As register name query only affects LLVM pdb tools, could this change be merged at first while I am working on fixing LLVM pdb tool? Also ARM64 support for LLVM pdb tool is new, so it would not block anything or test.

[rnk]

In D62608#1522123, @TomTan wrote:

Yes, I was thinking on passing CPU arch (as you mentioned from S_COMPILE3) to get correct register name. I am trying to find a way in each include site of "CodeViewRegisters.def" to get that information. At the mean time, the current issue affects debugging experience on Chromium and derived projects. As register name query only affects LLVM pdb tools, could this change be merged at first while I am working on fixing LLVM pdb tool? Also ARM64 support for LLVM pdb tool is new, so it would not block anything or test.

The way I interpret LLVM's project policy is that new features and bug fixes should have tests, and with our testing infrastructure, that usually means starting with a dumper. Right now I'm working on missing inline line tables, and before I send the functionality for review and write tests for it, I've gone and improved the dumper in rL362037.

A while back (rL312042) I rebased an improvement to llvm-dwarfdump to do this kind of location pretty printing stuff, and when I did, I uncovered several of these kinds of tests where the dumper printed the hex bytes of a dwarf expression, and the test contained comments explaining that these bytes were correct. However, the comments were stale and the bytes were actually wrong, at some point someone updated them without interpreting the bytes and checking the comments. I'd like to avoid similar situations in the future. :)

[TomTan]

It makes sense to fix the dumper for test infrastructure. This update fixes register names in the dumper. I also changed the wildcard for register name to ARM64_SP in the new test, because register name is shown correct by the dumper based on CPUType in the PDB.

There is still a TODO item for printing to yaml. I haven't found a easy way to pass in CPUType for register name query. I'd like to get your advise on this and fix it later.

[rnk]

lgtm, thanks!

lib/DebugInfo/PDB/Native/NativeSession.cpp

86 ↗

(On Diff #202466)

Did you mean to add const here? It doesn't seem necessary, please revert it if so.

[TomTan]

lib/DebugInfo/PDB/Native/NativeSession.cpp

86 ↗

(On Diff #202466)

Thanks for the catch. Yes, this is unnecessary. I tried query CPUType from getGlobalScope(), but found a class variable CompilationCPU for that. I'll revert the all added const for getLobalScope().

[TomTan]

Remove unnecessary const and clean up.

[mgorny]

This API change broke builds of LLDB:
http://green.lab.llvm.org/green/job/lldb-cmake/27531/
http://lab.llvm.org:8011/builders/netbsd-amd64/builds/20296

[TomTan]

In D62608#1526080, @mgorny wrote:

This API change broke builds of LLDB:
http://green.lab.llvm.org/green/job/lldb-cmake/27531/
http://lab.llvm.org:8011/builders/netbsd-amd64/builds/20296

Uploaded a fix as D62772.

[mgorny]

Could we, please, revert this until the fix for LLDB is ready and approved?

[TomTan]

In D62608#1526620, @mgorny wrote:

Could we, please, revert this until the fix for LLDB is ready and approved?

The fix for LLDB was merged yesterday.

include/llvm/DebugInfo/CodeView/CodeView.h

enum class FrameCookieKind : uint8_t {
   Copy,
   XorStackPointer,
   XorFramePointer,
   XorR13,
 };
 
 // Corresponds to CV_HREG_e enum.
 enum class RegisterId : uint16_t {
+#define CV_REGISTER_ARM64
 #define CV_REGISTER(name, value) name = value,
 #include "CodeViewRegisters.def"
 #undef CV_REGISTER
+#undef CV_REGISTER_ARM64
 };
 
 /// Two-bit value indicating which register is the designated frame pointer
 /// register. Appears in the S_FRAMEPROC record flags.
 enum class EncodedFramePtrReg : uint8_t {
   None = 0,
   StackPtr = 1,
   FramePtr = 2,

include/llvm/DebugInfo/CodeView/CodeViewRegisters.def

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef CV_REGISTER
 #define CV_REGISTER(name, value)
 #endif
 
 // This currently only contains the "register subset shared by all processor
-// types" (ERR etc.) and the x86 registers.
+// types" (ERR etc.) and the x86/arm64 registers.
 
 // Some system headers define macros that conflict with our enums. Every
 // compiler supported by LLVM has the push_macro and pop_macro pragmas, so use
 // them to avoid the conflict.
 #pragma push_macro("CR0")
 #pragma push_macro("CR1")
 #pragma push_macro("CR2")
 #pragma push_macro("CR3")

 CV_REGISTER(AMD64_K1, 759)
 CV_REGISTER(AMD64_K2, 760)
 CV_REGISTER(AMD64_K3, 761)
 CV_REGISTER(AMD64_K4, 762)
 CV_REGISTER(AMD64_K5, 763)
 CV_REGISTER(AMD64_K6, 764)
 CV_REGISTER(AMD64_K7, 765)
 
+#ifdef CV_REGISTER_ARM64
+
+// ARM64 registers
+
+CV_REGISTER(ARM64_NOREG, 0)
+
+// General purpose 32-bit integer registers
+
+CV_REGISTER(ARM64_W0, 10)
+CV_REGISTER(ARM64_W1, 11)
+CV_REGISTER(ARM64_W2, 12)
+CV_REGISTER(ARM64_W3, 13)
+CV_REGISTER(ARM64_W4, 14)
+CV_REGISTER(ARM64_W5, 15)
+CV_REGISTER(ARM64_W6, 16)
+CV_REGISTER(ARM64_W7, 17)
+CV_REGISTER(ARM64_W8, 18)
+CV_REGISTER(ARM64_W9, 19)
+CV_REGISTER(ARM64_W10, 20)
+CV_REGISTER(ARM64_W11, 21)
+CV_REGISTER(ARM64_W12, 22)
+CV_REGISTER(ARM64_W13, 23)
+CV_REGISTER(ARM64_W14, 24)
+CV_REGISTER(ARM64_W15, 25)
+CV_REGISTER(ARM64_W16, 26)
+CV_REGISTER(ARM64_W17, 27)
+CV_REGISTER(ARM64_W18, 28)
+CV_REGISTER(ARM64_W19, 29)
+CV_REGISTER(ARM64_W20, 30)
+CV_REGISTER(ARM64_W21, 31)
+CV_REGISTER(ARM64_W22, 32)
+CV_REGISTER(ARM64_W23, 33)
+CV_REGISTER(ARM64_W24, 34)
+CV_REGISTER(ARM64_W25, 35)
+CV_REGISTER(ARM64_W26, 36)
+CV_REGISTER(ARM64_W27, 37)
+CV_REGISTER(ARM64_W28, 38)
+CV_REGISTER(ARM64_W29, 39)
+CV_REGISTER(ARM64_W30, 40)
+CV_REGISTER(ARM64_W31, 41)
+
+// General purpose 64-bit integer registers
+
+CV_REGISTER(ARM64_X0, 50)
+CV_REGISTER(ARM64_X1, 51)
+CV_REGISTER(ARM64_X2, 52)
+CV_REGISTER(ARM64_X3, 53)
+CV_REGISTER(ARM64_X4, 54)
+CV_REGISTER(ARM64_X5, 55)
+CV_REGISTER(ARM64_X6, 56)
+CV_REGISTER(ARM64_X7, 57)
+CV_REGISTER(ARM64_X8, 58)
+CV_REGISTER(ARM64_X9, 59)
+CV_REGISTER(ARM64_X10, 60)
+CV_REGISTER(ARM64_X11, 61)
+CV_REGISTER(ARM64_X12, 62)
+CV_REGISTER(ARM64_X13, 63)
+CV_REGISTER(ARM64_X14, 64)
+CV_REGISTER(ARM64_X15, 65)
+CV_REGISTER(ARM64_X16, 66)
+CV_REGISTER(ARM64_X17, 67)
+CV_REGISTER(ARM64_X18, 68)
+CV_REGISTER(ARM64_X19, 69)
+CV_REGISTER(ARM64_X20, 70)
+CV_REGISTER(ARM64_X21, 71)
+CV_REGISTER(ARM64_X22, 72)
+CV_REGISTER(ARM64_X23, 73)
+CV_REGISTER(ARM64_X24, 74)
+CV_REGISTER(ARM64_X25, 75)
+CV_REGISTER(ARM64_X26, 76)
+CV_REGISTER(ARM64_X27, 77)
+CV_REGISTER(ARM64_X28, 78)
+CV_REGISTER(ARM64_X29, 79)
+CV_REGISTER(ARM64_X30, 80)
+CV_REGISTER(ARM64_X31, 81)
+
+// statue register
+
+CV_REGISTER(ARM64_NZCV, 90)
+
+// 32-bit floating point registers
+
+CV_REGISTER(ARM64_S0, 100)
+CV_REGISTER(ARM64_S1, 101)
+CV_REGISTER(ARM64_S2, 102)
+CV_REGISTER(ARM64_S3, 103)
+CV_REGISTER(ARM64_S4, 104)
+CV_REGISTER(ARM64_S5, 105)
+CV_REGISTER(ARM64_S6, 106)
+CV_REGISTER(ARM64_S7, 107)
+CV_REGISTER(ARM64_S8, 108)
+CV_REGISTER(ARM64_S9, 109)
+CV_REGISTER(ARM64_S10, 110)
+CV_REGISTER(ARM64_S11, 111)
+CV_REGISTER(ARM64_S12, 112)
+CV_REGISTER(ARM64_S13, 113)
+CV_REGISTER(ARM64_S14, 114)
+CV_REGISTER(ARM64_S15, 115)
+CV_REGISTER(ARM64_S16, 116)
+CV_REGISTER(ARM64_S17, 117)
+CV_REGISTER(ARM64_S18, 118)
+CV_REGISTER(ARM64_S19, 119)
+CV_REGISTER(ARM64_S20, 120)
+CV_REGISTER(ARM64_S21, 121)
+CV_REGISTER(ARM64_S22, 122)
+CV_REGISTER(ARM64_S23, 123)
+CV_REGISTER(ARM64_S24, 124)
+CV_REGISTER(ARM64_S25, 125)
+CV_REGISTER(ARM64_S26, 126)
+CV_REGISTER(ARM64_S27, 127)
+CV_REGISTER(ARM64_S28, 128)
+CV_REGISTER(ARM64_S29, 129)
+CV_REGISTER(ARM64_S30, 130)
+CV_REGISTER(ARM64_S31, 131)
+
+// 64-bit floating point registers
+
+CV_REGISTER(ARM64_D0, 140)
+CV_REGISTER(ARM64_D1, 141)
+CV_REGISTER(ARM64_D2, 142)
+CV_REGISTER(ARM64_D3, 143)
+CV_REGISTER(ARM64_D4, 144)
+CV_REGISTER(ARM64_D5, 145)
+CV_REGISTER(ARM64_D6, 146)
+CV_REGISTER(ARM64_D7, 147)
+CV_REGISTER(ARM64_D8, 148)
+CV_REGISTER(ARM64_D9, 149)
+CV_REGISTER(ARM64_D10, 150)
+CV_REGISTER(ARM64_D11, 151)
+CV_REGISTER(ARM64_D12, 152)
+CV_REGISTER(ARM64_D13, 153)
+CV_REGISTER(ARM64_D14, 154)
+CV_REGISTER(ARM64_D15, 155)
+CV_REGISTER(ARM64_D16, 156)
+CV_REGISTER(ARM64_D17, 157)
+CV_REGISTER(ARM64_D18, 158)
+CV_REGISTER(ARM64_D19, 159)
+CV_REGISTER(ARM64_D20, 160)
+CV_REGISTER(ARM64_D21, 161)
+CV_REGISTER(ARM64_D22, 162)
+CV_REGISTER(ARM64_D23, 163)
+CV_REGISTER(ARM64_D24, 164)
+CV_REGISTER(ARM64_D25, 165)
+CV_REGISTER(ARM64_D26, 166)
+CV_REGISTER(ARM64_D27, 167)
+CV_REGISTER(ARM64_D28, 168)
+CV_REGISTER(ARM64_D29, 169)
+CV_REGISTER(ARM64_D30, 170)
+CV_REGISTER(ARM64_D31, 171)
+
+// 128-bit SIMD registers
+
+CV_REGISTER(ARM64_Q0, 180)
+CV_REGISTER(ARM64_Q1, 181)
+CV_REGISTER(ARM64_Q2, 182)
+CV_REGISTER(ARM64_Q3, 183)
+CV_REGISTER(ARM64_Q4, 184)
+CV_REGISTER(ARM64_Q5, 185)
+CV_REGISTER(ARM64_Q6, 186)
+CV_REGISTER(ARM64_Q7, 187)
+CV_REGISTER(ARM64_Q8, 188)
+CV_REGISTER(ARM64_Q9, 189)
+CV_REGISTER(ARM64_Q10, 190)
+CV_REGISTER(ARM64_Q11, 191)
+CV_REGISTER(ARM64_Q12, 192)
+CV_REGISTER(ARM64_Q13, 193)
+CV_REGISTER(ARM64_Q14, 194)
+CV_REGISTER(ARM64_Q15, 195)
+CV_REGISTER(ARM64_Q16, 196)
+CV_REGISTER(ARM64_Q17, 197)
+CV_REGISTER(ARM64_Q18, 198)
+CV_REGISTER(ARM64_Q19, 199)
+CV_REGISTER(ARM64_Q20, 200)
+CV_REGISTER(ARM64_Q21, 201)
+CV_REGISTER(ARM64_Q22, 202)
+CV_REGISTER(ARM64_Q23, 203)
+CV_REGISTER(ARM64_Q24, 204)
+CV_REGISTER(ARM64_Q25, 205)
+CV_REGISTER(ARM64_Q26, 206)
+CV_REGISTER(ARM64_Q27, 207)
+CV_REGISTER(ARM64_Q28, 208)
+CV_REGISTER(ARM64_Q29, 209)
+CV_REGISTER(ARM64_Q30, 210)
+CV_REGISTER(ARM64_Q31, 211)
+
+// Floating point status register
+
+CV_REGISTER(ARM64_FPSR, 220)
+
+#endif // CV_REGISTER_ARM64
+
 #pragma pop_macro("CR0")
 #pragma pop_macro("CR1")
 #pragma pop_macro("CR2")
 #pragma pop_macro("CR3")
 #pragma pop_macro("CR4")

lib/DebugInfo/PDB/PDBExtras.cpp

 }
 
 raw_ostream &llvm::pdb::operator<<(raw_ostream &OS,
                                    const codeview::RegisterId &Reg) {
   switch (Reg) {
 #define CV_REGISTER(name, val) case codeview::RegisterId::name: OS << #name; return OS;
 #include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
 #undef CV_REGISTER
+
+    default:
+      break;
   }
   OS << static_cast<int>(Reg);
   return OS;
 }
 
 raw_ostream &llvm::pdb::operator<<(raw_ostream &OS, const PDB_LocType &Loc) {
   switch (Loc) {
     CASE_OUTPUT_ENUM_CLASS_STR(PDB_LocType, Static, "static", OS)

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

 
 #include "AArch64MCTargetDesc.h"
 #include "AArch64ELFStreamer.h"
 #include "AArch64MCAsmInfo.h"
 #include "AArch64WinCOFFStreamer.h"
 #include "MCTargetDesc/AArch64AddressingModes.h"
 #include "MCTargetDesc/AArch64InstPrinter.h"
 #include "TargetInfo/AArch64TargetInfo.h"
+#include "llvm/DebugInfo/CodeView/CodeView.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"

 createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   if (CPU.empty())
     CPU = "generic";
 
   return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
-  for (unsigned Reg = AArch64::NoRegister + 1;
-       Reg < AArch64::NUM_TARGET_REGS; ++Reg) {
-    unsigned CV = MRI->getEncodingValue(Reg);
-    MRI->mapLLVMRegToCVReg(Reg, CV);
-  }
+  // Mapping from CodeView to MC register id.
+  static const struct {
+    codeview::RegisterId CVReg;
+    MCPhysReg Reg;
+  } RegMap[] = {
+    {codeview::RegisterId::ARM64_W0, AArch64::W0},
+    {codeview::RegisterId::ARM64_W1, AArch64::W1},
+    {codeview::RegisterId::ARM64_W2, AArch64::W2},
+    {codeview::RegisterId::ARM64_W3, AArch64::W3},
+    {codeview::RegisterId::ARM64_W4, AArch64::W4},
+    {codeview::RegisterId::ARM64_W5, AArch64::W5},
+    {codeview::RegisterId::ARM64_W6, AArch64::W6},
+    {codeview::RegisterId::ARM64_W7, AArch64::W7},
+    {codeview::RegisterId::ARM64_W8, AArch64::W8},
+    {codeview::RegisterId::ARM64_W9, AArch64::W9},
+    {codeview::RegisterId::ARM64_W10, AArch64::W10},
+    {codeview::RegisterId::ARM64_W11, AArch64::W11},
+    {codeview::RegisterId::ARM64_W12, AArch64::W12},
+    {codeview::RegisterId::ARM64_W13, AArch64::W13},
+    {codeview::RegisterId::ARM64_W14, AArch64::W14},
+    {codeview::RegisterId::ARM64_W15, AArch64::W15},
+    {codeview::RegisterId::ARM64_W16, AArch64::W16},
+    {codeview::RegisterId::ARM64_W17, AArch64::W17},
+    {codeview::RegisterId::ARM64_W18, AArch64::W18},
+    {codeview::RegisterId::ARM64_W19, AArch64::W19},
+    {codeview::RegisterId::ARM64_W20, AArch64::W20},
+    {codeview::RegisterId::ARM64_W21, AArch64::W21},
+    {codeview::RegisterId::ARM64_W22, AArch64::W22},
+    {codeview::RegisterId::ARM64_W23, AArch64::W23},
+    {codeview::RegisterId::ARM64_W24, AArch64::W24},
+    {codeview::RegisterId::ARM64_W25, AArch64::W25},
+    {codeview::RegisterId::ARM64_W26, AArch64::W26},
+    {codeview::RegisterId::ARM64_W27, AArch64::W27},
+    {codeview::RegisterId::ARM64_W28, AArch64::W28},
+    {codeview::RegisterId::ARM64_W29, AArch64::W29},
+    {codeview::RegisterId::ARM64_W30, AArch64::W30},
+    {codeview::RegisterId::ARM64_W31, AArch64::WSP},
+    {codeview::RegisterId::ARM64_X0, AArch64::X0},
+    {codeview::RegisterId::ARM64_X1, AArch64::X1},
+    {codeview::RegisterId::ARM64_X2, AArch64::X2},
+    {codeview::RegisterId::ARM64_X3, AArch64::X3},
+    {codeview::RegisterId::ARM64_X4, AArch64::X4},
+    {codeview::RegisterId::ARM64_X5, AArch64::X5},
+    {codeview::RegisterId::ARM64_X6, AArch64::X6},
+    {codeview::RegisterId::ARM64_X7, AArch64::X7},
+    {codeview::RegisterId::ARM64_X8, AArch64::X8},
+    {codeview::RegisterId::ARM64_X9, AArch64::X9},
+    {codeview::RegisterId::ARM64_X10, AArch64::X10},
+    {codeview::RegisterId::ARM64_X11, AArch64::X11},
+    {codeview::RegisterId::ARM64_X12, AArch64::X12},
+    {codeview::RegisterId::ARM64_X13, AArch64::X13},
+    {codeview::RegisterId::ARM64_X14, AArch64::X14},
+    {codeview::RegisterId::ARM64_X15, AArch64::X15},
+    {codeview::RegisterId::ARM64_X16, AArch64::X16},
+    {codeview::RegisterId::ARM64_X17, AArch64::X17},
+    {codeview::RegisterId::ARM64_X18, AArch64::X18},
+    {codeview::RegisterId::ARM64_X19, AArch64::X19},
+    {codeview::RegisterId::ARM64_X20, AArch64::X20},
+    {codeview::RegisterId::ARM64_X21, AArch64::X21},
+    {codeview::RegisterId::ARM64_X22, AArch64::X22},
+    {codeview::RegisterId::ARM64_X23, AArch64::X23},
+    {codeview::RegisterId::ARM64_X24, AArch64::X24},
+    {codeview::RegisterId::ARM64_X25, AArch64::X25},
+    {codeview::RegisterId::ARM64_X26, AArch64::X26},
+    {codeview::RegisterId::ARM64_X27, AArch64::X27},
+    {codeview::RegisterId::ARM64_X28, AArch64::X28},
+    {codeview::RegisterId::ARM64_X29, AArch64::FP},
+    {codeview::RegisterId::ARM64_X30, AArch64::LR},
+    {codeview::RegisterId::ARM64_X31, AArch64::SP},
+    {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV},
+    {codeview::RegisterId::ARM64_S0, AArch64::S0},
+    {codeview::RegisterId::ARM64_S1, AArch64::S1},
+    {codeview::RegisterId::ARM64_S2, AArch64::S2},
+    {codeview::RegisterId::ARM64_S3, AArch64::S3},
+    {codeview::RegisterId::ARM64_S4, AArch64::S4},
+    {codeview::RegisterId::ARM64_S5, AArch64::S5},
+    {codeview::RegisterId::ARM64_S6, AArch64::S6},
+    {codeview::RegisterId::ARM64_S7, AArch64::S7},
+    {codeview::RegisterId::ARM64_S8, AArch64::S8},
+    {codeview::RegisterId::ARM64_S9, AArch64::S9},
+    {codeview::RegisterId::ARM64_S10, AArch64::S10},
+    {codeview::RegisterId::ARM64_S11, AArch64::S11},
+    {codeview::RegisterId::ARM64_S12, AArch64::S12},
+    {codeview::RegisterId::ARM64_S13, AArch64::S13},
+    {codeview::RegisterId::ARM64_S14, AArch64::S14},
+    {codeview::RegisterId::ARM64_S15, AArch64::S15},
+    {codeview::RegisterId::ARM64_S16, AArch64::S16},
+    {codeview::RegisterId::ARM64_S17, AArch64::S17},
+    {codeview::RegisterId::ARM64_S18, AArch64::S18},
+    {codeview::RegisterId::ARM64_S19, AArch64::S19},
+    {codeview::RegisterId::ARM64_S20, AArch64::S20},
+    {codeview::RegisterId::ARM64_S21, AArch64::S21},
+    {codeview::RegisterId::ARM64_S22, AArch64::S22},
+    {codeview::RegisterId::ARM64_S23, AArch64::S23},
+    {codeview::RegisterId::ARM64_S24, AArch64::S24},
+    {codeview::RegisterId::ARM64_S25, AArch64::S25},
+    {codeview::RegisterId::ARM64_S26, AArch64::S26},
+    {codeview::RegisterId::ARM64_S27, AArch64::S27},
+    {codeview::RegisterId::ARM64_S28, AArch64::S28},
+    {codeview::RegisterId::ARM64_S29, AArch64::S29},
+    {codeview::RegisterId::ARM64_S30, AArch64::S30},
+    {codeview::RegisterId::ARM64_S31, AArch64::S31},
+    {codeview::RegisterId::ARM64_D0, AArch64::D0},
+    {codeview::RegisterId::ARM64_D1, AArch64::D1},
+    {codeview::RegisterId::ARM64_D2, AArch64::D2},
+    {codeview::RegisterId::ARM64_D3, AArch64::D3},
+    {codeview::RegisterId::ARM64_D4, AArch64::D4},
+    {codeview::RegisterId::ARM64_D5, AArch64::D5},
+    {codeview::RegisterId::ARM64_D6, AArch64::D6},
+    {codeview::RegisterId::ARM64_D7, AArch64::D7},
+    {codeview::RegisterId::ARM64_D8, AArch64::D8},
+    {codeview::RegisterId::ARM64_D9, AArch64::D9},
+    {codeview::RegisterId::ARM64_D10, AArch64::D10},
+    {codeview::RegisterId::ARM64_D11, AArch64::D11},
+    {codeview::RegisterId::ARM64_D12, AArch64::D12},
+    {codeview::RegisterId::ARM64_D13, AArch64::D13},
+    {codeview::RegisterId::ARM64_D14, AArch64::D14},
+    {codeview::RegisterId::ARM64_D15, AArch64::D15},
+    {codeview::RegisterId::ARM64_D16, AArch64::D16},
+    {codeview::RegisterId::ARM64_D17, AArch64::D17},
+    {codeview::RegisterId::ARM64_D18, AArch64::D18},
+    {codeview::RegisterId::ARM64_D19, AArch64::D19},
+    {codeview::RegisterId::ARM64_D20, AArch64::D20},
+    {codeview::RegisterId::ARM64_D21, AArch64::D21},
+    {codeview::RegisterId::ARM64_D22, AArch64::D22},
+    {codeview::RegisterId::ARM64_D23, AArch64::D23},
+    {codeview::RegisterId::ARM64_D24, AArch64::D24},
+    {codeview::RegisterId::ARM64_D25, AArch64::D25},
+    {codeview::RegisterId::ARM64_D26, AArch64::D26},
+    {codeview::RegisterId::ARM64_D27, AArch64::D27},
+    {codeview::RegisterId::ARM64_D28, AArch64::D28},
+    {codeview::RegisterId::ARM64_D29, AArch64::D29},
+    {codeview::RegisterId::ARM64_D30, AArch64::D30},
+    {codeview::RegisterId::ARM64_D31, AArch64::D31},
+    {codeview::RegisterId::ARM64_Q0, AArch64::Q0},
+    {codeview::RegisterId::ARM64_Q1, AArch64::Q1},
+    {codeview::RegisterId::ARM64_Q2, AArch64::Q2},
+    {codeview::RegisterId::ARM64_Q3, AArch64::Q3},
+    {codeview::RegisterId::ARM64_Q4, AArch64::Q4},
+    {codeview::RegisterId::ARM64_Q5, AArch64::Q5},
+    {codeview::RegisterId::ARM64_Q6, AArch64::Q6},
+    {codeview::RegisterId::ARM64_Q7, AArch64::Q7},
+    {codeview::RegisterId::ARM64_Q8, AArch64::Q8},
+    {codeview::RegisterId::ARM64_Q9, AArch64::Q9},
+    {codeview::RegisterId::ARM64_Q10, AArch64::Q10},
+    {codeview::RegisterId::ARM64_Q11, AArch64::Q11},
+    {codeview::RegisterId::ARM64_Q12, AArch64::Q12},
+    {codeview::RegisterId::ARM64_Q13, AArch64::Q13},
+    {codeview::RegisterId::ARM64_Q14, AArch64::Q14},
+    {codeview::RegisterId::ARM64_Q15, AArch64::Q15},
+    {codeview::RegisterId::ARM64_Q16, AArch64::Q16},
+    {codeview::RegisterId::ARM64_Q17, AArch64::Q17},
+    {codeview::RegisterId::ARM64_Q18, AArch64::Q18},
+    {codeview::RegisterId::ARM64_Q19, AArch64::Q19},
+    {codeview::RegisterId::ARM64_Q20, AArch64::Q20},
+    {codeview::RegisterId::ARM64_Q21, AArch64::Q21},
+    {codeview::RegisterId::ARM64_Q22, AArch64::Q22},
+    {codeview::RegisterId::ARM64_Q23, AArch64::Q23},
+    {codeview::RegisterId::ARM64_Q24, AArch64::Q24},
+    {codeview::RegisterId::ARM64_Q25, AArch64::Q25},
+    {codeview::RegisterId::ARM64_Q26, AArch64::Q26},
+    {codeview::RegisterId::ARM64_Q27, AArch64::Q27},
+    {codeview::RegisterId::ARM64_Q28, AArch64::Q28},
+    {codeview::RegisterId::ARM64_Q29, AArch64::Q29},
+    {codeview::RegisterId::ARM64_Q30, AArch64::Q30},
+    {codeview::RegisterId::ARM64_Q31, AArch64::Q31},
+
+  };
+  for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
+    MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
 }
 
 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitAArch64MCRegisterInfo(X, AArch64::LR);
   AArch64_MC::initLLVMToCVRegMapping(X);
   return X;
 }

test/DebugInfo/COFF/register-variables-arm64.ll

+; RUN: llc < %s -filetype=obj | llvm-readobj --codeview - | FileCheck %s --check-prefix=OBJ
+
+; Generated from:
+; volatile int x;
+; int getint(void);
+; void putint(int);
+; static inline int inlineinc(int a) {
+;   int b = a + 1;
+;   ++x;
+;   return b;
+; }
+; void f(int p) {
+;   if (p) {
+;     int a = getint();
+;     int b = inlineinc(a);
+;     putint(b);
+;   } else {
+;     int c = getint();
+;     putint(c);
+;   }
+; }
+
+
+; OBJ:   DefRangeRegisterRelSym {
+; OBJ:     Kind: S_DEFRANGE_REGISTER_REL (0x1145)
+; OBJ:     BaseRegister: {{.*}} (0x51)
+; OBJ:     HasSpilledUDTMember: No
+; OBJ:     OffsetInParent: 0
+; OBJ:     BasePointerOffset: 28
+; OBJ:     LocalVariableAddrRange {
+; OBJ:       OffsetStart: .text+0xC
+; OBJ:       ISectStart: 0x0
+; OBJ:       Range: 0x44
+; OBJ:     }
+; OBJ:   }
+
+; ModuleID = 't.cpp'
+source_filename = "test/DebugInfo/COFF/register-variables-arm64.ll"
+target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-unknown-windows-msvc19.16.27023"
+
+@x = common dso_local global i32 0, align 4, !dbg !0
+
+; Function Attrs: noinline nounwind optnone uwtable
+define dso_local void @f(i32 %p) #0 !dbg !12 {
+entry:
+  %p.addr = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 %p, i32* %p.addr, align 4
+  call void @llvm.dbg.declare(metadata i32* %p.addr, metadata !15, metadata !DIExpression()), !dbg !16
+  %0 = load i32, i32* %p.addr, align 4, !dbg !17
+  %tobool = icmp ne i32 %0, 0, !dbg !17
+  br i1 %tobool, label %if.then, label %if.else, !dbg !17
+
+if.then:                                          ; preds = %entry
+  call void @llvm.dbg.declare(metadata i32* %a, metadata !18, metadata !DIExpression()), !dbg !21
+  %call = call i32 @getint(), !dbg !21
+  store i32 %call, i32* %a, align 4, !dbg !21
+  call void @llvm.dbg.declare(metadata i32* %b, metadata !22, metadata !DIExpression()), !dbg !23
+  %1 = load i32, i32* %a, align 4, !dbg !23
+  %call1 = call i32 @inlineinc(i32 %1), !dbg !23
+  store i32 %call1, i32* %b, align 4, !dbg !23
+  %2 = load i32, i32* %b, align 4, !dbg !24
+  call void @putint(i32 %2), !dbg !24
+  br label %if.end, !dbg !25
+
+if.else:                                          ; preds = %entry
+  call void @llvm.dbg.declare(metadata i32* %c, metadata !26, metadata !DIExpression()), !dbg !28
+  %call2 = call i32 @getint(), !dbg !28
+  store i32 %call2, i32* %c, align 4, !dbg !28
+  %3 = load i32, i32* %c, align 4, !dbg !29
+  call void @putint(i32 %3), !dbg !29
+  br label %if.end, !dbg !30
+
+if.end:                                           ; preds = %if.else, %if.then
+  ret void, !dbg !31
+}
+
+; Function Attrs: nounwind readnone speculatable
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+declare dso_local i32 @getint() #2
+
+; Function Attrs: noinline nounwind optnone uwtable
+define internal i32 @inlineinc(i32 %a) #0 !dbg !32 {
+entry:
+  %a.addr = alloca i32, align 4
+  %b = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !35, metadata !DIExpression()), !dbg !36
+  call void @llvm.dbg.declare(metadata i32* %b, metadata !37, metadata !DIExpression()), !dbg !38
+  %0 = load i32, i32* %a.addr, align 4, !dbg !38
+  %add = add nsw i32 %0, 1, !dbg !38
+  store i32 %add, i32* %b, align 4, !dbg !38
+  %1 = load volatile i32, i32* @x, align 4, !dbg !39
+  %inc = add nsw i32 %1, 1, !dbg !39
+  store volatile i32 %inc, i32* @x, align 4, !dbg !39
+  %2 = load i32, i32* %b, align 4, !dbg !40
+  ret i32 %2, !dbg !40
+}
+
+declare dso_local void @putint(i32) #2
+
+attributes #0 = { noinline nounwind optnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+neon" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone speculatable }
+attributes #2 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+neon" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.dbg.cu = !{!2}
+!llvm.module.flags = !{!8, !9, !10}
+!llvm.ident = !{!11}
+
+!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression())
+!1 = distinct !DIGlobalVariable(name: "x", scope: !2, file: !3, line: 1, type: !6, isLocal: false, isDefinition: true)
+!2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang version 9.0.0 (trunk 361867) (llvm/trunk 361866)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5, nameTableKind: None)
+!3 = !DIFile(filename: "t.c", directory: "S:\5CLLVM\5Csvn\5Csbr\5Cbin", checksumkind: CSK_MD5, checksum: "734c448e95a6204a439a847ed063e5ce")
+!4 = !{}
+!5 = !{!0}
+!6 = !DIDerivedType(tag: DW_TAG_volatile_type, baseType: !7)
+!7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+!8 = !{i32 2, !"CodeView", i32 1}
+!9 = !{i32 2, !"Debug Info Version", i32 3}
+!10 = !{i32 1, !"wchar_size", i32 2}
+!11 = !{!"clang version 9.0.0 (trunk 361867) (llvm/trunk 361866)"}
+!12 = distinct !DISubprogram(name: "f", scope: !3, file: !3, line: 9, type: !13, scopeLine: 9, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !2, retainedNodes: !4)
+!13 = !DISubroutineType(types: !14)
+!14 = !{null, !7}
+!15 = !DILocalVariable(name: "p", arg: 1, scope: !12, file: !3, line: 9, type: !7)
+!16 = !DILocation(line: 9, scope: !12)
+!17 = !DILocation(line: 10, scope: !12)
+!18 = !DILocalVariable(name: "a", scope: !19, file: !3, line: 11, type: !7)
+!19 = distinct !DILexicalBlock(scope: !20, file: !3, line: 10)
+!20 = distinct !DILexicalBlock(scope: !12, file: !3, line: 10)
+!21 = !DILocation(line: 11, scope: !19)
+!22 = !DILocalVariable(name: "b", scope: !19, file: !3, line: 12, type: !7)
+!23 = !DILocation(line: 12, scope: !19)
+!24 = !DILocation(line: 13, scope: !19)
+!25 = !DILocation(line: 14, scope: !19)
+!26 = !DILocalVariable(name: "c", scope: !27, file: !3, line: 15, type: !7)
+!27 = distinct !DILexicalBlock(scope: !20, file: !3, line: 14)
+!28 = !DILocation(line: 15, scope: !27)
+!29 = !DILocation(line: 16, scope: !27)
+!30 = !DILocation(line: 17, scope: !27)
+!31 = !DILocation(line: 18, scope: !12)
+!32 = distinct !DISubprogram(name: "inlineinc", scope: !3, file: !3, line: 4, type: !33, scopeLine: 4, flags: DIFlagPrototyped, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition, unit: !2, retainedNodes: !4)
+!33 = !DISubroutineType(types: !34)
+!34 = !{!7, !7}
+!35 = !DILocalVariable(name: "a", arg: 1, scope: !32, file: !3, line: 4, type: !7)
+!36 = !DILocation(line: 4, scope: !32)
+!37 = !DILocalVariable(name: "b", scope: !32, file: !3, line: 5, type: !7)
+!38 = !DILocation(line: 5, scope: !32)
+!39 = !DILocation(line: 6, scope: !32)
+!40 = !DILocation(line: 7, scope: !32)

tools/llvm-pdbutil/MinimalSymbolDumper.cpp

static std::string formatCookieKind(FrameCookieKind Kind) {
   return formatUnknownEnum(Kind);
 }
 
 static std::string formatRegisterId(RegisterId Id) {
   switch (Id) {
 #define CV_REGISTER(name, val) RETURN_CASE(RegisterId, name, #name)
 #include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
 #undef CV_REGISTER
+
+    default:
+        break;
   }
   return formatUnknownEnum(Id);
 }
 
 static std::string formatRegisterId(uint16_t Reg16) {
   return formatRegisterId(RegisterId(Reg16));
 }