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Differential D62285

[AArch64] Add nvcast patterns for v2f32 -> v1f64
ClosedPublic

Authored by sepavloff on May 22 2019, 10:27 PM.

Details

Reviewers
t.p.northover
Commits
rGed595e8627b3: [AArch64] Add nvcast patterns for v2f32 -> v1f64
rL361584: [AArch64] Add nvcast patterns for v2f32 -> v1f64
Summary

Constant stores of f32 values can create such NvCast nodes.

Diff Detail

Event Timeline

sepavloff created this revision.May 22 2019, 10:27 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 22 2019, 10:27 PM
Herald added subscribers: hiraditya, kristof.beyls, javed.absar. · View Herald Transcript
Harbormaster completed remote builds in B32353: Diff 200871.May 22 2019, 10:27 PM
t.p.northover accepted this revision.May 23 2019, 7:44 AM

LGTM.

This revision is now accepted and ready to land.May 23 2019, 7:44 AM
Closed by commit rL361584: [AArch64] Add nvcast patterns for v2f32 -> v1f64 (authored by sepavloff). · Explain WhyMay 23 2019, 6:17 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
1 line
test/
CodeGen/
AArch64/
12 lines

Diff 200871

llvm/lib/Target/AArch64/AArch64InstrInfo.td

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def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>; def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>; def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>; def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>; def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>; def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>; def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>; def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
def : Pat<(v1f64 (AArch64NvCast (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
// Natural vector casts (128 bit) // Natural vector casts (128 bit)
def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>; def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>; def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>; def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>; def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>; def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>; def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
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llvm/test/CodeGen/AArch64/arm64-nvcast.ll

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define internal void @nvcast_f32_v8i8() { define internal void @nvcast_f32_v8i8() {
; CHECK-LABEL: _nvcast_f32_v8i8 ; CHECK-LABEL: _nvcast_f32_v8i8
; CHECK: movi.8b v[[REG:[0-9]+]], #254 ; CHECK: movi.8b v[[REG:[0-9]+]], #254
; CHECK: str d[[REG]] ; CHECK: str d[[REG]]
entry: entry:
store <2 x float> <float 0xC7DFDFDFC0000000, float 0xC7DFDFDFC0000000>, <2 x float>* bitcast (%"st1"* @_gv to <2 x float>*), align 8 store <2 x float> <float 0xC7DFDFDFC0000000, float 0xC7DFDFDFC0000000>, <2 x float>* bitcast (%"st1"* @_gv to <2 x float>*), align 8
ret void ret void
} }
%struct.Vector3 = type { float, float, float }
define void @nvcast_v2f32_v1f64(%struct.Vector3*) {
; CHECK-LABEL: _nvcast_v2f32_v1f64
; CHECK: fmov.2s v[[REG:[0-9]+]], #1.00000000
; CHECK: str d[[REG]], [x0]
entry:
%a13 = bitcast %struct.Vector3* %0 to <1 x double>*
store <1 x double> <double 0x3F8000003F800000>, <1 x double>* %a13, align 8
ret void
}