Fix register coalescer failure to prune value

[rampitec]

Summary

Register coalescer fails for the test in the patch with the assertion in
JoinVals::ConflictResolution `DefMI != nullptr'. It attempts to join
live intervals for two adjacent instructions and erase the copy:

%2:vreg_256 = COPY %1
%3:vreg_256 = COPY killed %1

The LI needs to be adjusted to kill subrange for the erased instruction
and extend the subrange of the original def. That was done for the main
interval only but not for the subrange. As a result subrange had a VNI
pointing to the erased slot resulting in the above failure.

[arsenm]

test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir

12 ↗

(On Diff #200361)

Can you reduce this more? You shouldn't need all of these blocks

[rampitec]

test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir

12 ↗

(On Diff #200361)

I do not see how. This is bugpoint reduced on the IR level, and then bugpoint does not work with MIR yet. A manual reduce will be a nightmare.

[arsenm]

test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir

12 ↗

(On Diff #200361)

Yes, I've done it many times. It's not that bad. It's fairly easy to eliminate the blocks, and then slows down inside the blocks

[rampitec]

Reduced test.

[arsenm]

I managed to reduce the test a bit more: https://ghostbin.com/paste/72n9f

I think this is correct

[rampitec]

Use test further reduced by Matt.

[arsenm]

LGTM

llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
     LLVM_DEBUG(dbgs() << "\t\tExpecting instruction removal at " << Def
                       << '\n');
     for (LiveInterval::SubRange &S : LI.subranges()) {
       LiveQueryResult Q = S.Query(Def);
 
       // If a subrange starts at the copy then an undefined value has been
       // copied and we must remove that subrange value as well.
       VNInfo *ValueOut = Q.valueOutOrDead();
-      if (ValueOut != nullptr && Q.valueIn() == nullptr) {
+      if (ValueOut != nullptr && (Q.valueIn() == nullptr ||
+                                  (V.Identical && V.Resolution == CR_Erase &&
+                                   ValueOut->def == Def))) {
         LLVM_DEBUG(dbgs() << "\t\tPrune sublane " << PrintLaneMask(S.LaneMask)
                           << " at " << Def << "\n");
         SmallVector<SlotIndex,8> EndPoints;
         LIS->pruneValue(S, Def, &EndPoints);
         DidPrune = true;
         // Mark value number as unused.
         ValueOut->markUnused();
 
-        if (V.Identical && S.Query(OtherDef).valueOut()) {
+        if (V.Identical && S.Query(OtherDef).valueOutOrDead()) {
           // If V is identical to V.OtherVNI (and S was live at OtherDef),
           // then we can't simply prune V from S. V needs to be replaced
           // with V.OtherVNI.
           LIS->extendToIndices(S, EndPoints);
         }
         continue;
       }
       // If a subrange ends at the copy, then a value was copied but only

llvm/trunk/test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
+
+# Test used to crash with message:
+# JoinVals::ConflictResolution (anonymous namespace)::JoinVals::analyzeValue(unsigned int, (anonymous namespace)::JoinVals &): Assertion `DefMI != nullptr' failed
+
+---
+name:            test
+tracksRegLiveness: true
+body:             |
+  ; GCN-LABEL: name: test
+  ; GCN: bb.0:
+  ; GCN:   successors: %bb.2(0x80000000)
+  ; GCN:   undef %1.sub0:vreg_128 = IMPLICIT_DEF
+  ; GCN:   %1.sub1:vreg_128 = IMPLICIT_DEF
+  ; GCN:   S_BRANCH %bb.2
+  ; GCN: bb.1:
+  ; GCN:   successors: %bb.2(0x80000000)
+  ; GCN:   [[DEF:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
+  ; GCN: bb.2:
+  ; GCN:   [[DEF]].sub2:vreg_128 = COPY undef %3:sreg_32
+  ; GCN:   S_ENDPGM 0, implicit [[DEF]]
+  bb.0:
+    undef %0.sub0:vreg_128 = IMPLICIT_DEF
+    %0.sub1:vreg_128 = IMPLICIT_DEF
+    %1:vreg_128 = COPY %0
+    %2:vreg_128 = COPY killed %0
+    S_BRANCH %bb.2
+
+  bb.1:
+    %1:vreg_128 = COPY killed undef %1
+
+  bb.2:
+    %1.sub2:vreg_128 = COPY undef %3:sreg_32
+    %2:vreg_128 = COPY killed %1
+    %4:vreg_128 = COPY killed %2
+    S_ENDPGM 0, implicit killed %4
+
+...