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Differential D61332

[AMDGPU] gfx1010 DS implementation
ClosedPublic

Authored by rampitec on Apr 30 2019, 12:13 PM.

Details

Reviewers
kzhuravl
msearles
Commits
rGa224f68a10d6: [AMDGPU] gfx1010 DS implementation
rL359696: [AMDGPU] gfx1010 DS implementation

Diff Detail

Event Timeline

rampitec created this revision.Apr 30 2019, 12:13 PM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptApr 30 2019, 12:13 PM
rampitec added a parent revision: D61330: [AMDGPU] gfx1010 VMEM and SMEM implementation.Apr 30 2019, 12:14 PM
rampitec added a child revision: D61339: [AMDGPU] gfx1010 MIMG implementation.Apr 30 2019, 1:55 PM
rampitec added a child revision: D61341: [AMDGPU] gfx1010 GCNNSAReassign pass.Apr 30 2019, 2:15 PM
rampitec added a child revision: D61344: [AMDGPU] gfx1010 GCNRegBankReassign pass.Apr 30 2019, 2:36 PM
kzhuravl accepted this revision.May 1 2019, 8:20 AM

LGTM

This revision is now accepted and ready to land.May 1 2019, 8:20 AM
Closed by commit rL359696: [AMDGPU] gfx1010 DS implementation (authored by rampitec). · Explain WhyMay 1 2019, 9:09 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptMay 1 2019, 9:09 AM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
AsmParser/
5 lines
370 lines
11 lines
test/
CodeGen/
AMDGPU/
262 lines
MC/
AMDGPU/
10 lines

Diff 197403

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Show First 20 Lines • Show All 4,041 Lines • ▼ Show 20 Lines if (Op.isToken() && Op.getToken() == "gds") {
continue; continue;
} }
// Handle optional arguments // Handle optional arguments
OptionalIdx[Op.getImmTy()] = i; OptionalIdx[Op.getImmTy()] = i;
} }
AMDGPUOperand::ImmTy OffsetType = AMDGPUOperand::ImmTy OffsetType =
(Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_si || (Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_gfx10 ||
Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_gfx6_gfx7 ||
Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_vi) ? AMDGPUOperand::ImmTySwizzle : Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_vi) ? AMDGPUOperand::ImmTySwizzle :
AMDGPUOperand::ImmTyOffset; AMDGPUOperand::ImmTyOffset;
addOptionalImmOperand(Inst, Operands, OptionalIdx, OffsetType); addOptionalImmOperand(Inst, Operands, OptionalIdx, OffsetType);
if (!IsGdsHardcoded) { if (!IsGdsHardcoded) {
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);
} }
▲ Show 20 Lines • Show All 1,100 Lines • ▼ Show 20 Lines for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {
} }
// Handle the case where soffset is an immediate // Handle the case where soffset is an immediate
if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) { if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {
Op.addImmOperands(Inst, 1); Op.addImmOperands(Inst, 1);
continue; continue;
} }
HasLdsModifier = Op.isLDS(); HasLdsModifier |= Op.isLDS();
// Handle tokens like 'offen' which are sometimes hard-coded into the // Handle tokens like 'offen' which are sometimes hard-coded into the
// asm string. There are no MCInst operands for these. // asm string. There are no MCInst operands for these.
if (Op.isToken()) { if (Op.isToken()) {
continue; continue;
} }
assert(Op.isImm()); assert(Op.isImm());
▲ Show 20 Lines • Show All 997 Lines • Show Last 20 Lines

lib/Target/AMDGPU/DSInstructions.td

Show First 20 Lines • Show All 802 Lines • ▼ Show 20 Linesdef : Pat <
(DS_ORDERED_COUNT $value, (as_i16imm $offset)) (DS_ORDERED_COUNT $value, (as_i16imm $offset))
>; >;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Target-specific instruction encodings. // Target-specific instruction encodings.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Base ENC_DS for GFX6, GFX7. // Base ENC_DS for GFX6, GFX7, GFX10.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class DS_Real_si <bits<8> op, DS_Pseudo ds> : class Base_DS_Real_gfx6_gfx7_gfx10<bits<8> op, DS_Pseudo ps, int ef> :
DS_Real <ds>, DS_Real<ps>, SIMCInstr <ps.Mnemonic, ef> {
SIMCInstr <ds.Mnemonic, SIEncodingFamily.SI> {
let AssemblerPredicates=[isGFX6GFX7];
let DecoderNamespace="GFX6GFX7";
// encoding let Inst{7-0} = !if(ps.has_offset0, offset0, 0);
let Inst{7-0} = !if(ds.has_offset0, offset0, 0); let Inst{15-8} = !if(ps.has_offset1, offset1, 0);
let Inst{15-8} = !if(ds.has_offset1, offset1, 0); let Inst{17} = !if(ps.has_gds, gds, ps.gdsValue);
let Inst{17} = !if(ds.has_gds, gds, ds.gdsValue);
let Inst{25-18} = op; let Inst{25-18} = op;
let Inst{31-26} = 0x36; // ds prefix let Inst{31-26} = 0x36;
let Inst{39-32} = !if(ds.has_addr, addr, 0); let Inst{39-32} = !if(ps.has_addr, addr, 0);
let Inst{47-40} = !if(ds.has_data0, data0, 0); let Inst{47-40} = !if(ps.has_data0, data0, 0);
let Inst{55-48} = !if(ds.has_data1, data1, 0); let Inst{55-48} = !if(ps.has_data1, data1, 0);
let Inst{63-56} = !if(ds.has_vdst, vdst, 0); let Inst{63-56} = !if(ps.has_vdst, vdst, 0);
} }
def DS_ADD_U32_si : DS_Real_si<0x0, DS_ADD_U32>; //===----------------------------------------------------------------------===//
def DS_SUB_U32_si : DS_Real_si<0x1, DS_SUB_U32>; // GFX10.
def DS_RSUB_U32_si : DS_Real_si<0x2, DS_RSUB_U32>; //===----------------------------------------------------------------------===//
def DS_INC_U32_si : DS_Real_si<0x3, DS_INC_U32>;
def DS_DEC_U32_si : DS_Real_si<0x4, DS_DEC_U32>; let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
def DS_MIN_I32_si : DS_Real_si<0x5, DS_MIN_I32>; multiclass DS_Real_gfx10<bits<8> op> {
def DS_MAX_I32_si : DS_Real_si<0x6, DS_MAX_I32>; def _gfx10 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
def DS_MIN_U32_si : DS_Real_si<0x7, DS_MIN_U32>; SIEncodingFamily.GFX10>;
def DS_MAX_U32_si : DS_Real_si<0x8, DS_MAX_U32>; }
def DS_AND_B32_si : DS_Real_si<0x9, DS_AND_B32>; } // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
def DS_OR_B32_si : DS_Real_si<0xa, DS_OR_B32>;
def DS_XOR_B32_si : DS_Real_si<0xb, DS_XOR_B32>; defm DS_ADD_F32 : DS_Real_gfx10<0x015>;
def DS_MSKOR_B32_si : DS_Real_si<0xc, DS_MSKOR_B32>; defm DS_ADD_RTN_F32 : DS_Real_gfx10<0x055>;
def DS_WRITE_B32_si : DS_Real_si<0xd, DS_WRITE_B32>; defm DS_ADD_SRC2_F32 : DS_Real_gfx10<0x095>;
def DS_WRITE2_B32_si : DS_Real_si<0xe, DS_WRITE2_B32>; defm DS_WRITE_B8_D16_HI : DS_Real_gfx10<0x0a0>;
def DS_WRITE2ST64_B32_si : DS_Real_si<0xf, DS_WRITE2ST64_B32>; defm DS_WRITE_B16_D16_HI : DS_Real_gfx10<0x0a1>;
def DS_CMPST_B32_si : DS_Real_si<0x10, DS_CMPST_B32>; defm DS_READ_U8_D16 : DS_Real_gfx10<0x0a2>;
def DS_CMPST_F32_si : DS_Real_si<0x11, DS_CMPST_F32>; defm DS_READ_U8_D16_HI : DS_Real_gfx10<0x0a3>;
def DS_MIN_F32_si : DS_Real_si<0x12, DS_MIN_F32>; defm DS_READ_I8_D16 : DS_Real_gfx10<0x0a4>;
def DS_MAX_F32_si : DS_Real_si<0x13, DS_MAX_F32>; defm DS_READ_I8_D16_HI : DS_Real_gfx10<0x0a5>;
def DS_NOP_si : DS_Real_si<0x14, DS_NOP>; defm DS_READ_U16_D16 : DS_Real_gfx10<0x0a6>;
def DS_GWS_INIT_si : DS_Real_si<0x19, DS_GWS_INIT>; defm DS_READ_U16_D16_HI : DS_Real_gfx10<0x0a7>;
def DS_GWS_SEMA_V_si : DS_Real_si<0x1a, DS_GWS_SEMA_V>; defm DS_WRITE_ADDTID_B32 : DS_Real_gfx10<0x0b0>;
def DS_GWS_SEMA_BR_si : DS_Real_si<0x1b, DS_GWS_SEMA_BR>; defm DS_READ_ADDTID_B32 : DS_Real_gfx10<0x0b1>;
def DS_GWS_SEMA_P_si : DS_Real_si<0x1c, DS_GWS_SEMA_P>; defm DS_PERMUTE_B32 : DS_Real_gfx10<0x0b2>;
def DS_GWS_BARRIER_si : DS_Real_si<0x1d, DS_GWS_BARRIER>; defm DS_BPERMUTE_B32 : DS_Real_gfx10<0x0b3>;
def DS_WRITE_B8_si : DS_Real_si<0x1e, DS_WRITE_B8>;
def DS_WRITE_B16_si : DS_Real_si<0x1f, DS_WRITE_B16>; //===----------------------------------------------------------------------===//
def DS_ADD_RTN_U32_si : DS_Real_si<0x20, DS_ADD_RTN_U32>; // GFX7, GFX10.
def DS_SUB_RTN_U32_si : DS_Real_si<0x21, DS_SUB_RTN_U32>; //===----------------------------------------------------------------------===//
def DS_RSUB_RTN_U32_si : DS_Real_si<0x22, DS_RSUB_RTN_U32>;
def DS_INC_RTN_U32_si : DS_Real_si<0x23, DS_INC_RTN_U32>; let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
def DS_DEC_RTN_U32_si : DS_Real_si<0x24, DS_DEC_RTN_U32>; multiclass DS_Real_gfx7<bits<8> op> {
def DS_MIN_RTN_I32_si : DS_Real_si<0x25, DS_MIN_RTN_I32>; def _gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
def DS_MAX_RTN_I32_si : DS_Real_si<0x26, DS_MAX_RTN_I32>; SIEncodingFamily.SI>;
def DS_MIN_RTN_U32_si : DS_Real_si<0x27, DS_MIN_RTN_U32>; }
def DS_MAX_RTN_U32_si : DS_Real_si<0x28, DS_MAX_RTN_U32>; } // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"
def DS_AND_RTN_B32_si : DS_Real_si<0x29, DS_AND_RTN_B32>;
def DS_OR_RTN_B32_si : DS_Real_si<0x2a, DS_OR_RTN_B32>; multiclass DS_Real_gfx7_gfx10<bits<8> op> :
def DS_XOR_RTN_B32_si : DS_Real_si<0x2b, DS_XOR_RTN_B32>; DS_Real_gfx7<op>, DS_Real_gfx10<op>;
def DS_MSKOR_RTN_B32_si : DS_Real_si<0x2c, DS_MSKOR_RTN_B32>;
def DS_WRXCHG_RTN_B32_si : DS_Real_si<0x2d, DS_WRXCHG_RTN_B32>; // FIXME-GFX7: Add tests when upstreaming this part.
def DS_WRXCHG2_RTN_B32_si : DS_Real_si<0x2e, DS_WRXCHG2_RTN_B32>; defm DS_GWS_SEMA_RELEASE_ALL : DS_Real_gfx7_gfx10<0x018>;
def DS_WRXCHG2ST64_RTN_B32_si : DS_Real_si<0x2f, DS_WRXCHG2ST64_RTN_B32>; defm DS_WRAP_RTN_B32 : DS_Real_gfx7_gfx10<0x034>;
def DS_CMPST_RTN_B32_si : DS_Real_si<0x30, DS_CMPST_RTN_B32>; defm DS_CONDXCHG32_RTN_B64 : DS_Real_gfx7_gfx10<0x07e>;
def DS_CMPST_RTN_F32_si : DS_Real_si<0x31, DS_CMPST_RTN_F32>; defm DS_WRITE_B96 : DS_Real_gfx7_gfx10<0x0de>;
def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>; defm DS_WRITE_B128 : DS_Real_gfx7_gfx10<0x0df>;
def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>; defm DS_READ_B96 : DS_Real_gfx7_gfx10<0x0fe>;
defm DS_READ_B128 : DS_Real_gfx7_gfx10<0x0ff>;
// These instruction are CI/VI only
def DS_WRAP_RTN_B32_si : DS_Real_si<0x34, DS_WRAP_RTN_B32>; //===----------------------------------------------------------------------===//
def DS_CONDXCHG32_RTN_B64_si : DS_Real_si<0x7e, DS_CONDXCHG32_RTN_B64>; // GFX6, GFX7, GFX10.
def DS_GWS_SEMA_RELEASE_ALL_si : DS_Real_si<0x18, DS_GWS_SEMA_RELEASE_ALL>; //===----------------------------------------------------------------------===//
def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>; let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>; multiclass DS_Real_gfx6_gfx7<bits<8> op> {
def DS_READ2_B32_si : DS_Real_si<0x37, DS_READ2_B32>; def _gfx6_gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
def DS_READ2ST64_B32_si : DS_Real_si<0x38, DS_READ2ST64_B32>; SIEncodingFamily.SI>;
def DS_READ_I8_si : DS_Real_si<0x39, DS_READ_I8>; }
def DS_READ_U8_si : DS_Real_si<0x3a, DS_READ_U8>; } // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
def DS_READ_I16_si : DS_Real_si<0x3b, DS_READ_I16>;
def DS_READ_U16_si : DS_Real_si<0x3c, DS_READ_U16>; multiclass DS_Real_gfx6_gfx7_gfx10<bits<8> op> :
def DS_CONSUME_si : DS_Real_si<0x3d, DS_CONSUME>; DS_Real_gfx6_gfx7<op>, DS_Real_gfx10<op>;
def DS_APPEND_si : DS_Real_si<0x3e, DS_APPEND>;
def DS_ORDERED_COUNT_si : DS_Real_si<0x3f, DS_ORDERED_COUNT>; defm DS_ADD_U32 : DS_Real_gfx6_gfx7_gfx10<0x000>;
def DS_ADD_U64_si : DS_Real_si<0x40, DS_ADD_U64>; defm DS_SUB_U32 : DS_Real_gfx6_gfx7_gfx10<0x001>;
def DS_SUB_U64_si : DS_Real_si<0x41, DS_SUB_U64>; defm DS_RSUB_U32 : DS_Real_gfx6_gfx7_gfx10<0x002>;
def DS_RSUB_U64_si : DS_Real_si<0x42, DS_RSUB_U64>; defm DS_INC_U32 : DS_Real_gfx6_gfx7_gfx10<0x003>;
def DS_INC_U64_si : DS_Real_si<0x43, DS_INC_U64>; defm DS_DEC_U32 : DS_Real_gfx6_gfx7_gfx10<0x004>;
def DS_DEC_U64_si : DS_Real_si<0x44, DS_DEC_U64>; defm DS_MIN_I32 : DS_Real_gfx6_gfx7_gfx10<0x005>;
def DS_MIN_I64_si : DS_Real_si<0x45, DS_MIN_I64>; defm DS_MAX_I32 : DS_Real_gfx6_gfx7_gfx10<0x006>;
def DS_MAX_I64_si : DS_Real_si<0x46, DS_MAX_I64>; defm DS_MIN_U32 : DS_Real_gfx6_gfx7_gfx10<0x007>;
def DS_MIN_U64_si : DS_Real_si<0x47, DS_MIN_U64>; defm DS_MAX_U32 : DS_Real_gfx6_gfx7_gfx10<0x008>;
def DS_MAX_U64_si : DS_Real_si<0x48, DS_MAX_U64>; defm DS_AND_B32 : DS_Real_gfx6_gfx7_gfx10<0x009>;
def DS_AND_B64_si : DS_Real_si<0x49, DS_AND_B64>; defm DS_OR_B32 : DS_Real_gfx6_gfx7_gfx10<0x00a>;
def DS_OR_B64_si : DS_Real_si<0x4a, DS_OR_B64>; defm DS_XOR_B32 : DS_Real_gfx6_gfx7_gfx10<0x00b>;
def DS_XOR_B64_si : DS_Real_si<0x4b, DS_XOR_B64>; defm DS_MSKOR_B32 : DS_Real_gfx6_gfx7_gfx10<0x00c>;
def DS_MSKOR_B64_si : DS_Real_si<0x4c, DS_MSKOR_B64>; defm DS_WRITE_B32 : DS_Real_gfx6_gfx7_gfx10<0x00d>;
def DS_WRITE_B64_si : DS_Real_si<0x4d, DS_WRITE_B64>; defm DS_WRITE2_B32 : DS_Real_gfx6_gfx7_gfx10<0x00e>;
def DS_WRITE2_B64_si : DS_Real_si<0x4E, DS_WRITE2_B64>; defm DS_WRITE2ST64_B32 : DS_Real_gfx6_gfx7_gfx10<0x00f>;
def DS_WRITE2ST64_B64_si : DS_Real_si<0x4f, DS_WRITE2ST64_B64>; defm DS_CMPST_B32 : DS_Real_gfx6_gfx7_gfx10<0x010>;
def DS_CMPST_B64_si : DS_Real_si<0x50, DS_CMPST_B64>; defm DS_CMPST_F32 : DS_Real_gfx6_gfx7_gfx10<0x011>;
def DS_CMPST_F64_si : DS_Real_si<0x51, DS_CMPST_F64>; defm DS_MIN_F32 : DS_Real_gfx6_gfx7_gfx10<0x012>;
def DS_MIN_F64_si : DS_Real_si<0x52, DS_MIN_F64>; defm DS_MAX_F32 : DS_Real_gfx6_gfx7_gfx10<0x013>;
def DS_MAX_F64_si : DS_Real_si<0x53, DS_MAX_F64>; defm DS_NOP : DS_Real_gfx6_gfx7_gfx10<0x014>;
defm DS_GWS_INIT : DS_Real_gfx6_gfx7_gfx10<0x019>;
def DS_ADD_RTN_U64_si : DS_Real_si<0x60, DS_ADD_RTN_U64>; defm DS_GWS_SEMA_V : DS_Real_gfx6_gfx7_gfx10<0x01a>;
def DS_SUB_RTN_U64_si : DS_Real_si<0x61, DS_SUB_RTN_U64>; defm DS_GWS_SEMA_BR : DS_Real_gfx6_gfx7_gfx10<0x01b>;
def DS_RSUB_RTN_U64_si : DS_Real_si<0x62, DS_RSUB_RTN_U64>; defm DS_GWS_SEMA_P : DS_Real_gfx6_gfx7_gfx10<0x01c>;
def DS_INC_RTN_U64_si : DS_Real_si<0x63, DS_INC_RTN_U64>; defm DS_GWS_BARRIER : DS_Real_gfx6_gfx7_gfx10<0x01d>;
def DS_DEC_RTN_U64_si : DS_Real_si<0x64, DS_DEC_RTN_U64>; defm DS_WRITE_B8 : DS_Real_gfx6_gfx7_gfx10<0x01e>;
def DS_MIN_RTN_I64_si : DS_Real_si<0x65, DS_MIN_RTN_I64>; defm DS_WRITE_B16 : DS_Real_gfx6_gfx7_gfx10<0x01f>;
def DS_MAX_RTN_I64_si : DS_Real_si<0x66, DS_MAX_RTN_I64>; defm DS_ADD_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x020>;
def DS_MIN_RTN_U64_si : DS_Real_si<0x67, DS_MIN_RTN_U64>; defm DS_SUB_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x021>;
def DS_MAX_RTN_U64_si : DS_Real_si<0x68, DS_MAX_RTN_U64>; defm DS_RSUB_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x022>;
def DS_AND_RTN_B64_si : DS_Real_si<0x69, DS_AND_RTN_B64>; defm DS_INC_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x023>;
def DS_OR_RTN_B64_si : DS_Real_si<0x6a, DS_OR_RTN_B64>; defm DS_DEC_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x024>;
def DS_XOR_RTN_B64_si : DS_Real_si<0x6b, DS_XOR_RTN_B64>; defm DS_MIN_RTN_I32 : DS_Real_gfx6_gfx7_gfx10<0x025>;
def DS_MSKOR_RTN_B64_si : DS_Real_si<0x6c, DS_MSKOR_RTN_B64>; defm DS_MAX_RTN_I32 : DS_Real_gfx6_gfx7_gfx10<0x026>;
def DS_WRXCHG_RTN_B64_si : DS_Real_si<0x6d, DS_WRXCHG_RTN_B64>; defm DS_MIN_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x027>;
def DS_WRXCHG2_RTN_B64_si : DS_Real_si<0x6e, DS_WRXCHG2_RTN_B64>; defm DS_MAX_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x028>;
def DS_WRXCHG2ST64_RTN_B64_si : DS_Real_si<0x6f, DS_WRXCHG2ST64_RTN_B64>; defm DS_AND_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x029>;
def DS_CMPST_RTN_B64_si : DS_Real_si<0x70, DS_CMPST_RTN_B64>; defm DS_OR_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02a>;
def DS_CMPST_RTN_F64_si : DS_Real_si<0x71, DS_CMPST_RTN_F64>; defm DS_XOR_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02b>;
def DS_MIN_RTN_F64_si : DS_Real_si<0x72, DS_MIN_RTN_F64>; defm DS_MSKOR_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02c>;
def DS_MAX_RTN_F64_si : DS_Real_si<0x73, DS_MAX_RTN_F64>; defm DS_WRXCHG_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02d>;
defm DS_WRXCHG2_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02e>;
def DS_READ_B64_si : DS_Real_si<0x76, DS_READ_B64>; defm DS_WRXCHG2ST64_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02f>;
def DS_READ2_B64_si : DS_Real_si<0x77, DS_READ2_B64>; defm DS_CMPST_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x030>;
def DS_READ2ST64_B64_si : DS_Real_si<0x78, DS_READ2ST64_B64>; defm DS_CMPST_RTN_F32 : DS_Real_gfx6_gfx7_gfx10<0x031>;
defm DS_MIN_RTN_F32 : DS_Real_gfx6_gfx7_gfx10<0x032>;
def DS_ADD_SRC2_U32_si : DS_Real_si<0x80, DS_ADD_SRC2_U32>; defm DS_MAX_RTN_F32 : DS_Real_gfx6_gfx7_gfx10<0x033>;
def DS_SUB_SRC2_U32_si : DS_Real_si<0x81, DS_SUB_SRC2_U32>; defm DS_SWIZZLE_B32 : DS_Real_gfx6_gfx7_gfx10<0x035>;
def DS_RSUB_SRC2_U32_si : DS_Real_si<0x82, DS_RSUB_SRC2_U32>; defm DS_READ_B32 : DS_Real_gfx6_gfx7_gfx10<0x036>;
def DS_INC_SRC2_U32_si : DS_Real_si<0x83, DS_INC_SRC2_U32>; defm DS_READ2_B32 : DS_Real_gfx6_gfx7_gfx10<0x037>;
def DS_DEC_SRC2_U32_si : DS_Real_si<0x84, DS_DEC_SRC2_U32>; defm DS_READ2ST64_B32 : DS_Real_gfx6_gfx7_gfx10<0x038>;
def DS_MIN_SRC2_I32_si : DS_Real_si<0x85, DS_MIN_SRC2_I32>; defm DS_READ_I8 : DS_Real_gfx6_gfx7_gfx10<0x039>;
def DS_MAX_SRC2_I32_si : DS_Real_si<0x86, DS_MAX_SRC2_I32>; defm DS_READ_U8 : DS_Real_gfx6_gfx7_gfx10<0x03a>;
def DS_MIN_SRC2_U32_si : DS_Real_si<0x87, DS_MIN_SRC2_U32>; defm DS_READ_I16 : DS_Real_gfx6_gfx7_gfx10<0x03b>;
def DS_MAX_SRC2_U32_si : DS_Real_si<0x88, DS_MAX_SRC2_U32>; defm DS_READ_U16 : DS_Real_gfx6_gfx7_gfx10<0x03c>;
def DS_AND_SRC2_B32_si : DS_Real_si<0x89, DS_AND_SRC2_B32>; defm DS_CONSUME : DS_Real_gfx6_gfx7_gfx10<0x03d>;
def DS_OR_SRC2_B32_si : DS_Real_si<0x8a, DS_OR_SRC2_B32>; defm DS_APPEND : DS_Real_gfx6_gfx7_gfx10<0x03e>;
def DS_XOR_SRC2_B32_si : DS_Real_si<0x8b, DS_XOR_SRC2_B32>; defm DS_ORDERED_COUNT : DS_Real_gfx6_gfx7_gfx10<0x03f>;
def DS_WRITE_SRC2_B32_si : DS_Real_si<0x8d, DS_WRITE_SRC2_B32>; defm DS_ADD_U64 : DS_Real_gfx6_gfx7_gfx10<0x040>;
defm DS_SUB_U64 : DS_Real_gfx6_gfx7_gfx10<0x041>;
def DS_MIN_SRC2_F32_si : DS_Real_si<0x92, DS_MIN_SRC2_F32>; defm DS_RSUB_U64 : DS_Real_gfx6_gfx7_gfx10<0x042>;
def DS_MAX_SRC2_F32_si : DS_Real_si<0x93, DS_MAX_SRC2_F32>; defm DS_INC_U64 : DS_Real_gfx6_gfx7_gfx10<0x043>;
defm DS_DEC_U64 : DS_Real_gfx6_gfx7_gfx10<0x044>;
def DS_ADD_SRC2_U64_si : DS_Real_si<0xc0, DS_ADD_SRC2_U64>; defm DS_MIN_I64 : DS_Real_gfx6_gfx7_gfx10<0x045>;
def DS_SUB_SRC2_U64_si : DS_Real_si<0xc1, DS_SUB_SRC2_U64>; defm DS_MAX_I64 : DS_Real_gfx6_gfx7_gfx10<0x046>;
def DS_RSUB_SRC2_U64_si : DS_Real_si<0xc2, DS_RSUB_SRC2_U64>; defm DS_MIN_U64 : DS_Real_gfx6_gfx7_gfx10<0x047>;
def DS_INC_SRC2_U64_si : DS_Real_si<0xc3, DS_INC_SRC2_U64>; defm DS_MAX_U64 : DS_Real_gfx6_gfx7_gfx10<0x048>;
def DS_DEC_SRC2_U64_si : DS_Real_si<0xc4, DS_DEC_SRC2_U64>; defm DS_AND_B64 : DS_Real_gfx6_gfx7_gfx10<0x049>;
def DS_MIN_SRC2_I64_si : DS_Real_si<0xc5, DS_MIN_SRC2_I64>; defm DS_OR_B64 : DS_Real_gfx6_gfx7_gfx10<0x04a>;
def DS_MAX_SRC2_I64_si : DS_Real_si<0xc6, DS_MAX_SRC2_I64>; defm DS_XOR_B64 : DS_Real_gfx6_gfx7_gfx10<0x04b>;
def DS_MIN_SRC2_U64_si : DS_Real_si<0xc7, DS_MIN_SRC2_U64>; defm DS_MSKOR_B64 : DS_Real_gfx6_gfx7_gfx10<0x04c>;
def DS_MAX_SRC2_U64_si : DS_Real_si<0xc8, DS_MAX_SRC2_U64>; defm DS_WRITE_B64 : DS_Real_gfx6_gfx7_gfx10<0x04d>;
def DS_AND_SRC2_B64_si : DS_Real_si<0xc9, DS_AND_SRC2_B64>; defm DS_WRITE2_B64 : DS_Real_gfx6_gfx7_gfx10<0x04e>;
def DS_OR_SRC2_B64_si : DS_Real_si<0xca, DS_OR_SRC2_B64>; defm DS_WRITE2ST64_B64 : DS_Real_gfx6_gfx7_gfx10<0x04f>;
def DS_XOR_SRC2_B64_si : DS_Real_si<0xcb, DS_XOR_SRC2_B64>; defm DS_CMPST_B64 : DS_Real_gfx6_gfx7_gfx10<0x050>;
def DS_WRITE_SRC2_B64_si : DS_Real_si<0xcd, DS_WRITE_SRC2_B64>; defm DS_CMPST_F64 : DS_Real_gfx6_gfx7_gfx10<0x051>;
defm DS_MIN_F64 : DS_Real_gfx6_gfx7_gfx10<0x052>;
def DS_MIN_SRC2_F64_si : DS_Real_si<0xd2, DS_MIN_SRC2_F64>; defm DS_MAX_F64 : DS_Real_gfx6_gfx7_gfx10<0x053>;
def DS_MAX_SRC2_F64_si : DS_Real_si<0xd3, DS_MAX_SRC2_F64>; defm DS_ADD_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x060>;
def DS_WRITE_B96_si : DS_Real_si<0xde, DS_WRITE_B96>; defm DS_SUB_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x061>;
def DS_WRITE_B128_si : DS_Real_si<0xdf, DS_WRITE_B128>; defm DS_RSUB_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x062>;
def DS_READ_B96_si : DS_Real_si<0xfe, DS_READ_B96>; defm DS_INC_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x063>;
def DS_READ_B128_si : DS_Real_si<0xff, DS_READ_B128>; defm DS_DEC_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x064>;
defm DS_MIN_RTN_I64 : DS_Real_gfx6_gfx7_gfx10<0x065>;
defm DS_MAX_RTN_I64 : DS_Real_gfx6_gfx7_gfx10<0x066>;
defm DS_MIN_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x067>;
defm DS_MAX_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x068>;
defm DS_AND_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x069>;
defm DS_OR_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06a>;
defm DS_XOR_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06b>;
defm DS_MSKOR_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06c>;
defm DS_WRXCHG_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06d>;
defm DS_WRXCHG2_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06e>;
defm DS_WRXCHG2ST64_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06f>;
defm DS_CMPST_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x070>;
defm DS_CMPST_RTN_F64 : DS_Real_gfx6_gfx7_gfx10<0x071>;
defm DS_MIN_RTN_F64 : DS_Real_gfx6_gfx7_gfx10<0x072>;
defm DS_MAX_RTN_F64 : DS_Real_gfx6_gfx7_gfx10<0x073>;
defm DS_READ_B64 : DS_Real_gfx6_gfx7_gfx10<0x076>;
defm DS_READ2_B64 : DS_Real_gfx6_gfx7_gfx10<0x077>;
defm DS_READ2ST64_B64 : DS_Real_gfx6_gfx7_gfx10<0x078>;
defm DS_ADD_SRC2_U32 : DS_Real_gfx6_gfx7_gfx10<0x080>;
defm DS_SUB_SRC2_U32 : DS_Real_gfx6_gfx7_gfx10<0x081>;
defm DS_RSUB_SRC2_U32 : DS_Real_gfx6_gfx7_gfx10<0x082>;
defm DS_INC_SRC2_U32 : DS_Real_gfx6_gfx7_gfx10<0x083>;
defm DS_DEC_SRC2_U32 : DS_Real_gfx6_gfx7_gfx10<0x084>;
defm DS_MIN_SRC2_I32 : DS_Real_gfx6_gfx7_gfx10<0x085>;
defm DS_MAX_SRC2_I32 : DS_Real_gfx6_gfx7_gfx10<0x086>;
defm DS_MIN_SRC2_U32 : DS_Real_gfx6_gfx7_gfx10<0x087>;
defm DS_MAX_SRC2_U32 : DS_Real_gfx6_gfx7_gfx10<0x088>;
defm DS_AND_SRC2_B32 : DS_Real_gfx6_gfx7_gfx10<0x089>;
defm DS_OR_SRC2_B32 : DS_Real_gfx6_gfx7_gfx10<0x08a>;
defm DS_XOR_SRC2_B32 : DS_Real_gfx6_gfx7_gfx10<0x08b>;
defm DS_WRITE_SRC2_B32 : DS_Real_gfx6_gfx7_gfx10<0x08d>;
defm DS_MIN_SRC2_F32 : DS_Real_gfx6_gfx7_gfx10<0x092>;
defm DS_MAX_SRC2_F32 : DS_Real_gfx6_gfx7_gfx10<0x093>;
defm DS_ADD_SRC2_U64 : DS_Real_gfx6_gfx7_gfx10<0x0c0>;
defm DS_SUB_SRC2_U64 : DS_Real_gfx6_gfx7_gfx10<0x0c1>;
defm DS_RSUB_SRC2_U64 : DS_Real_gfx6_gfx7_gfx10<0x0c2>;
defm DS_INC_SRC2_U64 : DS_Real_gfx6_gfx7_gfx10<0x0c3>;
defm DS_DEC_SRC2_U64 : DS_Real_gfx6_gfx7_gfx10<0x0c4>;
defm DS_MIN_SRC2_I64 : DS_Real_gfx6_gfx7_gfx10<0x0c5>;
defm DS_MAX_SRC2_I64 : DS_Real_gfx6_gfx7_gfx10<0x0c6>;
defm DS_MIN_SRC2_U64 : DS_Real_gfx6_gfx7_gfx10<0x0c7>;
defm DS_MAX_SRC2_U64 : DS_Real_gfx6_gfx7_gfx10<0x0c8>;
defm DS_AND_SRC2_B64 : DS_Real_gfx6_gfx7_gfx10<0x0c9>;
defm DS_OR_SRC2_B64 : DS_Real_gfx6_gfx7_gfx10<0x0ca>;
defm DS_XOR_SRC2_B64 : DS_Real_gfx6_gfx7_gfx10<0x0cb>;
defm DS_WRITE_SRC2_B64 : DS_Real_gfx6_gfx7_gfx10<0x0cd>;
defm DS_MIN_SRC2_F64 : DS_Real_gfx6_gfx7_gfx10<0x0d2>;
defm DS_MAX_SRC2_F64 : DS_Real_gfx6_gfx7_gfx10<0x0d3>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// GFX8, GFX9 (VI). // GFX8, GFX9 (VI).
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class DS_Real_vi <bits<8> op, DS_Pseudo ds> : class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
DS_Real <ds>, DS_Real <ds>,
SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> { SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
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lib/Target/AMDGPU/SIISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 6,643 Lines • ▼ Show 20 LinesSDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
unsigned Alignment = Load->getAlignment(); unsigned Alignment = Load->getAlignment();
unsigned AS = Load->getAddressSpace(); unsigned AS = Load->getAddressSpace();
if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT, if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
AS, Alignment)) { AS, Alignment)) {
SDValue Ops[2]; SDValue Ops[2];
std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(Load, DAG); std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(Load, DAG);
return DAG.getMergeValues(Ops, DL); return DAG.getMergeValues(Ops, DL);
} }
if (Subtarget->hasLDSMisalignedBug() &&
AS == AMDGPUAS::FLAT_ADDRESS &&
Alignment < MemVT.getStoreSize() && MemVT.getSizeInBits() > 32) {
return SplitVectorLoad(Op, DAG);
}
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
// If there is a possibilty that flat instruction access scratch memory // If there is a possibilty that flat instruction access scratch memory
// then we need to use the same legalization rules we use for private. // then we need to use the same legalization rules we use for private.
if (AS == AMDGPUAS::FLAT_ADDRESS) if (AS == AMDGPUAS::FLAT_ADDRESS)
AS = MFI->hasFlatScratchInit() ? AS = MFI->hasFlatScratchInit() ?
AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS; AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS;
▲ Show 20 Lines • Show All 445 Lines • ▼ Show 20 Lines assert(VT.isVector() &&
Store->getValue().getValueType().getScalarType() == MVT::i32); Store->getValue().getValueType().getScalarType() == MVT::i32);
unsigned AS = Store->getAddressSpace(); unsigned AS = Store->getAddressSpace();
if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT, if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
AS, Store->getAlignment())) { AS, Store->getAlignment())) {
return expandUnalignedStore(Store, DAG); return expandUnalignedStore(Store, DAG);
} }
if (Subtarget->hasLDSMisalignedBug() &&
AS == AMDGPUAS::FLAT_ADDRESS &&
Store->getAlignment() < VT.getStoreSize() && VT.getSizeInBits() > 32) {
return SplitVectorStore(Op, DAG);
}
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
// If there is a possibilty that flat instruction access scratch memory // If there is a possibilty that flat instruction access scratch memory
// then we need to use the same legalization rules we use for private. // then we need to use the same legalization rules we use for private.
if (AS == AMDGPUAS::FLAT_ADDRESS) if (AS == AMDGPUAS::FLAT_ADDRESS)
AS = MFI->hasFlatScratchInit() ? AS = MFI->hasFlatScratchInit() ?
AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS; AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS;
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test/CodeGen/AMDGPU/lds-misaligned-bug.ll

  • This file was added.
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SPLIT %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -mattr=+cumode < %s | FileCheck -check-prefixes=GCN,VECT %s
; GCN-LABEL: test_local_misaligned_v2:
; GCN-DAG: ds_read2_b32
; GCN-DAG: ds_write2_b32
define amdgpu_kernel void @test_local_misaligned_v2(i32 addrspace(3)* %arg) {
bb:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid
%ptr = bitcast i32 addrspace(3)* %gep to <2 x i32> addrspace(3)*
%load = load <2 x i32>, <2 x i32> addrspace(3)* %ptr, align 4
%v1 = extractelement <2 x i32> %load, i32 0
%v2 = extractelement <2 x i32> %load, i32 1
%v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
store <2 x i32> %v4, <2 x i32> addrspace(3)* %ptr, align 4
ret void
}
; GCN-LABEL: test_local_misaligned_v4:
; GCN-DAG: ds_read2_b32
; GCN-DAG: ds_read2_b32
; GCN-DAG: ds_write2_b32
; GCN-DAG: ds_write2_b32
define amdgpu_kernel void @test_local_misaligned_v4(i32 addrspace(3)* %arg) {
bb:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid
%ptr = bitcast i32 addrspace(3)* %gep to <4 x i32> addrspace(3)*
%load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 4
%v1 = extractelement <4 x i32> %load, i32 0
%v2 = extractelement <4 x i32> %load, i32 1
%v3 = extractelement <4 x i32> %load, i32 2
%v4 = extractelement <4 x i32> %load, i32 3
%v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
store <4 x i32> %v8, <4 x i32> addrspace(3)* %ptr, align 4
ret void
}
; GCN-LABEL: test_local_misaligned_v3:
; GCN-DAG: ds_read2_b32
; GCN-DAG: ds_read_b32
; GCN-DAG: ds_write2_b32
; GCN-DAG: ds_write_b32
define amdgpu_kernel void @test_local_misaligned_v3(i32 addrspace(3)* %arg) {
bb:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid
%ptr = bitcast i32 addrspace(3)* %gep to <3 x i32> addrspace(3)*
%load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 4
%v1 = extractelement <3 x i32> %load, i32 0
%v2 = extractelement <3 x i32> %load, i32 1
%v3 = extractelement <3 x i32> %load, i32 2
%v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
store <3 x i32> %v7, <3 x i32> addrspace(3)* %ptr, align 4
ret void
}
; GCN-LABEL: test_flat_misaligned_v2:
; VECT-DAG: flat_load_dwordx2 v
; VECT-DAG: flat_store_dwordx2 v
; SPLIT-DAG: flat_load_dword v
; SPLIT-DAG: flat_load_dword v
; SPLIT-DAG: flat_store_dword v
; SPLIT-DAG: flat_store_dword v
define amdgpu_kernel void @test_flat_misaligned_v2(i32* %arg) {
bb:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32* %arg, i32 %lid
%ptr = bitcast i32* %gep to <2 x i32>*
%load = load <2 x i32>, <2 x i32>* %ptr, align 4
%v1 = extractelement <2 x i32> %load, i32 0
%v2 = extractelement <2 x i32> %load, i32 1
%v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
store <2 x i32> %v4, <2 x i32>* %ptr, align 4
ret void
}
; GCN-LABEL: test_flat_misaligned_v4:
; VECT-DAG: flat_load_dwordx4 v
; VECT-DAG: flat_store_dwordx4 v
; SPLIT-DAG: flat_load_dword v
; SPLIT-DAG: flat_load_dword v
; SPLIT-DAG: flat_load_dword v
; SPLIT-DAG: flat_load_dword v
; SPLIT-DAG: flat_store_dword v
; SPLIT-DAG: flat_store_dword v
; SPLIT-DAG: flat_store_dword v
; SPLIT-DAG: flat_store_dword v
define amdgpu_kernel void @test_flat_misaligned_v4(i32* %arg) {
bb:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32* %arg, i32 %lid
%ptr = bitcast i32* %gep to <4 x i32>*
%load = load <4 x i32>, <4 x i32>* %ptr, align 4
%v1 = extractelement <4 x i32> %load, i32 0
%v2 = extractelement <4 x i32> %load, i32 1
%v3 = extractelement <4 x i32> %load, i32 2
%v4 = extractelement <4 x i32> %load, i32 3
%v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
store <4 x i32> %v8, <4 x i32>* %ptr, align 4
ret void
}
; GCN-LABEL: test_flat_misaligned_v3:
; VECT-DAG: flat_load_dwordx3 v
; VECT-DAG: flat_store_dwordx3 v
; SPLIT-DAG: flat_load_dword v
; SPLIT-DAG: flat_load_dword v
; SPLIT-DAG: flat_load_dword v
; SPLIT-DAG: flat_store_dword v
; SPLIT-DAG: flat_store_dword v
; SPLIT-DAG: flat_store_dword v
define amdgpu_kernel void @test_flat_misaligned_v3(i32* %arg) {
bb:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32* %arg, i32 %lid
%ptr = bitcast i32* %gep to <3 x i32>*
%load = load <3 x i32>, <3 x i32>* %ptr, align 4
%v1 = extractelement <3 x i32> %load, i32 0
%v2 = extractelement <3 x i32> %load, i32 1
%v3 = extractelement <3 x i32> %load, i32 2
%v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
store <3 x i32> %v7, <3 x i32>* %ptr, align 4
ret void
}
; GCN-LABEL: test_local_aligned_v2:
; GCN-DAG: ds_read_b64
; GCN-DAG: ds_write_b64
define amdgpu_kernel void @test_local_aligned_v2(i32 addrspace(3)* %arg) {
bb:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid
%ptr = bitcast i32 addrspace(3)* %gep to <2 x i32> addrspace(3)*
%load = load <2 x i32>, <2 x i32> addrspace(3)* %ptr, align 8
%v1 = extractelement <2 x i32> %load, i32 0
%v2 = extractelement <2 x i32> %load, i32 1
%v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
store <2 x i32> %v4, <2 x i32> addrspace(3)* %ptr, align 8
ret void
}
; GCN-LABEL: test_local_aligned_v3:
; GCN-DAG: ds_read_b64
; GCN-DAG: ds_read_b32
; GCN-DAG: ds_write_b64
; GCN-DAG: ds_write_b32
define amdgpu_kernel void @test_local_aligned_v3(i32 addrspace(3)* %arg) {
bb:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid
%ptr = bitcast i32 addrspace(3)* %gep to <3 x i32> addrspace(3)*
%load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 16
%v1 = extractelement <3 x i32> %load, i32 0
%v2 = extractelement <3 x i32> %load, i32 1
%v3 = extractelement <3 x i32> %load, i32 2
%v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
store <3 x i32> %v7, <3 x i32> addrspace(3)* %ptr, align 16
ret void
}
; GCN-LABEL: test_flat_aligned_v2:
; GCN-DAG: flat_load_dwordx2 v
; GCN-DAG: flat_store_dwordx2 v
define amdgpu_kernel void @test_flat_aligned_v2(i32* %arg) {
bb:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32* %arg, i32 %lid
%ptr = bitcast i32* %gep to <2 x i32>*
%load = load <2 x i32>, <2 x i32>* %ptr, align 8
%v1 = extractelement <2 x i32> %load, i32 0
%v2 = extractelement <2 x i32> %load, i32 1
%v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
store <2 x i32> %v4, <2 x i32>* %ptr, align 8
ret void
}
; GCN-LABEL: test_flat_aligned_v4:
; GCN-DAG: flat_load_dwordx4 v
; GCN-DAG: flat_store_dwordx4 v
define amdgpu_kernel void @test_flat_aligned_v4(i32* %arg) {
bb:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32* %arg, i32 %lid
%ptr = bitcast i32* %gep to <4 x i32>*
%load = load <4 x i32>, <4 x i32>* %ptr, align 16
%v1 = extractelement <4 x i32> %load, i32 0
%v2 = extractelement <4 x i32> %load, i32 1
%v3 = extractelement <4 x i32> %load, i32 2
%v4 = extractelement <4 x i32> %load, i32 3
%v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
store <4 x i32> %v8, <4 x i32>* %ptr, align 16
ret void
}
; GCN-LABEL: test_local_v4_aligned8:
; GCN-DAG: ds_read2_b64
; GCN-DAG: ds_write2_b64
define amdgpu_kernel void @test_local_v4_aligned8(i32 addrspace(3)* %arg) {
bb:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid
%ptr = bitcast i32 addrspace(3)* %gep to <4 x i32> addrspace(3)*
%load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 8
%v1 = extractelement <4 x i32> %load, i32 0
%v2 = extractelement <4 x i32> %load, i32 1
%v3 = extractelement <4 x i32> %load, i32 2
%v4 = extractelement <4 x i32> %load, i32 3
%v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
store <4 x i32> %v8, <4 x i32> addrspace(3)* %ptr, align 8
ret void
}
; GCN-LABEL: test_flat_v4_aligned8:
; VECT-DAG: flat_load_dwordx4 v
; VECT-DAG: flat_store_dwordx4 v
; SPLIT-DAG: flat_load_dwordx2 v
; SPLIT-DAG: flat_load_dwordx2 v
; SPLIT-DAG: flat_store_dwordx2 v
; SPLIT-DAG: flat_store_dwordx2 v
define amdgpu_kernel void @test_flat_v4_aligned8(i32* %arg) {
bb:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32* %arg, i32 %lid
%ptr = bitcast i32* %gep to <4 x i32>*
%load = load <4 x i32>, <4 x i32>* %ptr, align 8
%v1 = extractelement <4 x i32> %load, i32 0
%v2 = extractelement <4 x i32> %load, i32 1
%v3 = extractelement <4 x i32> %load, i32 2
%v4 = extractelement <4 x i32> %load, i32 3
%v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
store <4 x i32> %v8, <4 x i32>* %ptr, align 8
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x()

test/MC/AMDGPU/mubuf-gfx10.s

  • This file was added.
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds
// GFX10: buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds ; encoding: [0x00,0x40,0x25,0xe0,0x00,0x05,0x42,0x03]
buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds dlc
// GFX10: buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds dlc ; encoding: [0x00,0xc0,0x25,0xe0,0x00,0x05,0x42,0x03]
buffer_load_sbyte v5, off, s[8:11], s3 glc slc dlc
// GFX10: buffer_load_sbyte v5, off, s[8:11], s3 glc slc dlc ; encoding: [0x00,0xc0,0x24,0xe0,0x00,0x05,0x42,0x03]