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Differential D61330

[AMDGPU] gfx1010 VMEM and SMEM implementation
ClosedPublic

Authored by rampitec on Apr 30 2019, 11:46 AM.

Details

Reviewers
kzhuravl
msearles
Commits
rGa6322941ffc1: [AMDGPU] gfx1010 VMEM and SMEM implementation
rL359621: [AMDGPU] gfx1010 VMEM and SMEM implementation

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rL LLVM

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include/
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IR/
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AMDGPU/
GlobalISel/
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Diff 197456

llvm/trunk/include/llvm/IR/IntrinsicsAMDGPU.td

Show First 20 Lines • Show All 1,425 Lines • ▼ Show 20 Linesdef int_amdgcn_ds_permute :
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>; Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
// llvm.amdgcn.ds.bpermute <index> <src> // llvm.amdgcn.ds.bpermute <index> <src>
def int_amdgcn_ds_bpermute : def int_amdgcn_ds_bpermute :
GCCBuiltin<"__builtin_amdgcn_ds_bpermute">, GCCBuiltin<"__builtin_amdgcn_ds_bpermute">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>; Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// GFX10 Intrinsics
//===----------------------------------------------------------------------===//
def int_amdgcn_s_get_waveid_in_workgroup :
GCCBuiltin<"__builtin_amdgcn_s_get_waveid_in_workgroup">,
Intrinsic<[llvm_i32_ty], [], [IntrReadMem]>;
//===----------------------------------------------------------------------===//
// Deep learning intrinsics. // Deep learning intrinsics.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// f32 %r = llvm.amdgcn.fdot2(v2f16 %a, v2f16 %b, f32 %c, i1 %clamp) // f32 %r = llvm.amdgcn.fdot2(v2f16 %a, v2f16 %b, f32 %c, i1 %clamp)
// %r = %a[0] * %b[0] + %a[1] * %b[1] + %c // %r = %a[0] * %b[0] + %a[1] * %b[1] + %c
def int_amdgcn_fdot2 : def int_amdgcn_fdot2 :
GCCBuiltin<"__builtin_amdgcn_fdot2">, GCCBuiltin<"__builtin_amdgcn_fdot2">,
Intrinsic< Intrinsic<
▲ Show 20 Lines • Show All 134 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Show First 20 Lines • Show All 119 Lines • ▼ Show 20 Linesprivate:
bool isDSOffsetLegal(SDValue Base, unsigned Offset, bool isDSOffsetLegal(SDValue Base, unsigned Offset,
unsigned OffsetBits) const; unsigned OffsetBits) const;
bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const; bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0, bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
SDValue &Offset1) const; SDValue &Offset1) const;
bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr, bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
SDValue &SOffset, SDValue &Offset, SDValue &Offen, SDValue &SOffset, SDValue &Offset, SDValue &Offen,
SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC, SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
SDValue &TFE) const; SDValue &TFE, SDValue &DLC) const;
bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr, bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
SDValue &SOffset, SDValue &Offset, SDValue &GLC, SDValue &SOffset, SDValue &Offset, SDValue &GLC,
SDValue &SLC, SDValue &TFE) const; SDValue &SLC, SDValue &TFE, SDValue &DLC) const;
bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
SDValue &VAddr, SDValue &SOffset, SDValue &Offset, SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
SDValue &SLC) const; SDValue &SLC) const;
bool SelectMUBUFScratchOffen(SDNode *Parent, bool SelectMUBUFScratchOffen(SDNode *Parent,
SDValue Addr, SDValue &RSrc, SDValue &VAddr, SDValue Addr, SDValue &RSrc, SDValue &VAddr,
SDValue &SOffset, SDValue &ImmOffset) const; SDValue &SOffset, SDValue &ImmOffset) const;
bool SelectMUBUFScratchOffset(SDNode *Parent, bool SelectMUBUFScratchOffset(SDNode *Parent,
SDValue Addr, SDValue &SRsrc, SDValue &Soffset, SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
SDValue &Offset) const; SDValue &Offset) const;
bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset, bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
SDValue &Offset, SDValue &GLC, SDValue &SLC, SDValue &Offset, SDValue &GLC, SDValue &SLC,
SDValue &TFE) const; SDValue &TFE, SDValue &DLC) const;
bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset, bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
SDValue &Offset, SDValue &SLC) const; SDValue &Offset, SDValue &SLC) const;
bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset, bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
SDValue &Offset) const; SDValue &Offset) const;
bool SelectFlatAtomic(SDValue Addr, SDValue &VAddr, bool SelectFlatAtomic(SDNode *N, SDValue Addr, SDValue &VAddr,
SDValue &Offset, SDValue &SLC) const; SDValue &Offset, SDValue &SLC) const;
bool SelectFlatAtomicSigned(SDValue Addr, SDValue &VAddr, bool SelectFlatAtomicSigned(SDNode *N, SDValue Addr, SDValue &VAddr,
SDValue &Offset, SDValue &SLC) const; SDValue &Offset, SDValue &SLC) const;
template <bool IsSigned> template <bool IsSigned>
bool SelectFlatOffset(SDValue Addr, SDValue &VAddr, bool SelectFlatOffset(SDNode *N, SDValue Addr, SDValue &VAddr,
SDValue &Offset, SDValue &SLC) const; SDValue &Offset, SDValue &SLC) const;
bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset, bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
bool &Imm) const; bool &Imm) const;
SDValue Expand32BitAddress(SDValue Addr) const; SDValue Expand32BitAddress(SDValue Addr) const;
bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset, bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
bool &Imm) const; bool &Imm) const;
bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const; bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
▲ Show 20 Lines • Show All 1,051 Lines • ▼ Show 20 Linesbool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
return true; return true;
} }
bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr, bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
SDValue &VAddr, SDValue &SOffset, SDValue &VAddr, SDValue &SOffset,
SDValue &Offset, SDValue &Offen, SDValue &Offset, SDValue &Offen,
SDValue &Idxen, SDValue &Addr64, SDValue &Idxen, SDValue &Addr64,
SDValue &GLC, SDValue &SLC, SDValue &GLC, SDValue &SLC,
SDValue &TFE) const { SDValue &TFE, SDValue &DLC) const {
// Subtarget prefers to use flat instruction // Subtarget prefers to use flat instruction
if (Subtarget->useFlatForGlobal()) if (Subtarget->useFlatForGlobal())
return false; return false;
SDLoc DL(Addr); SDLoc DL(Addr);
if (!GLC.getNode()) if (!GLC.getNode())
GLC = CurDAG->getTargetConstant(0, DL, MVT::i1); GLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
if (!SLC.getNode()) if (!SLC.getNode())
SLC = CurDAG->getTargetConstant(0, DL, MVT::i1); SLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
TFE = CurDAG->getTargetConstant(0, DL, MVT::i1); TFE = CurDAG->getTargetConstant(0, DL, MVT::i1);
DLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
Idxen = CurDAG->getTargetConstant(0, DL, MVT::i1); Idxen = CurDAG->getTargetConstant(0, DL, MVT::i1);
Offen = CurDAG->getTargetConstant(0, DL, MVT::i1); Offen = CurDAG->getTargetConstant(0, DL, MVT::i1);
Addr64 = CurDAG->getTargetConstant(0, DL, MVT::i1); Addr64 = CurDAG->getTargetConstant(0, DL, MVT::i1);
SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32); SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
ConstantSDNode *C1 = nullptr; ConstantSDNode *C1 = nullptr;
SDValue N0 = Addr; SDValue N0 = Addr;
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines SOffset =
CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32)), CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32)),
0); 0);
return true; return true;
} }
bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
SDValue &VAddr, SDValue &SOffset, SDValue &VAddr, SDValue &SOffset,
SDValue &Offset, SDValue &GLC, SDValue &Offset, SDValue &GLC,
SDValue &SLC, SDValue &TFE) const { SDValue &SLC, SDValue &TFE,
SDValue &DLC) const {
SDValue Ptr, Offen, Idxen, Addr64; SDValue Ptr, Offen, Idxen, Addr64;
// addr64 bit was removed for volcanic islands. // addr64 bit was removed for volcanic islands.
if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
return false; return false;
if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64, if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
GLC, SLC, TFE)) GLC, SLC, TFE, DLC))
return false; return false;
ConstantSDNode *C = cast<ConstantSDNode>(Addr64); ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
if (C->getSExtValue()) { if (C->getSExtValue()) {
SDLoc DL(Addr); SDLoc DL(Addr);
const SITargetLowering& Lowering = const SITargetLowering& Lowering =
*static_cast<const SITargetLowering*>(getTargetLowering()); *static_cast<const SITargetLowering*>(getTargetLowering());
SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
return true; return true;
} }
return false; return false;
} }
bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
SDValue &VAddr, SDValue &SOffset, SDValue &VAddr, SDValue &SOffset,
SDValue &Offset, SDValue &Offset,
SDValue &SLC) const { SDValue &SLC) const {
SLC = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i1); SLC = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i1);
SDValue GLC, TFE; SDValue GLC, TFE, DLC;
return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE); return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE, DLC);
} }
static bool isStackPtrRelative(const MachinePointerInfo &PtrInfo) { static bool isStackPtrRelative(const MachinePointerInfo &PtrInfo) {
auto PSV = PtrInfo.V.dyn_cast<const PseudoSourceValue *>(); auto PSV = PtrInfo.V.dyn_cast<const PseudoSourceValue *>();
return PSV && PSV->isStack(); return PSV && PSV->isStack();
} }
std::pair<SDValue, SDValue> AMDGPUDAGToDAGISel::foldFrameIndex(SDValue N) const { std::pair<SDValue, SDValue> AMDGPUDAGToDAGISel::foldFrameIndex(SDValue N) const {
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Linesbool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffset(SDNode *Parent,
Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16); Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16);
return true; return true;
} }
bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
SDValue &SOffset, SDValue &Offset, SDValue &SOffset, SDValue &Offset,
SDValue &GLC, SDValue &SLC, SDValue &GLC, SDValue &SLC,
SDValue &TFE) const { SDValue &TFE, SDValue &DLC) const {
SDValue Ptr, VAddr, Offen, Idxen, Addr64; SDValue Ptr, VAddr, Offen, Idxen, Addr64;
const SIInstrInfo *TII = const SIInstrInfo *TII =
static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo()); static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64, if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
GLC, SLC, TFE)) GLC, SLC, TFE, DLC))
return false; return false;
if (!cast<ConstantSDNode>(Offen)->getSExtValue() && if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
!cast<ConstantSDNode>(Idxen)->getSExtValue() && !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
!cast<ConstantSDNode>(Addr64)->getSExtValue()) { !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
APInt::getAllOnesValue(32).getZExtValue(); // Size APInt::getAllOnesValue(32).getZExtValue(); // Size
SDLoc DL(Addr); SDLoc DL(Addr);
const SITargetLowering& Lowering = const SITargetLowering& Lowering =
*static_cast<const SITargetLowering*>(getTargetLowering()); *static_cast<const SITargetLowering*>(getTargetLowering());
SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
return true; return true;
} }
return false; return false;
} }
bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
SDValue &Soffset, SDValue &Offset SDValue &Soffset, SDValue &Offset
) const { ) const {
SDValue GLC, SLC, TFE; SDValue GLC, SLC, TFE, DLC;
return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE); return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE, DLC);
} }
bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
SDValue &Soffset, SDValue &Offset, SDValue &Soffset, SDValue &Offset,
SDValue &SLC) const { SDValue &SLC) const {
SDValue GLC, TFE; SDValue GLC, TFE, DLC;
return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE); return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE, DLC);
} }
template <bool IsSigned> template <bool IsSigned>
bool AMDGPUDAGToDAGISel::SelectFlatOffset(SDValue Addr, bool AMDGPUDAGToDAGISel::SelectFlatOffset(SDNode *N,
SDValue Addr,
SDValue &VAddr, SDValue &VAddr,
SDValue &Offset, SDValue &Offset,
SDValue &SLC) const { SDValue &SLC) const {
int64_t OffsetVal = 0; return static_cast<const SITargetLowering*>(getTargetLowering())->
SelectFlatOffset(IsSigned, *CurDAG, N, Addr, VAddr, Offset, SLC);
if (Subtarget->hasFlatInstOffsets() &&
CurDAG->isBaseWithConstantOffset(Addr)) {
SDValue N0 = Addr.getOperand(0);
SDValue N1 = Addr.getOperand(1);
int64_t COffsetVal = cast<ConstantSDNode>(N1)->getSExtValue();
if ((IsSigned && isInt<13>(COffsetVal)) ||
(!IsSigned && isUInt<12>(COffsetVal))) {
Addr = N0;
OffsetVal = COffsetVal;
}
} }
VAddr = Addr; bool AMDGPUDAGToDAGISel::SelectFlatAtomic(SDNode *N,
Offset = CurDAG->getTargetConstant(OffsetVal, SDLoc(), MVT::i16); SDValue Addr,
SLC = CurDAG->getTargetConstant(0, SDLoc(), MVT::i1);
return true;
}
bool AMDGPUDAGToDAGISel::SelectFlatAtomic(SDValue Addr,
SDValue &VAddr, SDValue &VAddr,
SDValue &Offset, SDValue &Offset,
SDValue &SLC) const { SDValue &SLC) const {
return SelectFlatOffset<false>(Addr, VAddr, Offset, SLC); return SelectFlatOffset<false>(N, Addr, VAddr, Offset, SLC);
} }
bool AMDGPUDAGToDAGISel::SelectFlatAtomicSigned(SDValue Addr, bool AMDGPUDAGToDAGISel::SelectFlatAtomicSigned(SDNode *N,
SDValue Addr,
SDValue &VAddr, SDValue &VAddr,
SDValue &Offset, SDValue &Offset,
SDValue &SLC) const { SDValue &SLC) const {
return SelectFlatOffset<true>(Addr, VAddr, Offset, SLC); return SelectFlatOffset<true>(N, Addr, VAddr, Offset, SLC);
} }
bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode, bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
SDValue &Offset, bool &Imm) const { SDValue &Offset, bool &Imm) const {
// FIXME: Handle non-constant offsets. // FIXME: Handle non-constant offsets.
ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode); ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode);
if (!C) if (!C)
▲ Show 20 Lines • Show All 954 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h

Show First 20 Lines • Show All 317 Lines • ▼ Show 20 Linespublic:
uint32_t getImplicitParameterOffset(const MachineFunction &MF, uint32_t getImplicitParameterOffset(const MachineFunction &MF,
const ImplicitParameter Param) const; const ImplicitParameter Param) const;
MVT getFenceOperandTy(const DataLayout &DL) const override { MVT getFenceOperandTy(const DataLayout &DL) const override {
return MVT::i32; return MVT::i32;
} }
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override; AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
bool SelectFlatOffset(bool IsSigned, SelectionDAG &DAG, SDNode *N,
SDValue Addr, SDValue &VAddr, SDValue &Offset,
SDValue &SLC) const;
}; };
namespace AMDGPUISD { namespace AMDGPUISD {
enum NodeType : unsigned { enum NodeType : unsigned {
// AMDIL ISD Opcodes // AMDIL ISD Opcodes
FIRST_NUMBER = ISD::BUILTIN_OP_END, FIRST_NUMBER = ISD::BUILTIN_OP_END,
UMUL, // 32bit unsigned multiplication UMUL, // 32bit unsigned multiplication
▲ Show 20 Lines • Show All 206 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 2,880 Lines • ▼ Show 20 Lines if ((Size == 1 || Size == 2 || Size == 4) && !VT.isVector())
return false; return false;
if (Size == 3 || (Size > 4 && (Size % 4 != 0))) if (Size == 3 || (Size > 4 && (Size % 4 != 0)))
return false; return false;
return true; return true;
} }
// Find a load or store from corresponding pattern root.
// Roots may be build_vector, bitconvert or their combinations.
static MemSDNode* findMemSDNode(SDNode *N) {
N = AMDGPUTargetLowering::stripBitcast(SDValue(N,0)).getNode();
if (MemSDNode *MN = dyn_cast<MemSDNode>(N))
return MN;
assert(isa<BuildVectorSDNode>(N));
for (SDValue V : N->op_values())
if (MemSDNode *MN =
dyn_cast<MemSDNode>(AMDGPUTargetLowering::stripBitcast(V)))
return MN;
llvm_unreachable("cannot find MemSDNode in the pattern!");
}
bool AMDGPUTargetLowering::SelectFlatOffset(bool IsSigned,
SelectionDAG &DAG,
SDNode *N,
SDValue Addr,
SDValue &VAddr,
SDValue &Offset,
SDValue &SLC) const {
const GCNSubtarget &ST =
DAG.getMachineFunction().getSubtarget<GCNSubtarget>();
int64_t OffsetVal = 0;
if (ST.hasFlatInstOffsets() &&
(!ST.hasFlatSegmentOffsetBug() ||
findMemSDNode(N)->getAddressSpace() != AMDGPUAS::FLAT_ADDRESS) &&
DAG.isBaseWithConstantOffset(Addr)) {
SDValue N0 = Addr.getOperand(0);
SDValue N1 = Addr.getOperand(1);
int64_t COffsetVal = cast<ConstantSDNode>(N1)->getSExtValue();
if (ST.getGeneration() >= AMDGPUSubtarget::GFX10) {
if ((IsSigned && isInt<12>(COffsetVal)) ||
(!IsSigned && isUInt<11>(COffsetVal))) {
Addr = N0;
OffsetVal = COffsetVal;
}
} else {
if ((IsSigned && isInt<13>(COffsetVal)) ||
(!IsSigned && isUInt<12>(COffsetVal))) {
Addr = N0;
OffsetVal = COffsetVal;
}
}
}
VAddr = Addr;
Offset = DAG.getTargetConstant(OffsetVal, SDLoc(), MVT::i16);
SLC = DAG.getTargetConstant(0, SDLoc(), MVT::i1);
return true;
}
// Replace load of an illegal type with a store of a bitcast to a friendlier // Replace load of an illegal type with a store of a bitcast to a friendlier
// type. // type.
SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N, SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
DAGCombinerInfo &DCI) const { DAGCombinerInfo &DCI) const {
if (!DCI.isBeforeLegalize()) if (!DCI.isBeforeLegalize())
return SDValue(); return SDValue();
LoadSDNode *LN = cast<LoadSDNode>(N); LoadSDNode *LN = cast<LoadSDNode>(N);
▲ Show 20 Lines • Show All 1,786 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Show First 20 Lines • Show All 350 Lines • ▼ Show 20 Lines case 128:
break; break;
} }
MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode)) MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode))
.add(I.getOperand(1)) .add(I.getOperand(1))
.add(I.getOperand(0)) .add(I.getOperand(0))
.addImm(0) // offset .addImm(0) // offset
.addImm(0) // glc .addImm(0) // glc
.addImm(0); // slc .addImm(0) // slc
.addImm(0); // dlc
// Now that we selected an opcode, we need to constrain the register // Now that we selected an opcode, we need to constrain the register
// operands to use appropriate classes. // operands to use appropriate classes.
bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI); bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
I.eraseFromParent(); I.eraseFromParent();
return Ret; return Ret;
▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines case 64:
break; break;
} }
MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode)) MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode))
.add(I.getOperand(0)) .add(I.getOperand(0))
.addReg(PtrReg) .addReg(PtrReg)
.addImm(0) // offset .addImm(0) // offset
.addImm(0) // glc .addImm(0) // glc
.addImm(0); // slc .addImm(0) // slc
.addImm(0); // dlc
bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI); bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
I.eraseFromParent(); I.eraseFromParent();
return Ret; return Ret;
} }
bool AMDGPUInstructionSelector::select(MachineInstr &I, bool AMDGPUInstructionSelector::select(MachineInstr &I,
CodeGenCoverage &CoverageInfo) const { CodeGenCoverage &CoverageInfo) const {
▲ Show 20 Lines • Show All 162 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Show First 20 Lines • Show All 133 Lines • ▼ Show 20 Lines enum ImmTy {
ImmTyLDS, ImmTyLDS,
ImmTyOffen, ImmTyOffen,
ImmTyIdxen, ImmTyIdxen,
ImmTyAddr64, ImmTyAddr64,
ImmTyOffset, ImmTyOffset,
ImmTyInstOffset, ImmTyInstOffset,
ImmTyOffset0, ImmTyOffset0,
ImmTyOffset1, ImmTyOffset1,
ImmTyDLC,
ImmTyGLC, ImmTyGLC,
ImmTySLC, ImmTySLC,
ImmTyTFE, ImmTyTFE,
ImmTyD16, ImmTyD16,
ImmTyClampSI, ImmTyClampSI,
ImmTyOModSI, ImmTyOModSI,
ImmTyDppCtrl, ImmTyDppCtrl,
ImmTyDppRowMask, ImmTyDppRowMask,
▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Linespublic:
bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); } bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); }
bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); } bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); }
bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); } bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); }
bool isOffsetU12() const { return (isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset)) && isUInt<12>(getImm()); } bool isOffsetU12() const { return (isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset)) && isUInt<12>(getImm()); }
bool isOffsetS13() const { return (isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset)) && isInt<13>(getImm()); } bool isOffsetS13() const { return (isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset)) && isInt<13>(getImm()); }
bool isGDS() const { return isImmTy(ImmTyGDS); } bool isGDS() const { return isImmTy(ImmTyGDS); }
bool isLDS() const { return isImmTy(ImmTyLDS); } bool isLDS() const { return isImmTy(ImmTyLDS); }
bool isDLC() const { return isImmTy(ImmTyDLC); }
bool isGLC() const { return isImmTy(ImmTyGLC); } bool isGLC() const { return isImmTy(ImmTyGLC); }
bool isSLC() const { return isImmTy(ImmTySLC); } bool isSLC() const { return isImmTy(ImmTySLC); }
bool isTFE() const { return isImmTy(ImmTyTFE); } bool isTFE() const { return isImmTy(ImmTyTFE); }
bool isD16() const { return isImmTy(ImmTyD16); } bool isD16() const { return isImmTy(ImmTyD16); }
bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<8>(getImm()); } bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<8>(getImm()); }
bool isBankMask() const { return isImmTy(ImmTyDppBankMask); } bool isBankMask() const { return isImmTy(ImmTyDppBankMask); }
bool isRowMask() const { return isImmTy(ImmTyDppRowMask); } bool isRowMask() const { return isImmTy(ImmTyDppRowMask); }
bool isBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); } bool isBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); }
▲ Show 20 Lines • Show All 346 Lines • ▼ Show 20 Lines static void printImmTy(raw_ostream& OS, ImmTy Type) {
case ImmTyLDS: OS << "LDS"; break; case ImmTyLDS: OS << "LDS"; break;
case ImmTyOffen: OS << "Offen"; break; case ImmTyOffen: OS << "Offen"; break;
case ImmTyIdxen: OS << "Idxen"; break; case ImmTyIdxen: OS << "Idxen"; break;
case ImmTyAddr64: OS << "Addr64"; break; case ImmTyAddr64: OS << "Addr64"; break;
case ImmTyOffset: OS << "Offset"; break; case ImmTyOffset: OS << "Offset"; break;
case ImmTyInstOffset: OS << "InstOffset"; break; case ImmTyInstOffset: OS << "InstOffset"; break;
case ImmTyOffset0: OS << "Offset0"; break; case ImmTyOffset0: OS << "Offset0"; break;
case ImmTyOffset1: OS << "Offset1"; break; case ImmTyOffset1: OS << "Offset1"; break;
case ImmTyDLC: OS << "DLC"; break;
case ImmTyGLC: OS << "GLC"; break; case ImmTyGLC: OS << "GLC"; break;
case ImmTySLC: OS << "SLC"; break; case ImmTySLC: OS << "SLC"; break;
case ImmTyTFE: OS << "TFE"; break; case ImmTyTFE: OS << "TFE"; break;
case ImmTyD16: OS << "D16"; break; case ImmTyD16: OS << "D16"; break;
case ImmTyFORMAT: OS << "FORMAT"; break; case ImmTyFORMAT: OS << "FORMAT"; break;
case ImmTyClampSI: OS << "ClampSI"; break; case ImmTyClampSI: OS << "ClampSI"; break;
case ImmTyOModSI: OS << "OModSI"; break; case ImmTyOModSI: OS << "OModSI"; break;
case ImmTyDppCtrl: OS << "DppCtrl"; break; case ImmTyDppCtrl: OS << "DppCtrl"; break;
▲ Show 20 Lines • Show All 492 Lines • ▼ Show 20 Linespublic:
int64_t parseGPRIdxMacro(); int64_t parseGPRIdxMacro();
void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false); } void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false); }
void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, false); } void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, false); }
void cvtMubufAtomicReturn(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, true); } void cvtMubufAtomicReturn(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, true); }
void cvtMubufLds(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false, true); } void cvtMubufLds(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false, true); }
void cvtMtbuf(MCInst &Inst, const OperandVector &Operands); void cvtMtbuf(MCInst &Inst, const OperandVector &Operands);
AMDGPUOperand::Ptr defaultDLC() const;
AMDGPUOperand::Ptr defaultGLC() const; AMDGPUOperand::Ptr defaultGLC() const;
AMDGPUOperand::Ptr defaultSLC() const; AMDGPUOperand::Ptr defaultSLC() const;
AMDGPUOperand::Ptr defaultSMRDOffset8() const; AMDGPUOperand::Ptr defaultSMRDOffset8() const;
AMDGPUOperand::Ptr defaultSMRDOffset20() const; AMDGPUOperand::Ptr defaultSMRDOffset20() const;
AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const; AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const;
AMDGPUOperand::Ptr defaultOffsetU12() const; AMDGPUOperand::Ptr defaultOffsetU12() const;
AMDGPUOperand::Ptr defaultOffsetS13() const; AMDGPUOperand::Ptr defaultOffsetS13() const;
▲ Show 20 Lines • Show All 1,103 Lines • ▼ Show 20 Lines if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi ||
auto OpNum = auto OpNum =
AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel); AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel);
const auto &Op = Inst.getOperand(OpNum); const auto &Op = Inst.getOperand(OpNum);
if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) { if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) {
return Match_InvalidOperand; return Match_InvalidOperand;
} }
} }
if ((TSFlags & SIInstrFlags::FLAT) && !hasFlatOffsets()) { if (TSFlags & SIInstrFlags::FLAT) {
// FIXME: Produces error without correct column reported. // FIXME: Produces error without correct column reported.
auto OpNum = auto Opcode = Inst.getOpcode();
AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::offset); auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);
const auto &Op = Inst.getOperand(OpNum); const auto &Op = Inst.getOperand(OpNum);
if (Op.getImm() != 0) if (!hasFlatOffsets() && Op.getImm() != 0)
return Match_InvalidOperand;
// GFX10: Address offset is 12-bit signed byte offset. Must be positive for
// FLAT segment. For FLAT segment MSB is ignored and forced to zero.
if (isGFX10()) {
if (TSFlags & SIInstrFlags::IsNonFlatSeg) {
if (!isInt<12>(Op.getImm()))
return Match_InvalidOperand; return Match_InvalidOperand;
} else {
if (!isUInt<11>(Op.getImm()))
return Match_InvalidOperand;
}
}
} }
return Match_Success; return Match_Success;
} }
// What asm variants we should check // What asm variants we should check
ArrayRef<unsigned> AMDGPUAsmParser::getMatchedVariants() const { ArrayRef<unsigned> AMDGPUAsmParser::getMatchedVariants() const {
if (getForcedEncodingSize() == 32) { if (getForcedEncodingSize() == 32) {
▲ Show 20 Lines • Show All 1,561 Lines • ▼ Show 20 Lines switch(getLexer().getKind()) {
} }
break; break;
} }
default: default:
return MatchOperand_NoMatch; return MatchOperand_NoMatch;
} }
} }
if (!isGFX10() && ImmTy == AMDGPUOperand::ImmTyDLC)
return MatchOperand_ParseFail;
Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy)); Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy));
return MatchOperand_Success; return MatchOperand_Success;
} }
static void addOptionalImmOperand( static void addOptionalImmOperand(
MCInst& Inst, const OperandVector& Operands, MCInst& Inst, const OperandVector& Operands,
AMDGPUAsmParser::OptionalImmIndexMap& OptionalIdx, AMDGPUAsmParser::OptionalImmIndexMap& OptionalIdx,
AMDGPUOperand::ImmTy ImmT, AMDGPUOperand::ImmTy ImmT,
▲ Show 20 Lines • Show All 1,198 Lines • ▼ Show 20 Lines case AsmToken::Identifier:
return MatchOperand_Success; return MatchOperand_Success;
} }
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// mubuf // mubuf
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDLC() const {
return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDLC);
}
AMDGPUOperand::Ptr AMDGPUAsmParser::defaultGLC() const { AMDGPUOperand::Ptr AMDGPUAsmParser::defaultGLC() const {
return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyGLC); return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyGLC);
} }
AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSLC() const { AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSLC() const {
return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTySLC); return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTySLC);
} }
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Linesvoid AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
if (!IsAtomic) { // glc is hard-coded. if (!IsAtomic) { // glc is hard-coded.
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
} }
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
if (!IsLdsOpcode) { // tfe is not legal with lds opcodes if (!IsLdsOpcode) { // tfe is not legal with lds opcodes
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
} }
if (isGFX10())
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDLC);
} }
void AMDGPUAsmParser::cvtMtbuf(MCInst &Inst, const OperandVector &Operands) { void AMDGPUAsmParser::cvtMtbuf(MCInst &Inst, const OperandVector &Operands) {
OptionalImmIndexMap OptionalIdx; OptionalImmIndexMap OptionalIdx;
for (unsigned i = 1, e = Operands.size(); i != e; ++i) { for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
Show All 21 Linesvoid AMDGPUAsmParser::cvtMtbuf(MCInst &Inst, const OperandVector &Operands) {
} }
addOptionalImmOperand(Inst, Operands, OptionalIdx, addOptionalImmOperand(Inst, Operands, OptionalIdx,
AMDGPUOperand::ImmTyOffset); AMDGPUOperand::ImmTyOffset);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyFORMAT); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyFORMAT);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
if (isGFX10())
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDLC);
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// mimg // mimg
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands, void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands,
bool IsAtomic) { bool IsAtomic) {
Show All 19 Lines if (Op.isReg()) {
Op.addRegOperands(Inst, 1); Op.addRegOperands(Inst, 1);
} else if (Op.isImmModifier()) { } else if (Op.isImmModifier()) {
OptionalIdx[Op.getImmTy()] = I; OptionalIdx[Op.getImmTy()] = I;
} else { } else {
llvm_unreachable("unexpected operand type"); llvm_unreachable("unexpected operand type");
} }
} }
bool IsGFX10 = isGFX10();
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
if (IsGFX10)
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDLC);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128A16); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128A16);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyD16); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyD16);
} }
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Linesstatic const OptionalOperand AMDGPUOptionalOperandTable[] = {
{"idxen", AMDGPUOperand::ImmTyIdxen, true, nullptr}, {"idxen", AMDGPUOperand::ImmTyIdxen, true, nullptr},
{"addr64", AMDGPUOperand::ImmTyAddr64, true, nullptr}, {"addr64", AMDGPUOperand::ImmTyAddr64, true, nullptr},
{"offset0", AMDGPUOperand::ImmTyOffset0, false, nullptr}, {"offset0", AMDGPUOperand::ImmTyOffset0, false, nullptr},
{"offset1", AMDGPUOperand::ImmTyOffset1, false, nullptr}, {"offset1", AMDGPUOperand::ImmTyOffset1, false, nullptr},
{"gds", AMDGPUOperand::ImmTyGDS, true, nullptr}, {"gds", AMDGPUOperand::ImmTyGDS, true, nullptr},
{"lds", AMDGPUOperand::ImmTyLDS, true, nullptr}, {"lds", AMDGPUOperand::ImmTyLDS, true, nullptr},
{"offset", AMDGPUOperand::ImmTyOffset, false, nullptr}, {"offset", AMDGPUOperand::ImmTyOffset, false, nullptr},
{"inst_offset", AMDGPUOperand::ImmTyInstOffset, false, nullptr}, {"inst_offset", AMDGPUOperand::ImmTyInstOffset, false, nullptr},
{"dlc", AMDGPUOperand::ImmTyDLC, true, nullptr},
{"dfmt", AMDGPUOperand::ImmTyFORMAT, false, nullptr}, {"dfmt", AMDGPUOperand::ImmTyFORMAT, false, nullptr},
{"glc", AMDGPUOperand::ImmTyGLC, true, nullptr}, {"glc", AMDGPUOperand::ImmTyGLC, true, nullptr},
{"slc", AMDGPUOperand::ImmTySLC, true, nullptr}, {"slc", AMDGPUOperand::ImmTySLC, true, nullptr},
{"tfe", AMDGPUOperand::ImmTyTFE, true, nullptr}, {"tfe", AMDGPUOperand::ImmTyTFE, true, nullptr},
{"d16", AMDGPUOperand::ImmTyD16, true, nullptr}, {"d16", AMDGPUOperand::ImmTyD16, true, nullptr},
{"high", AMDGPUOperand::ImmTyHigh, true, nullptr}, {"high", AMDGPUOperand::ImmTyHigh, true, nullptr},
{"clamp", AMDGPUOperand::ImmTyClampSI, true, nullptr}, {"clamp", AMDGPUOperand::ImmTyClampSI, true, nullptr},
{"omod", AMDGPUOperand::ImmTyOModSI, false, ConvertOmodMul}, {"omod", AMDGPUOperand::ImmTyOModSI, false, ConvertOmodMul},
▲ Show 20 Lines • Show All 212 Lines • ▼ Show 20 Linesvoid AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) { if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) {
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
} }
if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) { if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) {
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
} }
// Special case v_mac_{f16, f32} and v_fmac_f32 (gfx906): // Special case v_mac_{f16, f32} and v_fmac_{f16, f32} (gfx906/gfx10+):
// it has src2 register operand that is tied to dst operand // it has src2 register operand that is tied to dst operand
// we don't allow modifiers for this operand in assembler so src2_modifiers // we don't allow modifiers for this operand in assembler so src2_modifiers
// should be 0. // should be 0.
if (Opc == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || if (Opc == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
Opc == AMDGPU::V_MAC_F32_e64_gfx10 || Opc == AMDGPU::V_MAC_F32_e64_gfx10 ||
Opc == AMDGPU::V_MAC_F32_e64_vi || Opc == AMDGPU::V_MAC_F32_e64_vi ||
Opc == AMDGPU::V_MAC_F16_e64_vi || Opc == AMDGPU::V_MAC_F16_e64_vi ||
Opc == AMDGPU::V_FMAC_F32_e64_gfx10 || Opc == AMDGPU::V_FMAC_F32_e64_gfx10 ||
▲ Show 20 Lines • Show All 433 Lines • ▼ Show 20 Lines case SIInstrFlags::VOP2:
} }
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, DstUnused::UNUSED_PRESERVE); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, DstUnused::UNUSED_PRESERVE);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD);
break; break;
case SIInstrFlags::VOPC: case SIInstrFlags::VOPC:
if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::clamp) != -1)
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD);
break; break;
default: default:
llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed"); llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");
} }
} }
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td

//===-- BUFInstructions.td - Buffer Instruction Defintions ----------------===// //===-- BUFInstructions.td - Buffer Instruction Defintions ----------------===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">; def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">; def MUBUFAddr64 : ComplexPattern<i64, 8, "SelectMUBUFAddr64">;
def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">; def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
def MUBUFScratchOffen : ComplexPattern<i64, 4, "SelectMUBUFScratchOffen", [], [SDNPWantParent]>; def MUBUFScratchOffen : ComplexPattern<i64, 4, "SelectMUBUFScratchOffen", [], [SDNPWantParent]>;
def MUBUFScratchOffset : ComplexPattern<i64, 3, "SelectMUBUFScratchOffset", [], [SDNPWantParent], 20>; def MUBUFScratchOffset : ComplexPattern<i64, 3, "SelectMUBUFScratchOffset", [], [SDNPWantParent], 20>;
def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">; def MUBUFOffset : ComplexPattern<i64, 7, "SelectMUBUFOffset">;
def MUBUFOffsetNoGLC : ComplexPattern<i64, 3, "SelectMUBUFOffset">; def MUBUFOffsetNoGLC : ComplexPattern<i64, 3, "SelectMUBUFOffset">;
def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">; def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
class MubufLoad <SDPatternOperator op> : PatFrag < class MubufLoad <SDPatternOperator op> : PatFrag <
(ops node:$ptr), (op node:$ptr), [{ (ops node:$ptr), (op node:$ptr), [{
auto const AS = cast<MemSDNode>(N)->getAddressSpace(); auto const AS = cast<MemSDNode>(N)->getAddressSpace();
return AS == AMDGPUAS::GLOBAL_ADDRESS || return AS == AMDGPUAS::GLOBAL_ADDRESS ||
AS == AMDGPUAS::CONSTANT_ADDRESS; AS == AMDGPUAS::CONSTANT_ADDRESS;
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Linesclass MTBUF_Pseudo <string opName, dag outs, dag ins,
let AsmMatchConverter = "cvtMtbuf"; let AsmMatchConverter = "cvtMtbuf";
bits<1> offen = 0; bits<1> offen = 0;
bits<1> idxen = 0; bits<1> idxen = 0;
bits<1> addr64 = 0; bits<1> addr64 = 0;
bits<1> has_vdata = 1; bits<1> has_vdata = 1;
bits<1> has_vaddr = 1; bits<1> has_vaddr = 1;
bits<1> has_glc = 1; bits<1> has_glc = 1;
bits<1> has_dlc = 1;
bits<1> glc_value = 0; // the value for glc if no such operand bits<1> glc_value = 0; // the value for glc if no such operand
bits<1> dlc_value = 0; // the value for dlc if no such operand
bits<1> has_srsrc = 1; bits<1> has_srsrc = 1;
bits<1> has_soffset = 1; bits<1> has_soffset = 1;
bits<1> has_offset = 1; bits<1> has_offset = 1;
bits<1> has_slc = 1; bits<1> has_slc = 1;
bits<1> has_tfe = 1; bits<1> has_tfe = 1;
} }
class MTBUF_Real <MTBUF_Pseudo ps> : class MTBUF_Real <MTBUF_Pseudo ps> :
InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> { InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> {
let isPseudo = 0; let isPseudo = 0;
let isCodeGenOnly = 0; let isCodeGenOnly = 0;
// copy relevant pseudo op flags // copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate; let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter; let AsmMatchConverter = ps.AsmMatchConverter;
let Constraints = ps.Constraints; let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding; let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags; let TSFlags = ps.TSFlags;
bits<12> offset; bits<12> offset;
bits<1> glc; bits<1> glc;
bits<1> dlc;
bits<7> format; bits<7> format;
bits<8> vaddr; bits<8> vaddr;
bits<8> vdata; bits<8> vdata;
bits<7> srsrc; bits<7> srsrc;
bits<1> slc; bits<1> slc;
bits<1> tfe; bits<1> tfe;
bits<8> soffset; bits<8> soffset;
bits<4> dfmt = format{3-0}; bits<4> dfmt = format{3-0};
bits<3> nfmt = format{6-4}; bits<3> nfmt = format{6-4};
} }
class getMTBUFInsDA<list<RegisterClass> vdataList, class getMTBUFInsDA<list<RegisterClass> vdataList,
list<RegisterClass> vaddrList=[]> { list<RegisterClass> vaddrList=[]> {
RegisterClass vdataClass = !if(!empty(vdataList), ?, !head(vdataList)); RegisterClass vdataClass = !if(!empty(vdataList), ?, !head(vdataList));
RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList)); RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
dag InsNoData = !if(!empty(vaddrList), dag InsNoData = !if(!empty(vaddrList),
(ins SReg_128:$srsrc, SCSrc_b32:$soffset, (ins SReg_128:$srsrc, SCSrc_b32:$soffset,
offset:$offset, FORMAT:$format, GLC:$glc, SLC:$slc, TFE:$tfe), offset:$offset, FORMAT:$format, GLC:$glc, SLC:$slc, TFE:$tfe, DLC:$dlc),
(ins vaddrClass:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset, (ins vaddrClass:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset,
offset:$offset, FORMAT:$format, GLC:$glc, SLC:$slc, TFE:$tfe) offset:$offset, FORMAT:$format, GLC:$glc, SLC:$slc, TFE:$tfe, DLC:$dlc)
); );
dag InsData = !if(!empty(vaddrList), dag InsData = !if(!empty(vaddrList),
(ins vdataClass:$vdata, SReg_128:$srsrc, (ins vdataClass:$vdata, SReg_128:$srsrc,
SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, GLC:$glc, SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, GLC:$glc,
SLC:$slc, TFE:$tfe), SLC:$slc, TFE:$tfe, DLC:$dlc),
(ins vdataClass:$vdata, vaddrClass:$vaddr, SReg_128:$srsrc, (ins vdataClass:$vdata, vaddrClass:$vaddr, SReg_128:$srsrc,
SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, GLC:$glc, SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, GLC:$glc,
SLC:$slc, TFE:$tfe) SLC:$slc, TFE:$tfe, DLC:$dlc)
); );
dag ret = !if(!empty(vdataList), InsNoData, InsData); dag ret = !if(!empty(vdataList), InsNoData, InsData);
} }
class getMTBUFIns<int addrKind, list<RegisterClass> vdataList=[]> { class getMTBUFIns<int addrKind, list<RegisterClass> vdataList=[]> {
dag ret = dag ret =
!if(!eq(addrKind, BUFAddrKind.Offset), getMTBUFInsDA<vdataList>.ret, !if(!eq(addrKind, BUFAddrKind.Offset), getMTBUFInsDA<vdataList>.ret,
!if(!eq(addrKind, BUFAddrKind.OffEn), getMTBUFInsDA<vdataList, [VGPR_32]>.ret, !if(!eq(addrKind, BUFAddrKind.OffEn), getMTBUFInsDA<vdataList, [VGPR_32]>.ret,
Show All 34 Linesclass MTBUF_Load_Pseudo <string opName,
int addrKind, int addrKind,
RegisterClass vdataClass, RegisterClass vdataClass,
list<dag> pattern=[], list<dag> pattern=[],
// Workaround bug bz30254 // Workaround bug bz30254
int addrKindCopy = addrKind> int addrKindCopy = addrKind>
: MTBUF_Pseudo<opName, : MTBUF_Pseudo<opName,
(outs vdataClass:$vdata), (outs vdataClass:$vdata),
getMTBUFIns<addrKindCopy>.ret, getMTBUFIns<addrKindCopy>.ret,
" $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe", " $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe$dlc",
pattern>, pattern>,
MTBUF_SetupAddr<addrKindCopy> { MTBUF_SetupAddr<addrKindCopy> {
let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret; let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
let mayLoad = 1; let mayLoad = 1;
let mayStore = 0; let mayStore = 0;
} }
multiclass MTBUF_Pseudo_Loads<string opName, RegisterClass vdataClass, multiclass MTBUF_Pseudo_Loads<string opName, RegisterClass vdataClass,
ValueType load_vt = i32, ValueType load_vt = i32,
SDPatternOperator ld = null_frag> { SDPatternOperator ld = null_frag> {
def _OFFSET : MTBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, def _OFFSET : MTBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
[(set load_vt:$vdata, [(set load_vt:$vdata,
(ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i8:$format, (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i8:$format,
i1:$glc, i1:$slc, i1:$tfe)))]>, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc)))]>,
MTBUFAddr64Table<0, NAME>; MTBUFAddr64Table<0, NAME>;
def _ADDR64 : MTBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, vdataClass, def _ADDR64 : MTBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
[(set load_vt:$vdata, [(set load_vt:$vdata,
(ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset,
i8:$format, i1:$glc, i1:$slc, i1:$tfe)))]>, i8:$format, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc)))]>,
MTBUFAddr64Table<1, NAME>; MTBUFAddr64Table<1, NAME>;
def _OFFEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>; def _OFFEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
def _IDXEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>; def _IDXEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
def _BOTHEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>; def _BOTHEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
let DisableWQM = 1 in { let DisableWQM = 1 in {
def _OFFSET_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass>; def _OFFSET_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass>;
def _OFFEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>; def _OFFEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
def _IDXEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>; def _IDXEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
def _BOTHEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>; def _BOTHEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
} }
} }
class MTBUF_Store_Pseudo <string opName, class MTBUF_Store_Pseudo <string opName,
int addrKind, int addrKind,
RegisterClass vdataClass, RegisterClass vdataClass,
list<dag> pattern=[], list<dag> pattern=[],
// Workaround bug bz30254 // Workaround bug bz30254
int addrKindCopy = addrKind, int addrKindCopy = addrKind,
RegisterClass vdataClassCopy = vdataClass> RegisterClass vdataClassCopy = vdataClass>
: MTBUF_Pseudo<opName, : MTBUF_Pseudo<opName,
(outs), (outs),
getMTBUFIns<addrKindCopy, [vdataClassCopy]>.ret, getMTBUFIns<addrKindCopy, [vdataClassCopy]>.ret,
" $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe", " $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe$dlc",
pattern>, pattern>,
MTBUF_SetupAddr<addrKindCopy> { MTBUF_SetupAddr<addrKindCopy> {
let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret; let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
let mayLoad = 0; let mayLoad = 0;
let mayStore = 1; let mayStore = 1;
} }
multiclass MTBUF_Pseudo_Stores<string opName, RegisterClass vdataClass, multiclass MTBUF_Pseudo_Stores<string opName, RegisterClass vdataClass,
ValueType store_vt = i32, ValueType store_vt = i32,
SDPatternOperator st = null_frag> { SDPatternOperator st = null_frag> {
def _OFFSET : MTBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass, def _OFFSET : MTBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
[(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset, [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
i16:$offset, i8:$format, i1:$glc, i16:$offset, i8:$format, i1:$glc,
i1:$slc, i1:$tfe))]>, i1:$slc, i1:$tfe, i1:$dlc))]>,
MTBUFAddr64Table<0, NAME>; MTBUFAddr64Table<0, NAME>;
def _ADDR64 : MTBUF_Store_Pseudo <opName, BUFAddrKind.Addr64, vdataClass, def _ADDR64 : MTBUF_Store_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
[(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, [(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
i16:$offset, i8:$format, i1:$glc, i16:$offset, i8:$format, i1:$glc,
i1:$slc, i1:$tfe))]>, i1:$slc, i1:$tfe, i1:$dlc))]>,
MTBUFAddr64Table<1, NAME>; MTBUFAddr64Table<1, NAME>;
def _OFFEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>; def _OFFEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
def _IDXEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>; def _IDXEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
def _BOTHEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>; def _BOTHEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
let DisableWQM = 1 in { let DisableWQM = 1 in {
def _OFFSET_exact : MTBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass>; def _OFFSET_exact : MTBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass>;
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesclass MUBUF_Pseudo <string opName, dag outs, dag ins,
bits<1> offen = 0; bits<1> offen = 0;
bits<1> idxen = 0; bits<1> idxen = 0;
bits<1> addr64 = 0; bits<1> addr64 = 0;
bits<1> lds = 0; bits<1> lds = 0;
bits<1> has_vdata = 1; bits<1> has_vdata = 1;
bits<1> has_vaddr = 1; bits<1> has_vaddr = 1;
bits<1> has_glc = 1; bits<1> has_glc = 1;
bits<1> has_dlc = 1;
bits<1> glc_value = 0; // the value for glc if no such operand bits<1> glc_value = 0; // the value for glc if no such operand
bits<1> dlc_value = 0; // the value for dlc if no such operand
bits<1> has_srsrc = 1; bits<1> has_srsrc = 1;
bits<1> has_soffset = 1; bits<1> has_soffset = 1;
bits<1> has_offset = 1; bits<1> has_offset = 1;
bits<1> has_slc = 1; bits<1> has_slc = 1;
bits<1> has_tfe = 1; bits<1> has_tfe = 1;
bits<4> dwords = 0; bits<4> dwords = 0;
} }
class MUBUF_Real <bits<7> op, MUBUF_Pseudo ps> : class MUBUF_Real <MUBUF_Pseudo ps> :
InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> { InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> {
let isPseudo = 0; let isPseudo = 0;
let isCodeGenOnly = 0; let isCodeGenOnly = 0;
// copy relevant pseudo op flags // copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate; let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter; let AsmMatchConverter = ps.AsmMatchConverter;
let Constraints = ps.Constraints; let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding; let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags; let TSFlags = ps.TSFlags;
bits<12> offset; bits<12> offset;
bits<1> glc; bits<1> glc;
bits<1> dlc;
bits<8> vaddr; bits<8> vaddr;
bits<8> vdata; bits<8> vdata;
bits<7> srsrc; bits<7> srsrc;
bits<1> slc; bits<1> slc;
bits<1> tfe; bits<1> tfe;
bits<8> soffset; bits<8> soffset;
} }
// For cache invalidation instructions. // For cache invalidation instructions.
class MUBUF_Invalidate <string opName, SDPatternOperator node> : class MUBUF_Invalidate <string opName, SDPatternOperator node = null_frag> :
MUBUF_Pseudo<opName, (outs), (ins), "", [(node)]> { MUBUF_Pseudo<opName, (outs), (ins), "", [(node)]> {
let AsmMatchConverter = ""; let AsmMatchConverter = "";
let hasSideEffects = 1; let hasSideEffects = 1;
let mayStore = 1; let mayStore = 1;
// Set everything to 0. // Set everything to 0.
let offen = 0; let offen = 0;
let idxen = 0; let idxen = 0;
let addr64 = 0; let addr64 = 0;
let has_vdata = 0; let has_vdata = 0;
let has_vaddr = 0; let has_vaddr = 0;
let has_glc = 0; let has_glc = 0;
let has_dlc = 0;
let glc_value = 0; let glc_value = 0;
let dlc_value = 0;
let has_srsrc = 0; let has_srsrc = 0;
let has_soffset = 0; let has_soffset = 0;
let has_offset = 0; let has_offset = 0;
let has_slc = 0; let has_slc = 0;
let has_tfe = 0; let has_tfe = 0;
} }
class getMUBUFInsDA<list<RegisterClass> vdataList, class getMUBUFInsDA<list<RegisterClass> vdataList,
Show All 10 Linesclass getMUBUFInsDA<list<RegisterClass> vdataList,
dag InsData = !if(!empty(vaddrList), dag InsData = !if(!empty(vaddrList),
(ins vdataClass:$vdata, SReg_128:$srsrc, (ins vdataClass:$vdata, SReg_128:$srsrc,
SCSrc_b32:$soffset, offset:$offset, GLC:$glc, SLC:$slc), SCSrc_b32:$soffset, offset:$offset, GLC:$glc, SLC:$slc),
(ins vdataClass:$vdata, vaddrClass:$vaddr, SReg_128:$srsrc, (ins vdataClass:$vdata, vaddrClass:$vaddr, SReg_128:$srsrc,
SCSrc_b32:$soffset, offset:$offset, GLC:$glc, SLC:$slc) SCSrc_b32:$soffset, offset:$offset, GLC:$glc, SLC:$slc)
); );
dag ret = !con( dag ret = !con(
!if(!empty(vdataList), InsNoData, InsData), !if(!empty(vdataList), InsNoData, InsData),
!if(isLds, (ins), (ins TFE:$tfe)) !if(isLds, (ins DLC:$dlc), (ins TFE:$tfe, DLC:$dlc))
); );
} }
class getMUBUFDwords<RegisterClass regClass> { class getMUBUFDwords<RegisterClass regClass> {
string regClassAsInt = !cast<string>(regClass); string regClassAsInt = !cast<string>(regClass);
int ret = int ret =
!if(!eq(regClassAsInt, !cast<string>(VGPR_32)), 1, !if(!eq(regClassAsInt, !cast<string>(VGPR_32)), 1,
!if(!eq(regClassAsInt, !cast<string>(VReg_64)), 2, !if(!eq(regClassAsInt, !cast<string>(VReg_64)), 2,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesclass MUBUF_Load_Pseudo <string opName,
list<dag> pattern=[], list<dag> pattern=[],
// Workaround bug bz30254 // Workaround bug bz30254
int addrKindCopy = addrKind> int addrKindCopy = addrKind>
: MUBUF_Pseudo<opName, : MUBUF_Pseudo<opName,
(outs vdataClass:$vdata), (outs vdataClass:$vdata),
!con(getMUBUFIns<addrKindCopy, [], isLds>.ret, !con(getMUBUFIns<addrKindCopy, [], isLds>.ret,
!if(HasTiedDest, (ins vdataClass:$vdata_in), (ins))), !if(HasTiedDest, (ins vdataClass:$vdata_in), (ins))),
" $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$glc$slc" # " $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$glc$slc" #
!if(isLds, " lds", "$tfe"), !if(isLds, " lds", "$tfe") # "$dlc",
pattern>, pattern>,
MUBUF_SetupAddr<addrKindCopy> { MUBUF_SetupAddr<addrKindCopy> {
let PseudoInstr = opName # !if(isLds, "_lds", "") # let PseudoInstr = opName # !if(isLds, "_lds", "") #
"_" # getAddrName<addrKindCopy>.ret; "_" # getAddrName<addrKindCopy>.ret;
let AsmMatchConverter = !if(isLds, "cvtMubufLds", "cvtMubuf"); let AsmMatchConverter = !if(isLds, "cvtMubufLds", "cvtMubuf");
let Constraints = !if(HasTiedDest, "$vdata = $vdata_in", ""); let Constraints = !if(HasTiedDest, "$vdata = $vdata_in", "");
let mayLoad = 1; let mayLoad = 1;
Show All 13 Linesmulticlass MUBUF_Pseudo_Loads<string opName, RegisterClass vdataClass,
bit TiedDest = 0, bit TiedDest = 0,
bit isLds = 0> { bit isLds = 0> {
def _OFFSET : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, def _OFFSET : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
TiedDest, isLds, TiedDest, isLds,
!if(isLds, !if(isLds,
[], [],
[(set load_vt:$vdata, [(set load_vt:$vdata,
(ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))])>, (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc)))])>,
MUBUFAddr64Table<0, NAME # !if(isLds, "_LDS", "")>; MUBUFAddr64Table<0, NAME # !if(isLds, "_LDS", "")>;
def _ADDR64 : MUBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, vdataClass, def _ADDR64 : MUBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
TiedDest, isLds, TiedDest, isLds,
!if(isLds, !if(isLds,
[], [],
[(set load_vt:$vdata, [(set load_vt:$vdata,
(ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))])>, (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc)))])>,
MUBUFAddr64Table<1, NAME # !if(isLds, "_LDS", "")>; MUBUFAddr64Table<1, NAME # !if(isLds, "_LDS", "")>;
def _OFFEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, TiedDest, isLds>; def _OFFEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, TiedDest, isLds>;
def _IDXEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, TiedDest, isLds>; def _IDXEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, TiedDest, isLds>;
def _BOTHEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, TiedDest, isLds>; def _BOTHEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, TiedDest, isLds>;
let DisableWQM = 1 in { let DisableWQM = 1 in {
def _OFFSET_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, TiedDest, isLds>; def _OFFSET_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, TiedDest, isLds>;
Show All 16 Linesclass MUBUF_Store_Pseudo <string opName,
RegisterClass vdataClass, RegisterClass vdataClass,
list<dag> pattern=[], list<dag> pattern=[],
// Workaround bug bz30254 // Workaround bug bz30254
int addrKindCopy = addrKind, int addrKindCopy = addrKind,
RegisterClass vdataClassCopy = vdataClass> RegisterClass vdataClassCopy = vdataClass>
: MUBUF_Pseudo<opName, : MUBUF_Pseudo<opName,
(outs), (outs),
getMUBUFIns<addrKindCopy, [vdataClassCopy]>.ret, getMUBUFIns<addrKindCopy, [vdataClassCopy]>.ret,
" $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe", " $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe$dlc",
pattern>, pattern>,
MUBUF_SetupAddr<addrKindCopy> { MUBUF_SetupAddr<addrKindCopy> {
let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret; let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
let mayLoad = 0; let mayLoad = 0;
let mayStore = 1; let mayStore = 1;
let maybeAtomic = 1; let maybeAtomic = 1;
let dwords = getMUBUFDwords<vdataClass>.ret; let dwords = getMUBUFDwords<vdataClass>.ret;
} }
multiclass MUBUF_Pseudo_Stores<string opName, RegisterClass vdataClass, multiclass MUBUF_Pseudo_Stores<string opName, RegisterClass vdataClass,
ValueType store_vt = i32, ValueType store_vt = i32,
SDPatternOperator st = null_frag> { SDPatternOperator st = null_frag> {
def _OFFSET : MUBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass, def _OFFSET : MUBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
[(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset, [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>, i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc))]>,
MUBUFAddr64Table<0, NAME>; MUBUFAddr64Table<0, NAME>;
def _ADDR64 : MUBUF_Store_Pseudo <opName, BUFAddrKind.Addr64, vdataClass, def _ADDR64 : MUBUF_Store_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
[(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, [(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>, i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc))]>,
MUBUFAddr64Table<1, NAME>; MUBUFAddr64Table<1, NAME>;
def _OFFEN : MUBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>; def _OFFEN : MUBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
def _IDXEN : MUBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>; def _IDXEN : MUBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
def _BOTHEN : MUBUF_Store_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>; def _BOTHEN : MUBUF_Store_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
let DisableWQM = 1 in { let DisableWQM = 1 in {
def _OFFSET_exact : MUBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass>; def _OFFSET_exact : MUBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass>;
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Linesclass MUBUF_Atomic_Pseudo<string opName,
: MUBUF_Pseudo<opName, outs, ins, asmOps, pattern>, : MUBUF_Pseudo<opName, outs, ins, asmOps, pattern>,
MUBUF_SetupAddr<addrKindCopy> { MUBUF_SetupAddr<addrKindCopy> {
let mayStore = 1; let mayStore = 1;
let mayLoad = 1; let mayLoad = 1;
let hasPostISelHook = 1; let hasPostISelHook = 1;
let hasSideEffects = 1; let hasSideEffects = 1;
let DisableWQM = 1; let DisableWQM = 1;
let has_glc = 0; let has_glc = 0;
let has_dlc = 0;
let has_tfe = 0; let has_tfe = 0;
let maybeAtomic = 1; let maybeAtomic = 1;
} }
class MUBUF_AtomicNoRet_Pseudo<string opName, int addrKind, class MUBUF_AtomicNoRet_Pseudo<string opName, int addrKind,
RegisterClass vdataClass, RegisterClass vdataClass,
list<dag> pattern=[], list<dag> pattern=[],
// Workaround bug bz30254 // Workaround bug bz30254
int addrKindCopy = addrKind, int addrKindCopy = addrKind,
RegisterClass vdataClassCopy = vdataClass> RegisterClass vdataClassCopy = vdataClass>
: MUBUF_Atomic_Pseudo<opName, addrKindCopy, : MUBUF_Atomic_Pseudo<opName, addrKindCopy,
(outs), (outs),
getMUBUFAtomicIns<addrKindCopy, vdataClassCopy, 0>.ret, getMUBUFAtomicIns<addrKindCopy, vdataClassCopy, 0>.ret,
" $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$slc", " $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$slc",
pattern>, pattern>,
AtomicNoRet<opName # "_" # getAddrName<addrKindCopy>.ret, 0> { AtomicNoRet<opName # "_" # getAddrName<addrKindCopy>.ret, 0> {
let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret; let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
let glc_value = 0; let glc_value = 0;
let dlc_value = 0;
let AsmMatchConverter = "cvtMubufAtomic"; let AsmMatchConverter = "cvtMubufAtomic";
} }
class MUBUF_AtomicRet_Pseudo<string opName, int addrKind, class MUBUF_AtomicRet_Pseudo<string opName, int addrKind,
RegisterClass vdataClass, RegisterClass vdataClass,
list<dag> pattern=[], list<dag> pattern=[],
// Workaround bug bz30254 // Workaround bug bz30254
int addrKindCopy = addrKind, int addrKindCopy = addrKind,
RegisterClass vdataClassCopy = vdataClass> RegisterClass vdataClassCopy = vdataClass>
: MUBUF_Atomic_Pseudo<opName, addrKindCopy, : MUBUF_Atomic_Pseudo<opName, addrKindCopy,
(outs vdataClassCopy:$vdata), (outs vdataClassCopy:$vdata),
getMUBUFAtomicIns<addrKindCopy, vdataClassCopy, 1>.ret, getMUBUFAtomicIns<addrKindCopy, vdataClassCopy, 1>.ret,
" $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # " glc$slc", " $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # " glc$slc",
pattern>, pattern>,
AtomicNoRet<opName # "_" # getAddrName<addrKindCopy>.ret, 1> { AtomicNoRet<opName # "_" # getAddrName<addrKindCopy>.ret, 1> {
let PseudoInstr = opName # "_rtn_" # getAddrName<addrKindCopy>.ret; let PseudoInstr = opName # "_rtn_" # getAddrName<addrKindCopy>.ret;
let glc_value = 1; let glc_value = 1;
let dlc_value = 0;
let Constraints = "$vdata = $vdata_in"; let Constraints = "$vdata = $vdata_in";
let DisableEncoding = "$vdata_in"; let DisableEncoding = "$vdata_in";
let AsmMatchConverter = "cvtMubufAtomicReturn"; let AsmMatchConverter = "cvtMubufAtomicReturn";
} }
multiclass MUBUF_Pseudo_Atomics_NO_RTN <string opName, multiclass MUBUF_Pseudo_Atomics_NO_RTN <string opName,
RegisterClass vdataClass, RegisterClass vdataClass,
ValueType vdataType, ValueType vdataType,
▲ Show 20 Lines • Show All 363 Lines • ▼ Show 20 Lines
// Instruction definitions for CI and newer. // Instruction definitions for CI and newer.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def BUFFER_WBINVL1_VOL : MUBUF_Invalidate <"buffer_wbinvl1_vol", def BUFFER_WBINVL1_VOL : MUBUF_Invalidate <"buffer_wbinvl1_vol",
int_amdgcn_buffer_wbinvl1_vol>; int_amdgcn_buffer_wbinvl1_vol>;
} // End let SubtargetPredicate = isGFX7Plus } // End let SubtargetPredicate = isGFX7Plus
let SubtargetPredicate = isGFX10Plus in {
def BUFFER_GL0_INV : MUBUF_Invalidate<"buffer_gl0_inv">;
def BUFFER_GL1_INV : MUBUF_Invalidate<"buffer_gl1_inv">;
} // End SubtargetPredicate = isGFX10Plus
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MUBUF Patterns // MUBUF Patterns
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def extract_glc : SDNodeXForm<imm, [{ def extract_glc : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() & 1, SDLoc(N), MVT::i8); return CurDAG->getTargetConstant(N->getZExtValue() & 1, SDLoc(N), MVT::i8);
}]>; }]>;
def extract_slc : SDNodeXForm<imm, [{ def extract_slc : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((N->getZExtValue() >> 1) & 1, SDLoc(N), MVT::i8); return CurDAG->getTargetConstant((N->getZExtValue() >> 1) & 1, SDLoc(N), MVT::i8);
}]>; }]>;
def extract_dlc : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((N->getZExtValue() >> 2) & 1, SDLoc(N), MVT::i8);
}]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// buffer_load/store_format patterns // buffer_load/store_format patterns
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
multiclass MUBUF_LoadIntrinsicPat<SDPatternOperator name, ValueType vt, multiclass MUBUF_LoadIntrinsicPat<SDPatternOperator name, ValueType vt,
string opcode> { string opcode> {
def : GCNPat< def : GCNPat<
(vt (name v4i32:$rsrc, 0, 0, i32:$soffset, imm:$offset, (vt (name v4i32:$rsrc, 0, 0, i32:$soffset, imm:$offset,
imm:$cachepolicy, 0)), imm:$cachepolicy, 0)),
(!cast<MUBUF_Pseudo>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset), (!cast<MUBUF_Pseudo>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset),
(extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
def : GCNPat< def : GCNPat<
(vt (name v4i32:$rsrc, 0, i32:$voffset, i32:$soffset, imm:$offset, (vt (name v4i32:$rsrc, 0, i32:$voffset, i32:$soffset, imm:$offset,
imm:$cachepolicy, 0)), imm:$cachepolicy, 0)),
(!cast<MUBUF_Pseudo>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset), (!cast<MUBUF_Pseudo>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset),
(extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
def : GCNPat< def : GCNPat<
(vt (name v4i32:$rsrc, i32:$vindex, 0, i32:$soffset, imm:$offset, (vt (name v4i32:$rsrc, i32:$vindex, 0, i32:$soffset, imm:$offset,
imm:$cachepolicy, imm)), imm:$cachepolicy, imm)),
(!cast<MUBUF_Pseudo>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset), (!cast<MUBUF_Pseudo>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset),
(extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
def : GCNPat< def : GCNPat<
(vt (name v4i32:$rsrc, i32:$vindex, i32:$voffset, i32:$soffset, imm:$offset, (vt (name v4i32:$rsrc, i32:$vindex, i32:$voffset, i32:$soffset, imm:$offset,
imm:$cachepolicy, imm)), imm:$cachepolicy, imm)),
(!cast<MUBUF_Pseudo>(opcode # _BOTHEN) (!cast<MUBUF_Pseudo>(opcode # _BOTHEN)
(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
$rsrc, $soffset, (as_i16imm $offset), $rsrc, $soffset, (as_i16imm $offset),
(extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
} }
defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, f32, "BUFFER_LOAD_FORMAT_X">; defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, f32, "BUFFER_LOAD_FORMAT_X">;
defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, i32, "BUFFER_LOAD_FORMAT_X">; defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, i32, "BUFFER_LOAD_FORMAT_X">;
defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v2f32, "BUFFER_LOAD_FORMAT_XY">; defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v2f32, "BUFFER_LOAD_FORMAT_XY">;
defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v2i32, "BUFFER_LOAD_FORMAT_XY">; defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v2i32, "BUFFER_LOAD_FORMAT_XY">;
defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v3f32, "BUFFER_LOAD_FORMAT_XYZ">; defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v3f32, "BUFFER_LOAD_FORMAT_XYZ">;
Show All 31 Lines
defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_ushort, i32, "BUFFER_LOAD_USHORT">; defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_ushort, i32, "BUFFER_LOAD_USHORT">;
multiclass MUBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt, multiclass MUBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt,
string opcode> { string opcode> {
def : GCNPat< def : GCNPat<
(name vt:$vdata, v4i32:$rsrc, 0, 0, i32:$soffset, imm:$offset, (name vt:$vdata, v4i32:$rsrc, 0, 0, i32:$soffset, imm:$offset,
imm:$cachepolicy, 0), imm:$cachepolicy, 0),
(!cast<MUBUF_Pseudo>(opcode # _OFFSET_exact) $vdata, $rsrc, $soffset, (as_i16imm $offset), (!cast<MUBUF_Pseudo>(opcode # _OFFSET_exact) $vdata, $rsrc, $soffset, (as_i16imm $offset),
(extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
def : GCNPat< def : GCNPat<
(name vt:$vdata, v4i32:$rsrc, 0, i32:$voffset, i32:$soffset, imm:$offset, (name vt:$vdata, v4i32:$rsrc, 0, i32:$voffset, i32:$soffset, imm:$offset,
imm:$cachepolicy, 0), imm:$cachepolicy, 0),
(!cast<MUBUF_Pseudo>(opcode # _OFFEN_exact) $vdata, $voffset, $rsrc, $soffset, (!cast<MUBUF_Pseudo>(opcode # _OFFEN_exact) $vdata, $voffset, $rsrc, $soffset,
(as_i16imm $offset), (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (as_i16imm $offset), (extract_glc $cachepolicy),
(extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
def : GCNPat< def : GCNPat<
(name vt:$vdata, v4i32:$rsrc, i32:$vindex, 0, i32:$soffset, imm:$offset, (name vt:$vdata, v4i32:$rsrc, i32:$vindex, 0, i32:$soffset, imm:$offset,
imm:$cachepolicy, imm), imm:$cachepolicy, imm),
(!cast<MUBUF_Pseudo>(opcode # _IDXEN_exact) $vdata, $vindex, $rsrc, $soffset, (!cast<MUBUF_Pseudo>(opcode # _IDXEN_exact) $vdata, $vindex, $rsrc, $soffset,
(as_i16imm $offset), (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (as_i16imm $offset), (extract_glc $cachepolicy),
(extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
def : GCNPat< def : GCNPat<
(name vt:$vdata, v4i32:$rsrc, i32:$vindex, i32:$voffset, i32:$soffset, imm:$offset, (name vt:$vdata, v4i32:$rsrc, i32:$vindex, i32:$voffset, i32:$soffset, imm:$offset,
imm:$cachepolicy, imm), imm:$cachepolicy, imm),
(!cast<MUBUF_Pseudo>(opcode # _BOTHEN_exact) (!cast<MUBUF_Pseudo>(opcode # _BOTHEN_exact)
$vdata, $vdata,
(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
$rsrc, $soffset, (as_i16imm $offset), $rsrc, $soffset, (as_i16imm $offset), (extract_glc $cachepolicy),
(extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
} }
defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, f32, "BUFFER_STORE_FORMAT_X">; defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, f32, "BUFFER_STORE_FORMAT_X">;
defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, i32, "BUFFER_STORE_FORMAT_X">; defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, i32, "BUFFER_STORE_FORMAT_X">;
defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v2f32, "BUFFER_STORE_FORMAT_XY">; defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v2f32, "BUFFER_STORE_FORMAT_XY">;
defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v2i32, "BUFFER_STORE_FORMAT_XY">; defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v2i32, "BUFFER_STORE_FORMAT_XY">;
defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v3f32, "BUFFER_STORE_FORMAT_XYZ">; defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v3f32, "BUFFER_STORE_FORMAT_XYZ">;
▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Lines (BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN
(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
$rsrc, $soffset, (as_i16imm $offset), (extract_slc $cachepolicy)), $rsrc, $soffset, (as_i16imm $offset), (extract_slc $cachepolicy)),
sub0) sub0)
>; >;
class MUBUFLoad_PatternADDR64 <MUBUF_Pseudo Instr_ADDR64, ValueType vt, class MUBUFLoad_PatternADDR64 <MUBUF_Pseudo Instr_ADDR64, ValueType vt,
PatFrag constant_ld> : GCNPat < PatFrag constant_ld> : GCNPat <
(vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
i16:$offset, i1:$glc, i1:$slc, i1:$tfe))), i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc))),
(Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe) (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe, $dlc)
>; >;
multiclass MUBUFLoad_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo Instr_OFFSET, multiclass MUBUFLoad_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo Instr_OFFSET,
ValueType vt, PatFrag atomic_ld> { ValueType vt, PatFrag atomic_ld> {
def : GCNPat < def : GCNPat <
(vt (atomic_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, (vt (atomic_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
i16:$offset, i1:$slc))), i16:$offset, i1:$slc))),
(Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, 0, $slc, 0) (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, 0, $slc, 0, 0)
>; >;
def : GCNPat < def : GCNPat <
(vt (atomic_ld (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset))), (vt (atomic_ld (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset))),
(Instr_OFFSET $rsrc, $soffset, (as_i16imm $offset), 0, 0, 0) (Instr_OFFSET $rsrc, $soffset, (as_i16imm $offset), 0, 0, 0, 0)
>; >;
} }
let SubtargetPredicate = isGFX6GFX7 in { let SubtargetPredicate = isGFX6GFX7 in {
def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>; def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>; def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>; def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>; def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORD_ADDR64, BUFFER_LOAD_DWORD_OFFSET, i32, mubuf_load_atomic>; defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORD_ADDR64, BUFFER_LOAD_DWORD_OFFSET, i32, mubuf_load_atomic>;
defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, BUFFER_LOAD_DWORDX2_OFFSET, i64, mubuf_load_atomic>; defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, BUFFER_LOAD_DWORDX2_OFFSET, i64, mubuf_load_atomic>;
} // End SubtargetPredicate = isGFX6GFX7 } // End SubtargetPredicate = isGFX6GFX7
multiclass MUBUFLoad_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt, multiclass MUBUFLoad_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt,
PatFrag ld> { PatFrag ld> {
def : GCNPat < def : GCNPat <
(vt (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, (vt (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset,
i16:$offset, i1:$glc, i1:$slc, i1:$tfe))), i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc))),
(Instr_OFFSET $srsrc, $soffset, $offset, $glc, $slc, $tfe) (Instr_OFFSET $srsrc, $soffset, $offset, $glc, $slc, $tfe, $dlc)
>; >;
} }
let OtherPredicates = [Has16BitInsts] in { let OtherPredicates = [Has16BitInsts] in {
defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_OFFSET, i16, sextloadi8_constant>; defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_OFFSET, i16, sextloadi8_constant>;
defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_OFFSET, i16, az_extloadi8_constant>; defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_OFFSET, i16, az_extloadi8_constant>;
defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_OFFSET, i16, mubuf_sextloadi8>; defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_OFFSET, i16, mubuf_sextloadi8>;
defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_OFFSET, i16, mubuf_az_extloadi8>; defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_OFFSET, i16, mubuf_az_extloadi8>;
defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_OFFSET, i16, mubuf_load>; defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_OFFSET, i16, mubuf_load>;
} // End OtherPredicates = [Has16BitInsts] } // End OtherPredicates = [Has16BitInsts]
multiclass MUBUFScratchLoadPat <MUBUF_Pseudo InstrOffen, multiclass MUBUFScratchLoadPat <MUBUF_Pseudo InstrOffen,
MUBUF_Pseudo InstrOffset, MUBUF_Pseudo InstrOffset,
ValueType vt, PatFrag ld> { ValueType vt, PatFrag ld> {
def : GCNPat < def : GCNPat <
(vt (ld (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr, (vt (ld (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
i32:$soffset, u16imm:$offset))), i32:$soffset, u16imm:$offset))),
(InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0) (InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0, 0)
>; >;
def : GCNPat < def : GCNPat <
(vt (ld (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset))), (vt (ld (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset))),
(InstrOffset $srsrc, $soffset, $offset, 0, 0, 0) (InstrOffset $srsrc, $soffset, $offset, 0, 0, 0, 0)
>; >;
} }
// XXX - Is it possible to have a complex pattern in a PatFrag? // XXX - Is it possible to have a complex pattern in a PatFrag?
multiclass MUBUFScratchLoadPat_D16 <MUBUF_Pseudo InstrOffen, multiclass MUBUFScratchLoadPat_D16 <MUBUF_Pseudo InstrOffen,
MUBUF_Pseudo InstrOffset, MUBUF_Pseudo InstrOffset,
ValueType vt, PatFrag ld_frag> { ValueType vt, PatFrag ld_frag> {
def : GCNPat < def : GCNPat <
(ld_frag (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr, i32:$soffset, u16imm:$offset), vt:$in), (ld_frag (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr, i32:$soffset, u16imm:$offset), vt:$in),
(InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0, $in) (InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0, 0, $in)
>; >;
def : GCNPat < def : GCNPat <
(ld_frag (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset), vt:$in), (ld_frag (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset), vt:$in),
(InstrOffset $srsrc, $soffset, $offset, 0, 0, 0, $in) (InstrOffset $srsrc, $soffset, $offset, 0, 0, 0, 0, $in)
>; >;
} }
defm : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, BUFFER_LOAD_SBYTE_OFFSET, i32, sextloadi8_private>; defm : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, BUFFER_LOAD_SBYTE_OFFSET, i32, sextloadi8_private>;
defm : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, BUFFER_LOAD_UBYTE_OFFSET, i32, az_extloadi8_private>; defm : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, BUFFER_LOAD_UBYTE_OFFSET, i32, az_extloadi8_private>;
defm : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, BUFFER_LOAD_SBYTE_OFFSET, i16, sextloadi8_private>; defm : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, BUFFER_LOAD_SBYTE_OFFSET, i16, sextloadi8_private>;
defm : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, BUFFER_LOAD_UBYTE_OFFSET, i16, az_extloadi8_private>; defm : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, BUFFER_LOAD_UBYTE_OFFSET, i16, az_extloadi8_private>;
defm : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, BUFFER_LOAD_SSHORT_OFFSET, i32, sextloadi16_private>; defm : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, BUFFER_LOAD_SSHORT_OFFSET, i32, sextloadi16_private>;
Show All 21 Lines
} }
multiclass MUBUFStore_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo Instr_OFFSET, multiclass MUBUFStore_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo Instr_OFFSET,
ValueType vt, PatFrag atomic_st> { ValueType vt, PatFrag atomic_st> {
// Store follows atomic op convention so address is forst // Store follows atomic op convention so address is forst
def : GCNPat < def : GCNPat <
(atomic_st (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, (atomic_st (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
i16:$offset, i1:$slc), vt:$val), i16:$offset, i1:$slc), vt:$val),
(Instr_ADDR64 $val, $vaddr, $srsrc, $soffset, $offset, 0, $slc, 0) (Instr_ADDR64 $val, $vaddr, $srsrc, $soffset, $offset, 0, $slc, 0, 0)
>; >;
def : GCNPat < def : GCNPat <
(atomic_st (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset), vt:$val), (atomic_st (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset), vt:$val),
(Instr_OFFSET $val, $rsrc, $soffset, (as_i16imm $offset), 0, 0, 0) (Instr_OFFSET $val, $rsrc, $soffset, (as_i16imm $offset), 0, 0, 0, 0)
>; >;
} }
let SubtargetPredicate = isGFX6GFX7 in { let SubtargetPredicate = isGFX6GFX7 in {
defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORD_ADDR64, BUFFER_STORE_DWORD_OFFSET, i32, store_atomic_global>; defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORD_ADDR64, BUFFER_STORE_DWORD_OFFSET, i32, store_atomic_global>;
defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORDX2_ADDR64, BUFFER_STORE_DWORDX2_OFFSET, i64, store_atomic_global>; defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORDX2_ADDR64, BUFFER_STORE_DWORDX2_OFFSET, i64, store_atomic_global>;
} // End Predicates = isGFX6GFX7 } // End Predicates = isGFX6GFX7
multiclass MUBUFStore_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt, multiclass MUBUFStore_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt,
PatFrag st> { PatFrag st> {
def : GCNPat < def : GCNPat <
(st vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset, (st vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
i16:$offset, i1:$glc, i1:$slc, i1:$tfe)), i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc)),
(Instr_OFFSET $vdata, $srsrc, $soffset, $offset, $glc, $slc, $tfe) (Instr_OFFSET $vdata, $srsrc, $soffset, $offset, $glc, $slc, $tfe, $dlc)
>; >;
} }
defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE_OFFSET, i16, truncstorei8_global>; defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE_OFFSET, i16, truncstorei8_global>;
defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT_OFFSET, i16, store_global>; defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT_OFFSET, i16, store_global>;
multiclass MUBUFScratchStorePat <MUBUF_Pseudo InstrOffen, multiclass MUBUFScratchStorePat <MUBUF_Pseudo InstrOffen,
MUBUF_Pseudo InstrOffset, MUBUF_Pseudo InstrOffset,
ValueType vt, PatFrag st> { ValueType vt, PatFrag st> {
def : GCNPat < def : GCNPat <
(st vt:$value, (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr, (st vt:$value, (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
i32:$soffset, u16imm:$offset)), i32:$soffset, u16imm:$offset)),
(InstrOffen $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0) (InstrOffen $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0, 0)
>; >;
def : GCNPat < def : GCNPat <
(st vt:$value, (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, (st vt:$value, (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset,
u16imm:$offset)), u16imm:$offset)),
(InstrOffset $value, $srsrc, $soffset, $offset, 0, 0, 0) (InstrOffset $value, $srsrc, $soffset, $offset, 0, 0, 0, 0)
>; >;
} }
defm : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, BUFFER_STORE_BYTE_OFFSET, i32, truncstorei8_private>; defm : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, BUFFER_STORE_BYTE_OFFSET, i32, truncstorei8_private>;
defm : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, BUFFER_STORE_SHORT_OFFSET, i32, truncstorei16_private>; defm : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, BUFFER_STORE_SHORT_OFFSET, i32, truncstorei16_private>;
defm : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, BUFFER_STORE_BYTE_OFFSET, i16, truncstorei8_private>; defm : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, BUFFER_STORE_BYTE_OFFSET, i16, truncstorei8_private>;
defm : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, BUFFER_STORE_SHORT_OFFSET, i16, store_private>; defm : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, BUFFER_STORE_SHORT_OFFSET, i16, store_private>;
defm : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, BUFFER_STORE_DWORD_OFFSET, i32, store_private>; defm : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, BUFFER_STORE_DWORD_OFFSET, i32, store_private>;
Show All 21 Lines
multiclass MTBUF_LoadIntrinsicPat<SDPatternOperator name, ValueType vt, multiclass MTBUF_LoadIntrinsicPat<SDPatternOperator name, ValueType vt,
string opcode> { string opcode> {
def : GCNPat< def : GCNPat<
(vt (name v4i32:$rsrc, 0, 0, i32:$soffset, imm:$offset, (vt (name v4i32:$rsrc, 0, 0, i32:$soffset, imm:$offset,
imm:$format, imm:$cachepolicy, 0)), imm:$format, imm:$cachepolicy, 0)),
(!cast<MTBUF_Pseudo>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset), (!cast<MTBUF_Pseudo>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset),
(as_i8imm $format), (as_i8imm $format),
(extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
def : GCNPat< def : GCNPat<
(vt (name v4i32:$rsrc, i32:$vindex, 0, i32:$soffset, imm:$offset, (vt (name v4i32:$rsrc, i32:$vindex, 0, i32:$soffset, imm:$offset,
imm:$format, imm:$cachepolicy, imm)), imm:$format, imm:$cachepolicy, imm)),
(!cast<MTBUF_Pseudo>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset), (!cast<MTBUF_Pseudo>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset),
(as_i8imm $format), (as_i8imm $format),
(extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
def : GCNPat< def : GCNPat<
(vt (name v4i32:$rsrc, 0, i32:$voffset, i32:$soffset, imm:$offset, (vt (name v4i32:$rsrc, 0, i32:$voffset, i32:$soffset, imm:$offset,
imm:$format, imm:$cachepolicy, 0)), imm:$format, imm:$cachepolicy, 0)),
(!cast<MTBUF_Pseudo>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset), (!cast<MTBUF_Pseudo>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset),
(as_i8imm $format), (as_i8imm $format),
(extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
def : GCNPat< def : GCNPat<
(vt (name v4i32:$rsrc, i32:$vindex, i32:$voffset, i32:$soffset, imm:$offset, (vt (name v4i32:$rsrc, i32:$vindex, i32:$voffset, i32:$soffset, imm:$offset,
imm:$format, imm:$cachepolicy, imm)), imm:$format, imm:$cachepolicy, imm)),
(!cast<MTBUF_Pseudo>(opcode # _BOTHEN) (!cast<MTBUF_Pseudo>(opcode # _BOTHEN)
(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
$rsrc, $soffset, (as_i16imm $offset), $rsrc, $soffset, (as_i16imm $offset),
(as_i8imm $format), (as_i8imm $format),
(extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
} }
defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, i32, "TBUFFER_LOAD_FORMAT_X">; defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, i32, "TBUFFER_LOAD_FORMAT_X">;
defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v2i32, "TBUFFER_LOAD_FORMAT_XY">; defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v2i32, "TBUFFER_LOAD_FORMAT_XY">;
defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v3i32, "TBUFFER_LOAD_FORMAT_XYZ">; defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v3i32, "TBUFFER_LOAD_FORMAT_XYZ">;
defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v4i32, "TBUFFER_LOAD_FORMAT_XYZW">; defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v4i32, "TBUFFER_LOAD_FORMAT_XYZW">;
defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, f32, "TBUFFER_LOAD_FORMAT_X">; defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, f32, "TBUFFER_LOAD_FORMAT_X">;
Show All 15 Lines
multiclass MTBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt, multiclass MTBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt,
string opcode> { string opcode> {
def : GCNPat< def : GCNPat<
(name vt:$vdata, v4i32:$rsrc, 0, 0, i32:$soffset, imm:$offset, (name vt:$vdata, v4i32:$rsrc, 0, 0, i32:$soffset, imm:$offset,
imm:$format, imm:$cachepolicy, 0), imm:$format, imm:$cachepolicy, 0),
(!cast<MTBUF_Pseudo>(opcode # _OFFSET_exact) $vdata, $rsrc, $soffset, (!cast<MTBUF_Pseudo>(opcode # _OFFSET_exact) $vdata, $rsrc, $soffset,
(as_i16imm $offset), (as_i8imm $format), (as_i16imm $offset), (as_i8imm $format),
(extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
def : GCNPat< def : GCNPat<
(name vt:$vdata, v4i32:$rsrc, i32:$vindex, 0, i32:$soffset, imm:$offset, (name vt:$vdata, v4i32:$rsrc, i32:$vindex, 0, i32:$soffset, imm:$offset,
imm:$format, imm:$cachepolicy, imm), imm:$format, imm:$cachepolicy, imm),
(!cast<MTBUF_Pseudo>(opcode # _IDXEN_exact) $vdata, $vindex, $rsrc, $soffset, (!cast<MTBUF_Pseudo>(opcode # _IDXEN_exact) $vdata, $vindex, $rsrc, $soffset,
(as_i16imm $offset), (as_i8imm $format), (as_i16imm $offset), (as_i8imm $format),
(extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
def : GCNPat< def : GCNPat<
(name vt:$vdata, v4i32:$rsrc, 0, i32:$voffset, i32:$soffset, imm:$offset, (name vt:$vdata, v4i32:$rsrc, 0, i32:$voffset, i32:$soffset, imm:$offset,
imm:$format, imm:$cachepolicy, 0), imm:$format, imm:$cachepolicy, 0),
(!cast<MTBUF_Pseudo>(opcode # _OFFEN_exact) $vdata, $voffset, $rsrc, $soffset, (!cast<MTBUF_Pseudo>(opcode # _OFFEN_exact) $vdata, $voffset, $rsrc, $soffset,
(as_i16imm $offset), (as_i8imm $format), (as_i16imm $offset), (as_i8imm $format),
(extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
def : GCNPat< def : GCNPat<
(name vt:$vdata, v4i32:$rsrc, i32:$vindex, i32:$voffset, i32:$soffset, (name vt:$vdata, v4i32:$rsrc, i32:$vindex, i32:$voffset, i32:$soffset,
imm:$offset, imm:$format, imm:$cachepolicy, imm), imm:$offset, imm:$format, imm:$cachepolicy, imm),
(!cast<MTBUF_Pseudo>(opcode # _BOTHEN_exact) (!cast<MTBUF_Pseudo>(opcode # _BOTHEN_exact)
$vdata, $vdata,
(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
$rsrc, $soffset, (as_i16imm $offset), (as_i8imm $format), $rsrc, $soffset, (as_i16imm $offset), (as_i8imm $format),
(extract_glc $cachepolicy), (extract_slc $cachepolicy), 0) (extract_glc $cachepolicy), (extract_slc $cachepolicy), 0, (extract_dlc $cachepolicy))
>; >;
} }
defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, i32, "TBUFFER_STORE_FORMAT_X">; defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, i32, "TBUFFER_STORE_FORMAT_X">;
defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v2i32, "TBUFFER_STORE_FORMAT_XY">; defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v2i32, "TBUFFER_STORE_FORMAT_XY">;
defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v3i32, "TBUFFER_STORE_FORMAT_XYZ">; defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v3i32, "TBUFFER_STORE_FORMAT_XYZ">;
defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v4i32, "TBUFFER_STORE_FORMAT_XYZW">; defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v4i32, "TBUFFER_STORE_FORMAT_XYZW">;
defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, f32, "TBUFFER_STORE_FORMAT_X">; defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, f32, "TBUFFER_STORE_FORMAT_X">;
Show All 13 Lineslet SubtargetPredicate = HasPackedD16VMem in {
defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, v4f16, "TBUFFER_STORE_FORMAT_D16_XYZW">; defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, v4f16, "TBUFFER_STORE_FORMAT_D16_XYZW">;
} // End HasPackedD16VMem. } // End HasPackedD16VMem.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Target-specific instruction encodings. // Target-specific instruction encodings.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Base ENC_MUBUF for GFX6, GFX7. // Base ENC_MUBUF for GFX6, GFX7, GFX10.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class MUBUF_Real_si <bits<7> op, MUBUF_Pseudo ps> : class Base_MUBUF_Real_gfx6_gfx7_gfx10<bits<7> op, MUBUF_Pseudo ps, int ef> :
MUBUF_Real<op, ps>, MUBUF_Real<ps>, Enc64, SIMCInstr<ps.PseudoInstr, ef> {
Enc64,
SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI> {
let AssemblerPredicate=isGFX6GFX7;
let DecoderNamespace="GFX6GFX7";
let Inst{11-0} = !if(ps.has_offset, offset, ?); let Inst{11-0} = !if(ps.has_offset, offset, ?);
let Inst{12} = ps.offen; let Inst{12} = ps.offen;
let Inst{13} = ps.idxen; let Inst{13} = ps.idxen;
let Inst{14} = !if(ps.has_glc, glc, ps.glc_value); let Inst{14} = !if(ps.has_glc, glc, ps.glc_value);
let Inst{15} = ps.addr64;
let Inst{16} = !if(ps.lds, 1, 0); let Inst{16} = !if(ps.lds, 1, 0);
let Inst{24-18} = op; let Inst{24-18} = op;
let Inst{31-26} = 0x38; //encoding let Inst{31-26} = 0x38;
let Inst{39-32} = !if(ps.has_vaddr, vaddr, ?); let Inst{39-32} = !if(ps.has_vaddr, vaddr, ?);
let Inst{47-40} = !if(ps.has_vdata, vdata, ?); let Inst{47-40} = !if(ps.has_vdata, vdata, ?);
let Inst{52-48} = !if(ps.has_srsrc, srsrc{6-2}, ?); let Inst{52-48} = !if(ps.has_srsrc, srsrc{6-2}, ?);
let Inst{54} = !if(ps.has_slc, slc, ?); let Inst{54} = !if(ps.has_slc, slc, ?);
let Inst{55} = !if(ps.has_tfe, tfe, ?); let Inst{55} = !if(ps.has_tfe, tfe, ?);
let Inst{63-56} = !if(ps.has_soffset, soffset, ?); let Inst{63-56} = !if(ps.has_soffset, soffset, ?);
} }
multiclass MUBUF_Real_AllAddr_si<bits<7> op> { class MUBUF_Real_gfx10<bits<8> op, MUBUF_Pseudo ps> :
def _OFFSET_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>; Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.GFX10> {
def _ADDR64_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64")>; let Inst{15} = !if(ps.has_dlc, dlc, ps.dlc_value);
def _OFFEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>; let Inst{25} = op{7};
def _IDXEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>; }
def _BOTHEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
}
multiclass MUBUF_Real_AllAddr_Lds_si<bits<7> op> {
def _OFFSET_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>,
MUBUFLdsTable<0, NAME # "_OFFSET_si">;
def _ADDR64_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64")>,
MUBUFLdsTable<0, NAME # "_ADDR64_si">;
def _OFFEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>,
MUBUFLdsTable<0, NAME # "_OFFEN_si">;
def _IDXEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>,
MUBUFLdsTable<0, NAME # "_IDXEN_si">;
def _BOTHEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>,
MUBUFLdsTable<0, NAME # "_BOTHEN_si">;
def _LDS_OFFSET_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFSET")>,
MUBUFLdsTable<1, NAME # "_OFFSET_si">;
def _LDS_ADDR64_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_ADDR64")>,
MUBUFLdsTable<1, NAME # "_ADDR64_si">;
def _LDS_OFFEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFEN")>,
MUBUFLdsTable<1, NAME # "_OFFEN_si">;
def _LDS_IDXEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>,
MUBUFLdsTable<1, NAME # "_IDXEN_si">;
def _LDS_BOTHEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>,
MUBUFLdsTable<1, NAME # "_BOTHEN_si">;
}
multiclass MUBUF_Real_Atomic_si<bits<7> op> : MUBUF_Real_AllAddr_si<op> {
def _OFFSET_RTN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET_RTN")>;
def _ADDR64_RTN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64_RTN")>;
def _OFFEN_RTN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN_RTN")>;
def _IDXEN_RTN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN_RTN")>;
def _BOTHEN_RTN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>;
}
defm BUFFER_LOAD_FORMAT_X : MUBUF_Real_AllAddr_Lds_si <0x00>;
defm BUFFER_LOAD_FORMAT_XY : MUBUF_Real_AllAddr_si <0x01>;
defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Real_AllAddr_si <0x02>;
defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Real_AllAddr_si <0x03>;
defm BUFFER_STORE_FORMAT_X : MUBUF_Real_AllAddr_si <0x04>;
defm BUFFER_STORE_FORMAT_XY : MUBUF_Real_AllAddr_si <0x05>;
defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Real_AllAddr_si <0x06>;
defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Real_AllAddr_si <0x07>;
defm BUFFER_LOAD_UBYTE : MUBUF_Real_AllAddr_Lds_si <0x08>;
defm BUFFER_LOAD_SBYTE : MUBUF_Real_AllAddr_Lds_si <0x09>;
defm BUFFER_LOAD_USHORT : MUBUF_Real_AllAddr_Lds_si <0x0a>;
defm BUFFER_LOAD_SSHORT : MUBUF_Real_AllAddr_Lds_si <0x0b>;
defm BUFFER_LOAD_DWORD : MUBUF_Real_AllAddr_Lds_si <0x0c>;
defm BUFFER_LOAD_DWORDX2 : MUBUF_Real_AllAddr_si <0x0d>;
defm BUFFER_LOAD_DWORDX4 : MUBUF_Real_AllAddr_si <0x0e>;
defm BUFFER_LOAD_DWORDX3 : MUBUF_Real_AllAddr_si <0x0f>;
defm BUFFER_STORE_BYTE : MUBUF_Real_AllAddr_si <0x18>;
defm BUFFER_STORE_SHORT : MUBUF_Real_AllAddr_si <0x1a>;
defm BUFFER_STORE_DWORD : MUBUF_Real_AllAddr_si <0x1c>;
defm BUFFER_STORE_DWORDX2 : MUBUF_Real_AllAddr_si <0x1d>;
defm BUFFER_STORE_DWORDX4 : MUBUF_Real_AllAddr_si <0x1e>;
defm BUFFER_STORE_DWORDX3 : MUBUF_Real_AllAddr_si <0x1f>;
defm BUFFER_ATOMIC_SWAP : MUBUF_Real_Atomic_si <0x30>;
defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Real_Atomic_si <0x31>;
defm BUFFER_ATOMIC_ADD : MUBUF_Real_Atomic_si <0x32>;
defm BUFFER_ATOMIC_SUB : MUBUF_Real_Atomic_si <0x33>;
//defm BUFFER_ATOMIC_RSUB : MUBUF_Real_Atomic_si <0x34>; // isn't on CI & VI
defm BUFFER_ATOMIC_SMIN : MUBUF_Real_Atomic_si <0x35>;
defm BUFFER_ATOMIC_UMIN : MUBUF_Real_Atomic_si <0x36>;
defm BUFFER_ATOMIC_SMAX : MUBUF_Real_Atomic_si <0x37>;
defm BUFFER_ATOMIC_UMAX : MUBUF_Real_Atomic_si <0x38>;
defm BUFFER_ATOMIC_AND : MUBUF_Real_Atomic_si <0x39>;
defm BUFFER_ATOMIC_OR : MUBUF_Real_Atomic_si <0x3a>;
defm BUFFER_ATOMIC_XOR : MUBUF_Real_Atomic_si <0x3b>;
defm BUFFER_ATOMIC_INC : MUBUF_Real_Atomic_si <0x3c>;
defm BUFFER_ATOMIC_DEC : MUBUF_Real_Atomic_si <0x3d>;
//defm BUFFER_ATOMIC_FCMPSWAP : MUBUF_Real_Atomic_si <0x3e>; // isn't on VI
//defm BUFFER_ATOMIC_FMIN : MUBUF_Real_Atomic_si <0x3f>; // isn't on VI
//defm BUFFER_ATOMIC_FMAX : MUBUF_Real_Atomic_si <0x40>; // isn't on VI
defm BUFFER_ATOMIC_SWAP_X2 : MUBUF_Real_Atomic_si <0x50>;
defm BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_Real_Atomic_si <0x51>;
defm BUFFER_ATOMIC_ADD_X2 : MUBUF_Real_Atomic_si <0x52>;
defm BUFFER_ATOMIC_SUB_X2 : MUBUF_Real_Atomic_si <0x53>;
//defm BUFFER_ATOMIC_RSUB_X2 : MUBUF_Real_Atomic_si <0x54>; // isn't on CI & VI
defm BUFFER_ATOMIC_SMIN_X2 : MUBUF_Real_Atomic_si <0x55>;
defm BUFFER_ATOMIC_UMIN_X2 : MUBUF_Real_Atomic_si <0x56>;
defm BUFFER_ATOMIC_SMAX_X2 : MUBUF_Real_Atomic_si <0x57>;
defm BUFFER_ATOMIC_UMAX_X2 : MUBUF_Real_Atomic_si <0x58>;
defm BUFFER_ATOMIC_AND_X2 : MUBUF_Real_Atomic_si <0x59>;
defm BUFFER_ATOMIC_OR_X2 : MUBUF_Real_Atomic_si <0x5a>;
defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Real_Atomic_si <0x5b>;
defm BUFFER_ATOMIC_INC_X2 : MUBUF_Real_Atomic_si <0x5c>;
defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Real_Atomic_si <0x5d>;
// FIXME: Need to handle hazard for BUFFER_ATOMIC_FCMPSWAP_X2 on CI.
//defm BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_Real_Atomic_si <0x5e">; // isn't on VI
//defm BUFFER_ATOMIC_FMIN_X2 : MUBUF_Real_Atomic_si <0x5f>; // isn't on VI
//defm BUFFER_ATOMIC_FMAX_X2 : MUBUF_Real_Atomic_si <0x60>; // isn't on VI
def BUFFER_WBINVL1_SC_si : MUBUF_Real_si <0x70, BUFFER_WBINVL1_SC>; class MUBUF_Real_gfx6_gfx7<bits<8> op, MUBUF_Pseudo ps> :
def BUFFER_WBINVL1_si : MUBUF_Real_si <0x71, BUFFER_WBINVL1>; Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.SI> {
let Inst{15} = ps.addr64;
}
class MTBUF_Real_si <bits<3> op, MTBUF_Pseudo ps> : //===----------------------------------------------------------------------===//
MTBUF_Real<ps>, // MUBUF - GFX10.
Enc64, //===----------------------------------------------------------------------===//
SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI> {
let AssemblerPredicate=isGFX6GFX7; let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
let DecoderNamespace="GFX6GFX7"; multiclass MUBUF_Real_gfx10_with_name<bits<8> op, string opName,
string asmName> {
def _gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(opName)> {
MUBUF_Pseudo ps = !cast<MUBUF_Pseudo>(opName);
let AsmString = asmName # ps.AsmOperands;
}
}
multiclass MUBUF_Real_AllAddr_gfx10<bits<8> op> {
def _BOTHEN_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
def _IDXEN_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
def _OFFEN_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
def _OFFSET_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
}
multiclass MUBUF_Real_AllAddr_Lds_gfx10<bits<8> op> {
def _OFFSET_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>,
MUBUFLdsTable<0, NAME # "_OFFSET_gfx10">;
def _OFFEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>,
MUBUFLdsTable<0, NAME # "_OFFEN_gfx10">;
def _IDXEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>,
MUBUFLdsTable<0, NAME # "_IDXEN_gfx10">;
def _BOTHEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>,
MUBUFLdsTable<0, NAME # "_BOTHEN_gfx10">;
def _LDS_OFFSET_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFSET")>,
MUBUFLdsTable<1, NAME # "_OFFSET_gfx10">;
def _LDS_OFFEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFEN")>,
MUBUFLdsTable<1, NAME # "_OFFEN_gfx10">;
def _LDS_IDXEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>,
MUBUFLdsTable<1, NAME # "_IDXEN_gfx10">;
def _LDS_BOTHEN_gfx10 : MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>,
MUBUFLdsTable<1, NAME # "_BOTHEN_gfx10">;
}
multiclass MUBUF_Real_Atomics_gfx10<bits<8> op> :
MUBUF_Real_AllAddr_gfx10<op> {
def _BOTHEN_RTN_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>;
def _IDXEN_RTN_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN_RTN")>;
def _OFFEN_RTN_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN_RTN")>;
def _OFFSET_RTN_gfx10 :
MUBUF_Real_gfx10<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET_RTN")>;
}
} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
defm BUFFER_STORE_BYTE_D16_HI : MUBUF_Real_AllAddr_gfx10<0x019>;
defm BUFFER_STORE_SHORT_D16_HI : MUBUF_Real_AllAddr_gfx10<0x01b>;
defm BUFFER_LOAD_UBYTE_D16 : MUBUF_Real_AllAddr_gfx10<0x020>;
defm BUFFER_LOAD_UBYTE_D16_HI : MUBUF_Real_AllAddr_gfx10<0x021>;
defm BUFFER_LOAD_SBYTE_D16 : MUBUF_Real_AllAddr_gfx10<0x022>;
defm BUFFER_LOAD_SBYTE_D16_HI : MUBUF_Real_AllAddr_gfx10<0x023>;
defm BUFFER_LOAD_SHORT_D16 : MUBUF_Real_AllAddr_gfx10<0x024>;
defm BUFFER_LOAD_SHORT_D16_HI : MUBUF_Real_AllAddr_gfx10<0x025>;
// FIXME-GFX10: Add following instructions:
//defm BUFFER_LOAD_FORMAT_D16_HI_X : MUBUF_Real_AllAddr_gfx10<0x026>;
//defm BUFFER_STORE_FORMAT_D16_HI_X : MUBUF_Real_AllAddr_gfx10<0x027>;
defm BUFFER_LOAD_FORMAT_D16_X : MUBUF_Real_AllAddr_gfx10<0x080>;
defm BUFFER_LOAD_FORMAT_D16_XY : MUBUF_Real_AllAddr_gfx10<0x081>;
defm BUFFER_LOAD_FORMAT_D16_XYZ : MUBUF_Real_AllAddr_gfx10<0x082>;
defm BUFFER_LOAD_FORMAT_D16_XYZW : MUBUF_Real_AllAddr_gfx10<0x083>;
defm BUFFER_STORE_FORMAT_D16_X : MUBUF_Real_AllAddr_gfx10<0x084>;
defm BUFFER_STORE_FORMAT_D16_XY : MUBUF_Real_AllAddr_gfx10<0x085>;
defm BUFFER_STORE_FORMAT_D16_XYZ : MUBUF_Real_AllAddr_gfx10<0x086>;
defm BUFFER_STORE_FORMAT_D16_XYZW : MUBUF_Real_AllAddr_gfx10<0x087>;
def BUFFER_GL0_INV_gfx10 :
MUBUF_Real_gfx10<0x071, BUFFER_GL0_INV>;
def BUFFER_GL1_INV_gfx10 :
MUBUF_Real_gfx10<0x072, BUFFER_GL1_INV>;
//===----------------------------------------------------------------------===//
// MUBUF - GFX6, GFX7, GFX10.
//===----------------------------------------------------------------------===//
let AssemblerPredicate = isGFX6, DecoderNamespace = "GFX6" in {
multiclass MUBUF_Real_gfx6<bits<8> op> {
def _gfx6 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME)>;
}
} // End AssemblerPredicate = isGFX6, DecoderNamespace = "GFX6"
let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
multiclass MUBUF_Real_gfx7<bits<8> op> {
def _gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME)>;
}
} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"
let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
multiclass MUBUF_Real_AllAddr_gfx6_gfx7<bits<8> op> {
def _ADDR64_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64")>;
def _BOTHEN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
def _IDXEN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>;
def _OFFEN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>;
def _OFFSET_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>;
}
multiclass MUBUF_Real_AllAddr_Lds_gfx6_gfx7<bits<8> op> {
def _OFFSET_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>,
MUBUFLdsTable<0, NAME # "_OFFSET_gfx6_gfx7">;
def _ADDR64_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64")>,
MUBUFLdsTable<0, NAME # "_ADDR64_gfx6_gfx7">;
def _OFFEN_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>,
MUBUFLdsTable<0, NAME # "_OFFEN_gfx6_gfx7">;
def _IDXEN_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>,
MUBUFLdsTable<0, NAME # "_IDXEN_gfx6_gfx7">;
def _BOTHEN_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>,
MUBUFLdsTable<0, NAME # "_BOTHEN_gfx6_gfx7">;
def _LDS_OFFSET_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFSET")>,
MUBUFLdsTable<1, NAME # "_OFFSET_gfx6_gfx7">;
def _LDS_ADDR64_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_ADDR64")>,
MUBUFLdsTable<1, NAME # "_ADDR64_gfx6_gfx7">;
def _LDS_OFFEN_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFEN")>,
MUBUFLdsTable<1, NAME # "_OFFEN_gfx6_gfx7">;
def _LDS_IDXEN_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>,
MUBUFLdsTable<1, NAME # "_IDXEN_gfx6_gfx7">;
def _LDS_BOTHEN_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>,
MUBUFLdsTable<1, NAME # "_BOTHEN_gfx6_gfx7">;
}
multiclass MUBUF_Real_Atomics_gfx6_gfx7<bits<8> op> :
MUBUF_Real_AllAddr_gfx6_gfx7<op> {
def _ADDR64_RTN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64_RTN")>;
def _BOTHEN_RTN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>;
def _IDXEN_RTN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN_RTN")>;
def _OFFEN_RTN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN_RTN")>;
def _OFFSET_RTN_gfx6_gfx7 :
MUBUF_Real_gfx6_gfx7<op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET_RTN")>;
}
} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
multiclass MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<bits<8> op> :
MUBUF_Real_AllAddr_gfx6_gfx7<op>, MUBUF_Real_AllAddr_gfx10<op>;
multiclass MUBUF_Real_AllAddr_Lds_gfx6_gfx7_gfx10<bits<8> op> :
MUBUF_Real_AllAddr_Lds_gfx6_gfx7<op>, MUBUF_Real_AllAddr_Lds_gfx10<op>;
multiclass MUBUF_Real_Atomics_gfx6_gfx7_gfx10<bits<8> op> :
MUBUF_Real_Atomics_gfx6_gfx7<op>, MUBUF_Real_Atomics_gfx10<op>;
// FIXME-GFX6: Following instructions are available only on GFX6.
//defm BUFFER_ATOMIC_RSUB : MUBUF_Real_Atomics_gfx6 <0x034>;
//defm BUFFER_ATOMIC_RSUB_X2 : MUBUF_Real_Atomics_gfx6 <0x054>;
defm BUFFER_LOAD_FORMAT_X : MUBUF_Real_AllAddr_Lds_gfx6_gfx7_gfx10<0x000>;
defm BUFFER_LOAD_FORMAT_XY : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x001>;
defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x002>;
defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x003>;
defm BUFFER_STORE_FORMAT_X : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x004>;
defm BUFFER_STORE_FORMAT_XY : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x005>;
defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x006>;
defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x007>;
defm BUFFER_LOAD_UBYTE : MUBUF_Real_AllAddr_Lds_gfx6_gfx7_gfx10<0x008>;
defm BUFFER_LOAD_SBYTE : MUBUF_Real_AllAddr_Lds_gfx6_gfx7_gfx10<0x009>;
defm BUFFER_LOAD_USHORT : MUBUF_Real_AllAddr_Lds_gfx6_gfx7_gfx10<0x00a>;
defm BUFFER_LOAD_SSHORT : MUBUF_Real_AllAddr_Lds_gfx6_gfx7_gfx10<0x00b>;
defm BUFFER_LOAD_DWORD : MUBUF_Real_AllAddr_Lds_gfx6_gfx7_gfx10<0x00c>;
defm BUFFER_LOAD_DWORDX2 : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x00d>;
defm BUFFER_LOAD_DWORDX4 : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x00e>;
defm BUFFER_LOAD_DWORDX3 : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x00f>;
defm BUFFER_STORE_BYTE : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x018>;
defm BUFFER_STORE_SHORT : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x01a>;
defm BUFFER_STORE_DWORD : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x01c>;
defm BUFFER_STORE_DWORDX2 : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x01d>;
defm BUFFER_STORE_DWORDX4 : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x01e>;
defm BUFFER_STORE_DWORDX3 : MUBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x01f>;
defm BUFFER_ATOMIC_SWAP : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x030>;
defm BUFFER_ATOMIC_CMPSWAP : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x031>;
defm BUFFER_ATOMIC_ADD : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x032>;
defm BUFFER_ATOMIC_SUB : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x033>;
defm BUFFER_ATOMIC_SMIN : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x035>;
defm BUFFER_ATOMIC_UMIN : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x036>;
defm BUFFER_ATOMIC_SMAX : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x037>;
defm BUFFER_ATOMIC_UMAX : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x038>;
defm BUFFER_ATOMIC_AND : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x039>;
defm BUFFER_ATOMIC_OR : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x03a>;
defm BUFFER_ATOMIC_XOR : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x03b>;
defm BUFFER_ATOMIC_INC : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x03c>;
defm BUFFER_ATOMIC_DEC : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x03d>;
// FIXME-GFX6-GFX7-GFX10: Add following instructions:
//defm BUFFER_ATOMIC_FCMPSWAP : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x03e>;
//defm BUFFER_ATOMIC_FMIN : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x03f>;
//defm BUFFER_ATOMIC_FMAX : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x040>;
defm BUFFER_ATOMIC_SWAP_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x050>;
defm BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x051>;
defm BUFFER_ATOMIC_ADD_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x052>;
defm BUFFER_ATOMIC_SUB_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x053>;
defm BUFFER_ATOMIC_SMIN_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x055>;
defm BUFFER_ATOMIC_UMIN_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x056>;
defm BUFFER_ATOMIC_SMAX_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x057>;
defm BUFFER_ATOMIC_UMAX_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x058>;
defm BUFFER_ATOMIC_AND_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x059>;
defm BUFFER_ATOMIC_OR_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x05a>;
defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x05b>;
defm BUFFER_ATOMIC_INC_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x05c>;
defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x05d>;
// FIXME-GFX7: Need to handle hazard for BUFFER_ATOMIC_FCMPSWAP_X2 on GFX7.
// FIXME-GFX6-GFX7-GFX10: Add following instructions:
//defm BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x05e>;
//defm BUFFER_ATOMIC_FMIN_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x05f>;
//defm BUFFER_ATOMIC_FMAX_X2 : MUBUF_Real_Atomics_gfx6_gfx7_gfx10<0x060>;
defm BUFFER_WBINVL1_SC : MUBUF_Real_gfx6<0x070>;
defm BUFFER_WBINVL1_VOL : MUBUF_Real_gfx7<0x070>;
def BUFFER_WBINVL1_gfx6_gfx7 : MUBUF_Real_gfx6_gfx7<0x071, BUFFER_WBINVL1>;
//===----------------------------------------------------------------------===//
// Base ENC_MTBUF for GFX6, GFX7, GFX10.
//===----------------------------------------------------------------------===//
class Base_MTBUF_Real_gfx6_gfx7_gfx10<bits<3> op, MTBUF_Pseudo ps, int ef> :
MTBUF_Real<ps>, Enc64, SIMCInstr<ps.PseudoInstr, ef> {
let Inst{11-0} = !if(ps.has_offset, offset, ?); let Inst{11-0} = !if(ps.has_offset, offset, ?);
let Inst{12} = ps.offen; let Inst{12} = ps.offen;
let Inst{13} = ps.idxen; let Inst{13} = ps.idxen;
let Inst{14} = !if(ps.has_glc, glc, ps.glc_value); let Inst{14} = !if(ps.has_glc, glc, ps.glc_value);
let Inst{15} = ps.addr64;
let Inst{18-16} = op; let Inst{18-16} = op;
let Inst{22-19} = dfmt;
let Inst{25-23} = nfmt;
let Inst{31-26} = 0x3a; //encoding let Inst{31-26} = 0x3a; //encoding
let Inst{39-32} = !if(ps.has_vaddr, vaddr, ?); let Inst{39-32} = !if(ps.has_vaddr, vaddr, ?);
let Inst{47-40} = !if(ps.has_vdata, vdata, ?); let Inst{47-40} = !if(ps.has_vdata, vdata, ?);
let Inst{52-48} = !if(ps.has_srsrc, srsrc{6-2}, ?); let Inst{52-48} = !if(ps.has_srsrc, srsrc{6-2}, ?);
let Inst{54} = !if(ps.has_slc, slc, ?); let Inst{54} = !if(ps.has_slc, slc, ?);
let Inst{55} = !if(ps.has_tfe, tfe, ?); let Inst{55} = !if(ps.has_tfe, tfe, ?);
let Inst{63-56} = !if(ps.has_soffset, soffset, ?); let Inst{63-56} = !if(ps.has_soffset, soffset, ?);
} }
multiclass MTBUF_Real_AllAddr_si<bits<3> op> { //===----------------------------------------------------------------------===//
def _OFFSET_si : MTBUF_Real_si <op, !cast<MTBUF_Pseudo>(NAME#"_OFFSET")>; // MTBUF - GFX10.
def _ADDR64_si : MTBUF_Real_si <op, !cast<MTBUF_Pseudo>(NAME#"_ADDR64")>; //===----------------------------------------------------------------------===//
def _OFFEN_si : MTBUF_Real_si <op, !cast<MTBUF_Pseudo>(NAME#"_OFFEN")>;
def _IDXEN_si : MTBUF_Real_si <op, !cast<MTBUF_Pseudo>(NAME#"_IDXEN")>; class MTBUF_Real_gfx10<bits<4> op, MTBUF_Pseudo ps> :
def _BOTHEN_si : MTBUF_Real_si <op, !cast<MTBUF_Pseudo>(NAME#"_BOTHEN")>; Base_MTBUF_Real_gfx6_gfx7_gfx10<op{2-0}, ps, SIEncodingFamily.GFX10> {
let Inst{15} = !if(ps.has_dlc, dlc, ps.dlc_value);
let Inst{25-19} = format;
let Inst{53} = op{3};
}
let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
multiclass MTBUF_Real_AllAddr_gfx10<bits<4> op> {
def _BOTHEN_gfx10 :
MTBUF_Real_gfx10<op, !cast<MTBUF_Pseudo>(NAME#"_BOTHEN")>;
def _IDXEN_gfx10 :
MTBUF_Real_gfx10<op, !cast<MTBUF_Pseudo>(NAME#"_IDXEN")>;
def _OFFEN_gfx10 :
MTBUF_Real_gfx10<op, !cast<MTBUF_Pseudo>(NAME#"_OFFEN")>;
def _OFFSET_gfx10 :
MTBUF_Real_gfx10<op, !cast<MTBUF_Pseudo>(NAME#"_OFFSET")>;
} }
} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
defm TBUFFER_LOAD_FORMAT_X : MTBUF_Real_AllAddr_si <0>; defm TBUFFER_LOAD_FORMAT_D16_X : MTBUF_Real_AllAddr_gfx10<0x008>;
defm TBUFFER_LOAD_FORMAT_XY : MTBUF_Real_AllAddr_si <1>; defm TBUFFER_LOAD_FORMAT_D16_XY : MTBUF_Real_AllAddr_gfx10<0x009>;
defm TBUFFER_LOAD_FORMAT_XYZ : MTBUF_Real_AllAddr_si <2>; defm TBUFFER_LOAD_FORMAT_D16_XYZ : MTBUF_Real_AllAddr_gfx10<0x00a>;
defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Real_AllAddr_si <3>; defm TBUFFER_LOAD_FORMAT_D16_XYZW : MTBUF_Real_AllAddr_gfx10<0x00b>;
defm TBUFFER_STORE_FORMAT_X : MTBUF_Real_AllAddr_si <4>; defm TBUFFER_STORE_FORMAT_D16_X : MTBUF_Real_AllAddr_gfx10<0x00c>;
defm TBUFFER_STORE_FORMAT_XY : MTBUF_Real_AllAddr_si <5>; defm TBUFFER_STORE_FORMAT_D16_XY : MTBUF_Real_AllAddr_gfx10<0x00d>;
defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Real_AllAddr_si <6>; defm TBUFFER_STORE_FORMAT_D16_XYZ : MTBUF_Real_AllAddr_gfx10<0x00e>;
defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Real_AllAddr_si <7>; defm TBUFFER_STORE_FORMAT_D16_XYZW : MTBUF_Real_AllAddr_gfx10<0x00f>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// CI // MTBUF - GFX6, GFX7, GFX10.
// MTBUF - GFX6, GFX7.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class MUBUF_Real_ci <bits<7> op, MUBUF_Pseudo ps> : class MTBUF_Real_gfx6_gfx7<bits<4> op, MTBUF_Pseudo ps> :
MUBUF_Real_si<op, ps> { Base_MTBUF_Real_gfx6_gfx7_gfx10<op{2-0}, ps, SIEncodingFamily.SI> {
let AssemblerPredicate = isGFX7Only; let Inst{15} = ps.addr64;
let DecoderNamespace = "GFX7"; let Inst{22-19} = dfmt;
let Inst{25-23} = nfmt;
} }
def BUFFER_WBINVL1_VOL_ci : MUBUF_Real_ci <0x70, BUFFER_WBINVL1_VOL>; let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
multiclass MTBUF_Real_AllAddr_gfx6_gfx7<bits<4> op> {
def _ADDR64_gfx6_gfx7 :
MTBUF_Real_gfx6_gfx7<op, !cast<MTBUF_Pseudo>(NAME#"_ADDR64")>;
def _BOTHEN_gfx6_gfx7 :
MTBUF_Real_gfx6_gfx7<op, !cast<MTBUF_Pseudo>(NAME#"_BOTHEN")>;
def _IDXEN_gfx6_gfx7 :
MTBUF_Real_gfx6_gfx7<op, !cast<MTBUF_Pseudo>(NAME#"_IDXEN")>;
def _OFFEN_gfx6_gfx7 :
MTBUF_Real_gfx6_gfx7<op, !cast<MTBUF_Pseudo>(NAME#"_OFFEN")>;
def _OFFSET_gfx6_gfx7 :
MTBUF_Real_gfx6_gfx7<op, !cast<MTBUF_Pseudo>(NAME#"_OFFSET")>;
}
} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
multiclass MTBUF_Real_AllAddr_gfx6_gfx7_gfx10<bits<4> op> :
MTBUF_Real_AllAddr_gfx6_gfx7<op>, MTBUF_Real_AllAddr_gfx10<op>;
defm TBUFFER_LOAD_FORMAT_X : MTBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x000>;
defm TBUFFER_LOAD_FORMAT_XY : MTBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x001>;
defm TBUFFER_LOAD_FORMAT_XYZ : MTBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x002>;
defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x003>;
defm TBUFFER_STORE_FORMAT_X : MTBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x004>;
defm TBUFFER_STORE_FORMAT_XY : MTBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x005>;
defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x006>;
defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Real_AllAddr_gfx6_gfx7_gfx10<0x007>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// GFX8, GFX9 (VI). // GFX8, GFX9 (VI).
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class MUBUF_Real_vi <bits<7> op, MUBUF_Pseudo ps> : class MUBUF_Real_vi <bits<7> op, MUBUF_Pseudo ps> :
MUBUF_Real<op, ps>, MUBUF_Real<ps>,
Enc64, Enc64,
SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI> { SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI> {
let AssemblerPredicate = isGFX8GFX9; let AssemblerPredicate = isGFX8GFX9;
let DecoderNamespace = "GFX8"; let DecoderNamespace = "GFX8";
let Inst{11-0} = !if(ps.has_offset, offset, ?); let Inst{11-0} = !if(ps.has_offset, offset, ?);
let Inst{12} = ps.offen; let Inst{12} = ps.offen;
let Inst{13} = ps.idxen; let Inst{13} = ps.idxen;
Show All 33 Lines def _LDS_OFFEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFEN")>,
MUBUFLdsTable<1, NAME # "_OFFEN_vi">; MUBUFLdsTable<1, NAME # "_OFFEN_vi">;
def _LDS_IDXEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>, def _LDS_IDXEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>,
MUBUFLdsTable<1, NAME # "_IDXEN_vi">; MUBUFLdsTable<1, NAME # "_IDXEN_vi">;
def _LDS_BOTHEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>, def _LDS_BOTHEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>,
MUBUFLdsTable<1, NAME # "_BOTHEN_vi">; MUBUFLdsTable<1, NAME # "_BOTHEN_vi">;
} }
class MUBUF_Real_gfx80 <bits<7> op, MUBUF_Pseudo ps> : class MUBUF_Real_gfx80 <bits<7> op, MUBUF_Pseudo ps> :
MUBUF_Real<op, ps>, MUBUF_Real<ps>,
Enc64, Enc64,
SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX80> { SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX80> {
let AssemblerPredicate=HasUnpackedD16VMem; let AssemblerPredicate=HasUnpackedD16VMem;
let DecoderNamespace="GFX80_UNPACKED"; let DecoderNamespace="GFX80_UNPACKED";
let Inst{11-0} = !if(ps.has_offset, offset, ?); let Inst{11-0} = !if(ps.has_offset, offset, ?);
let Inst{12} = ps.offen; let Inst{12} = ps.offen;
let Inst{13} = ps.idxen; let Inst{13} = ps.idxen;
▲ Show 20 Lines • Show All 222 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td

//===-- FLATInstructions.td - FLAT Instruction Defintions -----------------===// //===-- FLATInstructions.td - FLAT Instruction Defintions -----------------===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def FLATAtomic : ComplexPattern<i64, 3, "SelectFlatAtomic", [], [], -10>; def FLATAtomic : ComplexPattern<i64, 3, "SelectFlatAtomic", [], [SDNPWantRoot], -10>;
def FLATOffset : ComplexPattern<i64, 3, "SelectFlatOffset<false>", [], [], -10>; def FLATOffset : ComplexPattern<i64, 3, "SelectFlatOffset<false>", [], [SDNPWantRoot], -10>;
def FLATOffsetSigned : ComplexPattern<i64, 3, "SelectFlatOffset<true>", [], [], -10>; def FLATOffsetSigned : ComplexPattern<i64, 3, "SelectFlatOffset<true>", [], [SDNPWantRoot], -10>;
def FLATSignedAtomic : ComplexPattern<i64, 3, "SelectFlatAtomicSigned", [], [], -10>; def FLATSignedAtomic : ComplexPattern<i64, 3, "SelectFlatAtomicSigned", [], [SDNPWantRoot], -10>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// FLAT classes // FLAT classes
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class FLAT_Pseudo<string opName, dag outs, dag ins, class FLAT_Pseudo<string opName, dag outs, dag ins,
string asmOps, list<dag> pattern=[]> : string asmOps, list<dag> pattern=[]> :
InstSI<outs, ins, "", pattern>, InstSI<outs, ins, "", pattern>,
Show All 24 Linesclass FLAT_Pseudo<string opName, dag outs, dag ins,
bits<1> has_saddr = 0; bits<1> has_saddr = 0;
bits<1> enabled_saddr = 0; bits<1> enabled_saddr = 0;
bits<7> saddr_value = 0; bits<7> saddr_value = 0;
bits<1> has_vaddr = 1; bits<1> has_vaddr = 1;
bits<1> has_data = 1; bits<1> has_data = 1;
bits<1> has_glc = 1; bits<1> has_glc = 1;
bits<1> glcValue = 0; bits<1> glcValue = 0;
bits<1> has_dlc = 1;
bits<1> dlcValue = 0;
let SubtargetPredicate = !if(is_flat_global, HasFlatGlobalInsts, let SubtargetPredicate = !if(is_flat_global, HasFlatGlobalInsts,
!if(is_flat_scratch, HasFlatScratchInsts, HasFlatAddressSpace)); !if(is_flat_scratch, HasFlatScratchInsts, HasFlatAddressSpace));
// TODO: M0 if it could possibly access LDS (before gfx9? only)? // TODO: M0 if it could possibly access LDS (before gfx9? only)?
let Uses = !if(is_flat_global, [EXEC], [EXEC, FLAT_SCR]); let Uses = !if(is_flat_global, [EXEC], [EXEC, FLAT_SCR]);
// Internally, FLAT instruction are executed as both an LDS and a // Internally, FLAT instruction are executed as both an LDS and a
Show All 21 Linesclass FLAT_Real <bits<7> op, FLAT_Pseudo ps> :
// encoding fields // encoding fields
bits<8> vaddr; bits<8> vaddr;
bits<8> vdata; bits<8> vdata;
bits<7> saddr; bits<7> saddr;
bits<8> vdst; bits<8> vdst;
bits<1> slc; bits<1> slc;
bits<1> glc; bits<1> glc;
bits<1> dlc;
// Only valid on gfx9 // Only valid on gfx9
bits<1> lds = 0; // XXX - What does this actually do? bits<1> lds = 0; // XXX - What does this actually do?
// Segment, 00=flat, 01=scratch, 10=global, 11=reserved // Segment, 00=flat, 01=scratch, 10=global, 11=reserved
bits<2> seg = !if(ps.is_flat_global, 0b10, bits<2> seg = !if(ps.is_flat_global, 0b10,
!if(ps.is_flat_scratch, 0b01, 0)); !if(ps.is_flat_scratch, 0b01, 0));
Show All 37 Linesclass FLAT_Load_Pseudo <string opName, RegisterClass regClass,
opName, opName,
(outs regClass:$vdst), (outs regClass:$vdst),
!con( !con(
!con( !con(
!con( !con(
!con((ins VReg_64:$vaddr), !con((ins VReg_64:$vaddr),
!if(EnableSaddr, (ins SReg_64:$saddr), (ins))), !if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
(ins !if(HasSignedOffset,offset_s13,offset_u12):$offset)), (ins !if(HasSignedOffset,offset_s13,offset_u12):$offset)),
(ins GLC:$glc, SLC:$slc)), (ins GLC:$glc, SLC:$slc, DLC:$dlc)),
!if(HasTiedOutput, (ins regClass:$vdst_in), (ins))), !if(HasTiedOutput, (ins regClass:$vdst_in), (ins))),
" $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc"> { " $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
let has_data = 0; let has_data = 0;
let mayLoad = 1; let mayLoad = 1;
let has_saddr = HasSaddr; let has_saddr = HasSaddr;
let enabled_saddr = EnableSaddr; let enabled_saddr = EnableSaddr;
let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", ""); let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
let maybeAtomic = 1; let maybeAtomic = 1;
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", ""); let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
let DisableEncoding = !if(HasTiedOutput, "$vdst_in", ""); let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
} }
class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass, class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
bit HasSignedOffset = 0, bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo< bit HasSignedOffset = 0, bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
opName, opName,
(outs), (outs),
!con( !con(
!con( !con(
!con((ins VReg_64:$vaddr, vdataClass:$vdata), !con((ins VReg_64:$vaddr, vdataClass:$vdata),
!if(EnableSaddr, (ins SReg_64:$saddr), (ins))), !if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
(ins !if(HasSignedOffset,offset_s13,offset_u12):$offset)), (ins !if(HasSignedOffset,offset_s13,offset_u12):$offset)),
(ins GLC:$glc, SLC:$slc)), (ins GLC:$glc, SLC:$slc, DLC:$dlc)),
" $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc"> { " $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
let mayLoad = 0; let mayLoad = 0;
let mayStore = 1; let mayStore = 1;
let has_vdst = 0; let has_vdst = 0;
let has_saddr = HasSaddr; let has_saddr = HasSaddr;
let enabled_saddr = EnableSaddr; let enabled_saddr = EnableSaddr;
let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", ""); let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
let maybeAtomic = 1; let maybeAtomic = 1;
} }
Show All 16 Linesmulticlass FLAT_Global_Store_Pseudo<string opName, RegisterClass regClass> {
} }
} }
class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass, class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
bit EnableSaddr = 0>: FLAT_Pseudo< bit EnableSaddr = 0>: FLAT_Pseudo<
opName, opName,
(outs regClass:$vdst), (outs regClass:$vdst),
!if(EnableSaddr, !if(EnableSaddr,
(ins SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, SLC:$slc), (ins SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
(ins VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, SLC:$slc)), (ins VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
" $vdst, "#!if(EnableSaddr, "off", "$vaddr")#!if(EnableSaddr, ", $saddr", ", off")#"$offset$glc$slc"> { " $vdst, "#!if(EnableSaddr, "off", "$vaddr")#!if(EnableSaddr, ", $saddr", ", off")#"$offset$glc$slc$dlc"> {
let has_data = 0; let has_data = 0;
let mayLoad = 1; let mayLoad = 1;
let has_saddr = 1; let has_saddr = 1;
let enabled_saddr = EnableSaddr; let enabled_saddr = EnableSaddr;
let has_vaddr = !if(EnableSaddr, 0, 1); let has_vaddr = !if(EnableSaddr, 0, 1);
let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", ""); let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");
let maybeAtomic = 1; let maybeAtomic = 1;
} }
class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit EnableSaddr = 0> : FLAT_Pseudo< class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit EnableSaddr = 0> : FLAT_Pseudo<
opName, opName,
(outs), (outs),
!if(EnableSaddr, !if(EnableSaddr,
(ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, SLC:$slc), (ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
(ins vdataClass:$vdata, VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, SLC:$slc)), (ins vdataClass:$vdata, VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
" "#!if(EnableSaddr, "off", "$vaddr")#", $vdata, "#!if(EnableSaddr, "$saddr", "off")#"$offset$glc$slc"> { " "#!if(EnableSaddr, "off", "$vaddr")#", $vdata, "#!if(EnableSaddr, "$saddr", "off")#"$offset$glc$slc$dlc"> {
let mayLoad = 0; let mayLoad = 0;
let mayStore = 1; let mayStore = 1;
let has_vdst = 0; let has_vdst = 0;
let has_saddr = 1; let has_saddr = 1;
let enabled_saddr = EnableSaddr; let enabled_saddr = EnableSaddr;
let has_vaddr = !if(EnableSaddr, 0, 1); let has_vaddr = !if(EnableSaddr, 0, 1);
let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", ""); let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");
let maybeAtomic = 1; let maybeAtomic = 1;
Show All 15 Lines
class FLAT_AtomicNoRet_Pseudo<string opName, dag outs, dag ins, class FLAT_AtomicNoRet_Pseudo<string opName, dag outs, dag ins,
string asm, list<dag> pattern = []> : string asm, list<dag> pattern = []> :
FLAT_Pseudo<opName, outs, ins, asm, pattern> { FLAT_Pseudo<opName, outs, ins, asm, pattern> {
let mayLoad = 1; let mayLoad = 1;
let mayStore = 1; let mayStore = 1;
let has_glc = 0; let has_glc = 0;
let glcValue = 0; let glcValue = 0;
let has_dlc = 0;
let dlcValue = 0;
let has_vdst = 0; let has_vdst = 0;
let maybeAtomic = 1; let maybeAtomic = 1;
} }
class FLAT_AtomicRet_Pseudo<string opName, dag outs, dag ins, class FLAT_AtomicRet_Pseudo<string opName, dag outs, dag ins,
string asm, list<dag> pattern = []> string asm, list<dag> pattern = []>
: FLAT_AtomicNoRet_Pseudo<opName, outs, ins, asm, pattern> { : FLAT_AtomicNoRet_Pseudo<opName, outs, ins, asm, pattern> {
let hasPostISelHook = 1; let hasPostISelHook = 1;
let has_vdst = 1; let has_vdst = 1;
let glcValue = 1; let glcValue = 1;
let dlcValue = 0;
let PseudoInstr = NAME # "_RTN"; let PseudoInstr = NAME # "_RTN";
} }
multiclass FLAT_Atomic_Pseudo< multiclass FLAT_Atomic_Pseudo<
string opName, string opName,
RegisterClass vdst_rc, RegisterClass vdst_rc,
ValueType vt, ValueType vt,
SDPatternOperator atomic = null_frag, SDPatternOperator atomic = null_frag,
▲ Show 20 Lines • Show All 218 Lines • ▼ Show 20 Linesdefm FLAT_ATOMIC_XOR_X2 : FLAT_Atomic_Pseudo <"flat_atomic_xor_x2",
VReg_64, i64, atomic_xor_flat>; VReg_64, i64, atomic_xor_flat>;
defm FLAT_ATOMIC_INC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_inc_x2", defm FLAT_ATOMIC_INC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_inc_x2",
VReg_64, i64, atomic_inc_flat>; VReg_64, i64, atomic_inc_flat>;
defm FLAT_ATOMIC_DEC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_dec_x2", defm FLAT_ATOMIC_DEC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_dec_x2",
VReg_64, i64, atomic_dec_flat>; VReg_64, i64, atomic_dec_flat>;
// GFX7-only flat instructions. // GFX7-, GFX10-only flat instructions.
let SubtargetPredicate = isGFX7Only in { let SubtargetPredicate = isGFX7GFX10 in {
defm FLAT_ATOMIC_FCMPSWAP : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap", defm FLAT_ATOMIC_FCMPSWAP : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap",
VGPR_32, f32, null_frag, v2f32, VReg_64>; VGPR_32, f32, null_frag, v2f32, VReg_64>;
defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap_x2", defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap_x2",
VReg_64, f64, null_frag, v2f64, VReg_128>; VReg_64, f64, null_frag, v2f64, VReg_128>;
defm FLAT_ATOMIC_FMIN : FLAT_Atomic_Pseudo <"flat_atomic_fmin", defm FLAT_ATOMIC_FMIN : FLAT_Atomic_Pseudo <"flat_atomic_fmin",
VGPR_32, f32>; VGPR_32, f32>;
defm FLAT_ATOMIC_FMAX : FLAT_Atomic_Pseudo <"flat_atomic_fmax", defm FLAT_ATOMIC_FMAX : FLAT_Atomic_Pseudo <"flat_atomic_fmax",
VGPR_32, f32>; VGPR_32, f32>;
defm FLAT_ATOMIC_FMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmin_x2", defm FLAT_ATOMIC_FMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmin_x2",
VReg_64, f64>; VReg_64, f64>;
defm FLAT_ATOMIC_FMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmax_x2", defm FLAT_ATOMIC_FMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmax_x2",
VReg_64, f64>; VReg_64, f64>;
} // End SubtargetPredicate = isGFX7Only } // End SubtargetPredicate = isGFX7GFX10
let SubtargetPredicate = HasFlatGlobalInsts in { let SubtargetPredicate = HasFlatGlobalInsts in {
defm GLOBAL_LOAD_UBYTE : FLAT_Global_Load_Pseudo <"global_load_ubyte", VGPR_32>; defm GLOBAL_LOAD_UBYTE : FLAT_Global_Load_Pseudo <"global_load_ubyte", VGPR_32>;
defm GLOBAL_LOAD_SBYTE : FLAT_Global_Load_Pseudo <"global_load_sbyte", VGPR_32>; defm GLOBAL_LOAD_SBYTE : FLAT_Global_Load_Pseudo <"global_load_sbyte", VGPR_32>;
defm GLOBAL_LOAD_USHORT : FLAT_Global_Load_Pseudo <"global_load_ushort", VGPR_32>; defm GLOBAL_LOAD_USHORT : FLAT_Global_Load_Pseudo <"global_load_ushort", VGPR_32>;
defm GLOBAL_LOAD_SSHORT : FLAT_Global_Load_Pseudo <"global_load_sshort", VGPR_32>; defm GLOBAL_LOAD_SSHORT : FLAT_Global_Load_Pseudo <"global_load_sshort", VGPR_32>;
defm GLOBAL_LOAD_DWORD : FLAT_Global_Load_Pseudo <"global_load_dword", VGPR_32>; defm GLOBAL_LOAD_DWORD : FLAT_Global_Load_Pseudo <"global_load_dword", VGPR_32>;
defm GLOBAL_LOAD_DWORDX2 : FLAT_Global_Load_Pseudo <"global_load_dwordx2", VReg_64>; defm GLOBAL_LOAD_DWORDX2 : FLAT_Global_Load_Pseudo <"global_load_dwordx2", VReg_64>;
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defm SCRATCH_STORE_DWORDX3 : FLAT_Scratch_Store_Pseudo <"scratch_store_dwordx3", VReg_96>; defm SCRATCH_STORE_DWORDX3 : FLAT_Scratch_Store_Pseudo <"scratch_store_dwordx3", VReg_96>;
defm SCRATCH_STORE_DWORDX4 : FLAT_Scratch_Store_Pseudo <"scratch_store_dwordx4", VReg_128>; defm SCRATCH_STORE_DWORDX4 : FLAT_Scratch_Store_Pseudo <"scratch_store_dwordx4", VReg_128>;
defm SCRATCH_STORE_BYTE_D16_HI : FLAT_Scratch_Store_Pseudo <"scratch_store_byte_d16_hi", VGPR_32>; defm SCRATCH_STORE_BYTE_D16_HI : FLAT_Scratch_Store_Pseudo <"scratch_store_byte_d16_hi", VGPR_32>;
defm SCRATCH_STORE_SHORT_D16_HI : FLAT_Scratch_Store_Pseudo <"scratch_store_short_d16_hi", VGPR_32>; defm SCRATCH_STORE_SHORT_D16_HI : FLAT_Scratch_Store_Pseudo <"scratch_store_short_d16_hi", VGPR_32>;
} // End SubtargetPredicate = HasFlatScratchInsts } // End SubtargetPredicate = HasFlatScratchInsts
let SubtargetPredicate = isGFX10Plus, is_flat_global = 1 in {
defm GLOBAL_ATOMIC_FCMPSWAP :
FLAT_Global_Atomic_Pseudo<"global_atomic_fcmpswap", VGPR_32, f32>;
defm GLOBAL_ATOMIC_FMIN :
FLAT_Global_Atomic_Pseudo<"global_atomic_fmin", VGPR_32, f32>;
defm GLOBAL_ATOMIC_FMAX :
FLAT_Global_Atomic_Pseudo<"global_atomic_fmax", VGPR_32, f32>;
defm GLOBAL_ATOMIC_FCMPSWAP_X2 :
FLAT_Global_Atomic_Pseudo<"global_atomic_fcmpswap_x2", VReg_64, f64>;
defm GLOBAL_ATOMIC_FMIN_X2 :
FLAT_Global_Atomic_Pseudo<"global_atomic_fmin_x2", VReg_64, f64>;
defm GLOBAL_ATOMIC_FMAX_X2 :
FLAT_Global_Atomic_Pseudo<"global_atomic_fmax_x2", VReg_64, f64>;
} // End SubtargetPredicate = isGFX10Plus, is_flat_global = 1
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Flat Patterns // Flat Patterns
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Patterns for global loads with no offset. // Patterns for global loads with no offset.
class FlatLoadPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < class FlatLoadPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
(vt (node (FLATOffset i64:$vaddr, i16:$offset, i1:$slc))), (vt (node (FLATOffset i64:$vaddr, i16:$offset, i1:$slc))),
(inst $vaddr, $offset, 0, $slc) (inst $vaddr, $offset, 0, 0, $slc)
>; >;
class FlatLoadPat_D16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < class FlatLoadPat_D16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
(node (FLATOffset i64:$vaddr, i16:$offset, i1:$slc), vt:$in), (node (FLATOffset i64:$vaddr, i16:$offset, i1:$slc), vt:$in),
(inst $vaddr, $offset, 0, $slc, $in) (inst $vaddr, $offset, 0, 0, $slc, $in)
>; >;
class FlatSignedLoadPat_D16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < class FlatSignedLoadPat_D16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
(node (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc), vt:$in), (node (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc), vt:$in),
(inst $vaddr, $offset, 0, $slc, $in) (inst $vaddr, $offset, 0, 0, $slc, $in)
>; >;
class FlatLoadAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < class FlatLoadAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
(vt (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc))), (vt (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc))),
(inst $vaddr, $offset, 0, $slc) (inst $vaddr, $offset, 0, 0, $slc)
>; >;
class FlatLoadSignedPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < class FlatLoadSignedPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
(vt (node (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc))), (vt (node (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc))),
(inst $vaddr, $offset, 0, $slc) (inst $vaddr, $offset, 0, 0, $slc)
>; >;
class FlatStorePat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < class FlatStorePat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
(node vt:$data, (FLATOffset i64:$vaddr, i16:$offset, i1:$slc)), (node vt:$data, (FLATOffset i64:$vaddr, i16:$offset, i1:$slc)),
(inst $vaddr, $data, $offset, 0, $slc) (inst $vaddr, $data, $offset, 0, 0, $slc)
>; >;
class FlatStoreSignedPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < class FlatStoreSignedPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
(node vt:$data, (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc)), (node vt:$data, (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc)),
(inst $vaddr, $data, $offset, 0, $slc) (inst $vaddr, $data, $offset, 0, 0, $slc)
>; >;
class FlatStoreAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < class FlatStoreAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
// atomic store follows atomic binop convention so the address comes // atomic store follows atomic binop convention so the address comes
// first. // first.
(node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), vt:$data), (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), vt:$data),
(inst $vaddr, $data, $offset, 0, $slc) (inst $vaddr, $data, $offset, 0, 0, $slc)
>; >;
class FlatStoreSignedAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < class FlatStoreSignedAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat <
// atomic store follows atomic binop convention so the address comes // atomic store follows atomic binop convention so the address comes
// first. // first.
(node (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), vt:$data), (node (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), vt:$data),
(inst $vaddr, $data, $offset, 0, $slc) (inst $vaddr, $data, $offset, 0, 0, $slc)
>; >;
class FlatAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt, class FlatAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt,
ValueType data_vt = vt> : GCNPat < ValueType data_vt = vt> : GCNPat <
(vt (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$data)), (vt (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$data)),
(inst $vaddr, $data, $offset, $slc) (inst $vaddr, $data, $offset, $slc)
>; >;
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defm SCRATCH_LOAD_SHORT_D16 : FLAT_Real_AllAddr_vi <0x24>; defm SCRATCH_LOAD_SHORT_D16 : FLAT_Real_AllAddr_vi <0x24>;
defm SCRATCH_LOAD_SHORT_D16_HI : FLAT_Real_AllAddr_vi <0x25>; defm SCRATCH_LOAD_SHORT_D16_HI : FLAT_Real_AllAddr_vi <0x25>;
defm SCRATCH_STORE_SHORT : FLAT_Real_AllAddr_vi <0x1a>; defm SCRATCH_STORE_SHORT : FLAT_Real_AllAddr_vi <0x1a>;
defm SCRATCH_STORE_SHORT_D16_HI : FLAT_Real_AllAddr_vi <0x1b>; defm SCRATCH_STORE_SHORT_D16_HI : FLAT_Real_AllAddr_vi <0x1b>;
defm SCRATCH_STORE_DWORD : FLAT_Real_AllAddr_vi <0x1c>; defm SCRATCH_STORE_DWORD : FLAT_Real_AllAddr_vi <0x1c>;
defm SCRATCH_STORE_DWORDX2 : FLAT_Real_AllAddr_vi <0x1d>; defm SCRATCH_STORE_DWORDX2 : FLAT_Real_AllAddr_vi <0x1d>;
defm SCRATCH_STORE_DWORDX3 : FLAT_Real_AllAddr_vi <0x1e>; defm SCRATCH_STORE_DWORDX3 : FLAT_Real_AllAddr_vi <0x1e>;
defm SCRATCH_STORE_DWORDX4 : FLAT_Real_AllAddr_vi <0x1f>; defm SCRATCH_STORE_DWORDX4 : FLAT_Real_AllAddr_vi <0x1f>;
//===----------------------------------------------------------------------===//
// GFX10.
//===----------------------------------------------------------------------===//
class FLAT_Real_gfx10<bits<7> op, FLAT_Pseudo ps> :
FLAT_Real<op, ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX10> {
let AssemblerPredicate = isGFX10Plus;
let DecoderNamespace = "GFX10";
let Inst{11-0} = {offset{12}, offset{10-0}};
let Inst{12} = !if(ps.has_dlc, dlc, ps.dlcValue);
let Inst{54-48} = !if(ps.has_saddr, !if(ps.enabled_saddr, saddr, 0x7d), 0x7d);
let Inst{55} = 0;
}
multiclass FLAT_Real_Base_gfx10<bits<7> op> {
def _gfx10 :
FLAT_Real_gfx10<op, !cast<FLAT_Pseudo>(NAME)>;
}
multiclass FLAT_Real_RTN_gfx10<bits<7> op> {
def _RTN_gfx10 :
FLAT_Real_gfx10<op, !cast<FLAT_Pseudo>(NAME#"_RTN")>;
}
multiclass FLAT_Real_SADDR_gfx10<bits<7> op> {
def _SADDR_gfx10 :
FLAT_Real_gfx10<op, !cast<FLAT_Pseudo>(NAME#"_SADDR")>;
}
multiclass FLAT_Real_SADDR_RTN_gfx10<bits<7> op> {
def _SADDR_RTN_gfx10 :
FLAT_Real_gfx10<op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN")>;
}
multiclass FLAT_Real_AllAddr_gfx10<bits<7> op> :
FLAT_Real_Base_gfx10<op>,
FLAT_Real_SADDR_gfx10<op>;
multiclass FLAT_Real_Atomics_gfx10<bits<7> op> :
FLAT_Real_Base_gfx10<op>,
FLAT_Real_RTN_gfx10<op>;
multiclass FLAT_Real_GlblAtomics_gfx10<bits<7> op> :
FLAT_Real_AllAddr_gfx10<op>,
FLAT_Real_RTN_gfx10<op>,
FLAT_Real_SADDR_RTN_gfx10<op>;
// ENC_FLAT.
defm FLAT_LOAD_UBYTE : FLAT_Real_Base_gfx10<0x008>;
defm FLAT_LOAD_SBYTE : FLAT_Real_Base_gfx10<0x009>;
defm FLAT_LOAD_USHORT : FLAT_Real_Base_gfx10<0x00a>;
defm FLAT_LOAD_SSHORT : FLAT_Real_Base_gfx10<0x00b>;
defm FLAT_LOAD_DWORD : FLAT_Real_Base_gfx10<0x00c>;
defm FLAT_LOAD_DWORDX2 : FLAT_Real_Base_gfx10<0x00d>;
defm FLAT_LOAD_DWORDX4 : FLAT_Real_Base_gfx10<0x00e>;
defm FLAT_LOAD_DWORDX3 : FLAT_Real_Base_gfx10<0x00f>;
defm FLAT_STORE_BYTE : FLAT_Real_Base_gfx10<0x018>;
defm FLAT_STORE_BYTE_D16_HI : FLAT_Real_Base_gfx10<0x019>;
defm FLAT_STORE_SHORT : FLAT_Real_Base_gfx10<0x01a>;
defm FLAT_STORE_SHORT_D16_HI : FLAT_Real_Base_gfx10<0x01b>;
defm FLAT_STORE_DWORD : FLAT_Real_Base_gfx10<0x01c>;
defm FLAT_STORE_DWORDX2 : FLAT_Real_Base_gfx10<0x01d>;
defm FLAT_STORE_DWORDX4 : FLAT_Real_Base_gfx10<0x01e>;
defm FLAT_STORE_DWORDX3 : FLAT_Real_Base_gfx10<0x01f>;
defm FLAT_LOAD_UBYTE_D16 : FLAT_Real_Base_gfx10<0x020>;
defm FLAT_LOAD_UBYTE_D16_HI : FLAT_Real_Base_gfx10<0x021>;
defm FLAT_LOAD_SBYTE_D16 : FLAT_Real_Base_gfx10<0x022>;
defm FLAT_LOAD_SBYTE_D16_HI : FLAT_Real_Base_gfx10<0x023>;
defm FLAT_LOAD_SHORT_D16 : FLAT_Real_Base_gfx10<0x024>;
defm FLAT_LOAD_SHORT_D16_HI : FLAT_Real_Base_gfx10<0x025>;
defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_gfx10<0x030>;
defm FLAT_ATOMIC_CMPSWAP : FLAT_Real_Atomics_gfx10<0x031>;
defm FLAT_ATOMIC_ADD : FLAT_Real_Atomics_gfx10<0x032>;
defm FLAT_ATOMIC_SUB : FLAT_Real_Atomics_gfx10<0x033>;
defm FLAT_ATOMIC_SMIN : FLAT_Real_Atomics_gfx10<0x035>;
defm FLAT_ATOMIC_UMIN : FLAT_Real_Atomics_gfx10<0x036>;
defm FLAT_ATOMIC_SMAX : FLAT_Real_Atomics_gfx10<0x037>;
defm FLAT_ATOMIC_UMAX : FLAT_Real_Atomics_gfx10<0x038>;
defm FLAT_ATOMIC_AND : FLAT_Real_Atomics_gfx10<0x039>;
defm FLAT_ATOMIC_OR : FLAT_Real_Atomics_gfx10<0x03a>;
defm FLAT_ATOMIC_XOR : FLAT_Real_Atomics_gfx10<0x03b>;
defm FLAT_ATOMIC_INC : FLAT_Real_Atomics_gfx10<0x03c>;
defm FLAT_ATOMIC_DEC : FLAT_Real_Atomics_gfx10<0x03d>;
defm FLAT_ATOMIC_FCMPSWAP : FLAT_Real_Atomics_gfx10<0x03e>;
defm FLAT_ATOMIC_FMIN : FLAT_Real_Atomics_gfx10<0x03f>;
defm FLAT_ATOMIC_FMAX : FLAT_Real_Atomics_gfx10<0x040>;
defm FLAT_ATOMIC_SWAP_X2 : FLAT_Real_Atomics_gfx10<0x050>;
defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_Real_Atomics_gfx10<0x051>;
defm FLAT_ATOMIC_ADD_X2 : FLAT_Real_Atomics_gfx10<0x052>;
defm FLAT_ATOMIC_SUB_X2 : FLAT_Real_Atomics_gfx10<0x053>;
defm FLAT_ATOMIC_SMIN_X2 : FLAT_Real_Atomics_gfx10<0x055>;
defm FLAT_ATOMIC_UMIN_X2 : FLAT_Real_Atomics_gfx10<0x056>;
defm FLAT_ATOMIC_SMAX_X2 : FLAT_Real_Atomics_gfx10<0x057>;
defm FLAT_ATOMIC_UMAX_X2 : FLAT_Real_Atomics_gfx10<0x058>;
defm FLAT_ATOMIC_AND_X2 : FLAT_Real_Atomics_gfx10<0x059>;
defm FLAT_ATOMIC_OR_X2 : FLAT_Real_Atomics_gfx10<0x05a>;
defm FLAT_ATOMIC_XOR_X2 : FLAT_Real_Atomics_gfx10<0x05b>;
defm FLAT_ATOMIC_INC_X2 : FLAT_Real_Atomics_gfx10<0x05c>;
defm FLAT_ATOMIC_DEC_X2 : FLAT_Real_Atomics_gfx10<0x05d>;
defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_Real_Atomics_gfx10<0x05e>;
defm FLAT_ATOMIC_FMIN_X2 : FLAT_Real_Atomics_gfx10<0x05f>;
defm FLAT_ATOMIC_FMAX_X2 : FLAT_Real_Atomics_gfx10<0x060>;
// ENC_FLAT_GLBL.
defm GLOBAL_LOAD_UBYTE : FLAT_Real_AllAddr_gfx10<0x008>;
defm GLOBAL_LOAD_SBYTE : FLAT_Real_AllAddr_gfx10<0x009>;
defm GLOBAL_LOAD_USHORT : FLAT_Real_AllAddr_gfx10<0x00a>;
defm GLOBAL_LOAD_SSHORT : FLAT_Real_AllAddr_gfx10<0x00b>;
defm GLOBAL_LOAD_DWORD : FLAT_Real_AllAddr_gfx10<0x00c>;
defm GLOBAL_LOAD_DWORDX2 : FLAT_Real_AllAddr_gfx10<0x00d>;
defm GLOBAL_LOAD_DWORDX4 : FLAT_Real_AllAddr_gfx10<0x00e>;
defm GLOBAL_LOAD_DWORDX3 : FLAT_Real_AllAddr_gfx10<0x00f>;
defm GLOBAL_STORE_BYTE : FLAT_Real_AllAddr_gfx10<0x018>;
defm GLOBAL_STORE_BYTE_D16_HI : FLAT_Real_AllAddr_gfx10<0x019>;
defm GLOBAL_STORE_SHORT : FLAT_Real_AllAddr_gfx10<0x01a>;
defm GLOBAL_STORE_SHORT_D16_HI : FLAT_Real_AllAddr_gfx10<0x01b>;
defm GLOBAL_STORE_DWORD : FLAT_Real_AllAddr_gfx10<0x01c>;
defm GLOBAL_STORE_DWORDX2 : FLAT_Real_AllAddr_gfx10<0x01d>;
defm GLOBAL_STORE_DWORDX4 : FLAT_Real_AllAddr_gfx10<0x01e>;
defm GLOBAL_STORE_DWORDX3 : FLAT_Real_AllAddr_gfx10<0x01f>;
defm GLOBAL_LOAD_UBYTE_D16 : FLAT_Real_AllAddr_gfx10<0x020>;
defm GLOBAL_LOAD_UBYTE_D16_HI : FLAT_Real_AllAddr_gfx10<0x021>;
defm GLOBAL_LOAD_SBYTE_D16 : FLAT_Real_AllAddr_gfx10<0x022>;
defm GLOBAL_LOAD_SBYTE_D16_HI : FLAT_Real_AllAddr_gfx10<0x023>;
defm GLOBAL_LOAD_SHORT_D16 : FLAT_Real_AllAddr_gfx10<0x024>;
defm GLOBAL_LOAD_SHORT_D16_HI : FLAT_Real_AllAddr_gfx10<0x025>;
defm GLOBAL_ATOMIC_SWAP : FLAT_Real_GlblAtomics_gfx10<0x030>;
defm GLOBAL_ATOMIC_CMPSWAP : FLAT_Real_GlblAtomics_gfx10<0x031>;
defm GLOBAL_ATOMIC_ADD : FLAT_Real_GlblAtomics_gfx10<0x032>;
defm GLOBAL_ATOMIC_SUB : FLAT_Real_GlblAtomics_gfx10<0x033>;
defm GLOBAL_ATOMIC_SMIN : FLAT_Real_GlblAtomics_gfx10<0x035>;
defm GLOBAL_ATOMIC_UMIN : FLAT_Real_GlblAtomics_gfx10<0x036>;
defm GLOBAL_ATOMIC_SMAX : FLAT_Real_GlblAtomics_gfx10<0x037>;
defm GLOBAL_ATOMIC_UMAX : FLAT_Real_GlblAtomics_gfx10<0x038>;
defm GLOBAL_ATOMIC_AND : FLAT_Real_GlblAtomics_gfx10<0x039>;
defm GLOBAL_ATOMIC_OR : FLAT_Real_GlblAtomics_gfx10<0x03a>;
defm GLOBAL_ATOMIC_XOR : FLAT_Real_GlblAtomics_gfx10<0x03b>;
defm GLOBAL_ATOMIC_INC : FLAT_Real_GlblAtomics_gfx10<0x03c>;
defm GLOBAL_ATOMIC_DEC : FLAT_Real_GlblAtomics_gfx10<0x03d>;
defm GLOBAL_ATOMIC_FCMPSWAP : FLAT_Real_GlblAtomics_gfx10<0x03e>;
defm GLOBAL_ATOMIC_FMIN : FLAT_Real_GlblAtomics_gfx10<0x03f>;
defm GLOBAL_ATOMIC_FMAX : FLAT_Real_GlblAtomics_gfx10<0x040>;
defm GLOBAL_ATOMIC_SWAP_X2 : FLAT_Real_GlblAtomics_gfx10<0x050>;
defm GLOBAL_ATOMIC_CMPSWAP_X2 : FLAT_Real_GlblAtomics_gfx10<0x051>;
defm GLOBAL_ATOMIC_ADD_X2 : FLAT_Real_GlblAtomics_gfx10<0x052>;
defm GLOBAL_ATOMIC_SUB_X2 : FLAT_Real_GlblAtomics_gfx10<0x053>;
defm GLOBAL_ATOMIC_SMIN_X2 : FLAT_Real_GlblAtomics_gfx10<0x055>;
defm GLOBAL_ATOMIC_UMIN_X2 : FLAT_Real_GlblAtomics_gfx10<0x056>;
defm GLOBAL_ATOMIC_SMAX_X2 : FLAT_Real_GlblAtomics_gfx10<0x057>;
defm GLOBAL_ATOMIC_UMAX_X2 : FLAT_Real_GlblAtomics_gfx10<0x058>;
defm GLOBAL_ATOMIC_AND_X2 : FLAT_Real_GlblAtomics_gfx10<0x059>;
defm GLOBAL_ATOMIC_OR_X2 : FLAT_Real_GlblAtomics_gfx10<0x05a>;
defm GLOBAL_ATOMIC_XOR_X2 : FLAT_Real_GlblAtomics_gfx10<0x05b>;
defm GLOBAL_ATOMIC_INC_X2 : FLAT_Real_GlblAtomics_gfx10<0x05c>;
defm GLOBAL_ATOMIC_DEC_X2 : FLAT_Real_GlblAtomics_gfx10<0x05d>;
defm GLOBAL_ATOMIC_FCMPSWAP_X2 : FLAT_Real_GlblAtomics_gfx10<0x05e>;
defm GLOBAL_ATOMIC_FMIN_X2 : FLAT_Real_GlblAtomics_gfx10<0x05f>;
defm GLOBAL_ATOMIC_FMAX_X2 : FLAT_Real_GlblAtomics_gfx10<0x060>;
// ENC_FLAT_SCRATCH.
defm SCRATCH_LOAD_UBYTE : FLAT_Real_AllAddr_gfx10<0x008>;
defm SCRATCH_LOAD_SBYTE : FLAT_Real_AllAddr_gfx10<0x009>;
defm SCRATCH_LOAD_USHORT : FLAT_Real_AllAddr_gfx10<0x00a>;
defm SCRATCH_LOAD_SSHORT : FLAT_Real_AllAddr_gfx10<0x00b>;
defm SCRATCH_LOAD_DWORD : FLAT_Real_AllAddr_gfx10<0x00c>;
defm SCRATCH_LOAD_DWORDX2 : FLAT_Real_AllAddr_gfx10<0x00d>;
defm SCRATCH_LOAD_DWORDX4 : FLAT_Real_AllAddr_gfx10<0x00e>;
defm SCRATCH_LOAD_DWORDX3 : FLAT_Real_AllAddr_gfx10<0x00f>;
defm SCRATCH_STORE_BYTE : FLAT_Real_AllAddr_gfx10<0x018>;
defm SCRATCH_STORE_BYTE_D16_HI : FLAT_Real_AllAddr_gfx10<0x019>;
defm SCRATCH_STORE_SHORT : FLAT_Real_AllAddr_gfx10<0x01a>;
defm SCRATCH_STORE_SHORT_D16_HI : FLAT_Real_AllAddr_gfx10<0x01b>;
defm SCRATCH_STORE_DWORD : FLAT_Real_AllAddr_gfx10<0x01c>;
defm SCRATCH_STORE_DWORDX2 : FLAT_Real_AllAddr_gfx10<0x01d>;
defm SCRATCH_STORE_DWORDX4 : FLAT_Real_AllAddr_gfx10<0x01e>;
defm SCRATCH_STORE_DWORDX3 : FLAT_Real_AllAddr_gfx10<0x01f>;
defm SCRATCH_LOAD_UBYTE_D16 : FLAT_Real_AllAddr_gfx10<0x020>;
defm SCRATCH_LOAD_UBYTE_D16_HI : FLAT_Real_AllAddr_gfx10<0x021>;
defm SCRATCH_LOAD_SBYTE_D16 : FLAT_Real_AllAddr_gfx10<0x022>;
defm SCRATCH_LOAD_SBYTE_D16_HI : FLAT_Real_AllAddr_gfx10<0x023>;
defm SCRATCH_LOAD_SHORT_D16 : FLAT_Real_AllAddr_gfx10<0x024>;
defm SCRATCH_LOAD_SHORT_D16_HI : FLAT_Real_AllAddr_gfx10<0x025>;

llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h

Show All 35 Linesprivate:
void printU4ImmOperand(const MCInst *MI, unsigned OpNo, void printU4ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU16ImmOperand(const MCInst *MI, unsigned OpNo, void printU16ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printS13ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printS13ImmDecOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printU32ImmOperand(const MCInst *MI, unsigned OpNo, void printU32ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
void printNamedBit(const MCInst *MI, unsigned OpNo, raw_ostream &O, void printNamedBit(const MCInst *MI, unsigned OpNo, raw_ostream &O,
StringRef BitName); StringRef BitName);
void printOffen(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printOffen(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printIdxen(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printIdxen(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printAddr64(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printAddr64(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printMBUFOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printMBUFOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
Show All 9 Linesprivate:
void printSMRDOffset8(const MCInst *MI, unsigned OpNo, void printSMRDOffset8(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
void printSMRDOffset20(const MCInst *MI, unsigned OpNo, void printSMRDOffset20(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo, void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
void printGDS(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, void printGDS(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O); raw_ostream &O);
void printDLC(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printGLC(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, void printGLC(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O); raw_ostream &O);
void printSLC(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, void printSLC(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O); raw_ostream &O);
void printTFE(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, void printTFE(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O); raw_ostream &O);
void printDMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, void printDMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O); raw_ostream &O);
▲ Show 20 Lines • Show All 176 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
} }
void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) { raw_ostream &O) {
O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
} }
void AMDGPUInstPrinter::printS13ImmDecOperand(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printS13ImmDecOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
// GFX10: Address offset is 12-bit signed byte offset.
if (AMDGPU::isGFX10(STI)) {
O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
} else {
O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm())); O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
} }
}
void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
} }
void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
Show All 37 Lines
} }
void AMDGPUInstPrinter::printOffsetS13(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printOffsetS13(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
uint16_t Imm = MI->getOperand(OpNo).getImm(); uint16_t Imm = MI->getOperand(OpNo).getImm();
if (Imm != 0) { if (Imm != 0) {
O << ((OpNo == 0)? "offset:" : " offset:"); O << ((OpNo == 0)? "offset:" : " offset:");
printS13ImmDecOperand(MI, OpNo, O); printS13ImmDecOperand(MI, OpNo, STI, O);
} }
} }
void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
if (MI->getOperand(OpNo).getImm()) { if (MI->getOperand(OpNo).getImm()) {
O << " offset0:"; O << " offset0:";
Show All 28 Linesvoid AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
printU32ImmOperand(MI, OpNo, STI, O); printU32ImmOperand(MI, OpNo, STI, O);
} }
void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) { const MCSubtargetInfo &STI, raw_ostream &O) {
printNamedBit(MI, OpNo, O, "gds"); printNamedBit(MI, OpNo, O, "gds");
} }
void AMDGPUInstPrinter::printDLC(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
if (AMDGPU::isGFX10(STI))
printNamedBit(MI, OpNo, O, "dlc");
}
void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) { const MCSubtargetInfo &STI, raw_ostream &O) {
printNamedBit(MI, OpNo, O, "glc"); printNamedBit(MI, OpNo, O, "glc");
} }
void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) { const MCSubtargetInfo &STI, raw_ostream &O) {
printNamedBit(MI, OpNo, O, "slc"); printNamedBit(MI, OpNo, O, "slc");
▲ Show 20 Lines • Show All 1,330 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/SIFixupVectorISel.cpp

Show First 20 Lines • Show All 191 Lines • ▼ Show 20 Lines if (VData)
NewGlob->addOperand(MF, *VData); NewGlob->addOperand(MF, *VData);
NewGlob->addOperand(MF, MachineOperand::CreateReg(BaseReg, false)); NewGlob->addOperand(MF, MachineOperand::CreateReg(BaseReg, false));
NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::offset)); NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::offset));
MachineOperand *Glc = TII->getNamedOperand(MI, AMDGPU::OpName::glc); MachineOperand *Glc = TII->getNamedOperand(MI, AMDGPU::OpName::glc);
// Atomics dont have a GLC, so omit the field if not there. // Atomics dont have a GLC, so omit the field if not there.
if (Glc) if (Glc)
NewGlob->addOperand(MF, *Glc); NewGlob->addOperand(MF, *Glc);
MachineOperand *DLC = TII->getNamedOperand(MI, AMDGPU::OpName::dlc);
if (DLC)
NewGlob->addOperand(MF, *DLC);
NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::slc)); NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::slc));
// _D16 have an vdst_in operand, copy it in. // _D16 have an vdst_in operand, copy it in.
MachineOperand *VDstInOp = TII->getNamedOperand(MI, MachineOperand *VDstInOp = TII->getNamedOperand(MI,
AMDGPU::OpName::vdst_in); AMDGPU::OpName::vdst_in);
if (VDstInOp) if (VDstInOp)
NewGlob->addOperand(MF, *VDstInOp); NewGlob->addOperand(MF, *VDstInOp);
NewGlob->copyImplicitOps(MF, MI); NewGlob->copyImplicitOps(MF, MI);
NewGlob->cloneMemRefs(MF, MI); NewGlob->cloneMemRefs(MF, MI);
Show All 23 Lines

llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Linesvoid SIFrameLowering::emitFlatScratchInit(const GCNSubtarget &ST,
unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0);
unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1);
unsigned ScratchWaveOffsetReg = MFI->getScratchWaveOffsetReg(); unsigned ScratchWaveOffsetReg = MFI->getScratchWaveOffsetReg();
// Do a 64-bit pointer add. // Do a 64-bit pointer add.
if (ST.flatScratchIsPointer()) { if (ST.flatScratchIsPointer()) {
if (ST.getGeneration() >= AMDGPUSubtarget::GFX10) {
BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo)
.addReg(FlatScrInitLo)
.addReg(ScratchWaveOffsetReg);
BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), FlatScrInitHi)
.addReg(FlatScrInitHi)
.addImm(0);
BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SETREG_B32)).
addReg(FlatScrInitLo).
addImm(int16_t(AMDGPU::Hwreg::ID_FLAT_SCR_LO |
(31 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_)));
BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SETREG_B32)).
addReg(FlatScrInitHi).
addImm(int16_t(AMDGPU::Hwreg::ID_FLAT_SCR_HI |
(31 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_)));
return;
}
BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), AMDGPU::FLAT_SCR_LO) BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), AMDGPU::FLAT_SCR_LO)
.addReg(FlatScrInitLo) .addReg(FlatScrInitLo)
.addReg(ScratchWaveOffsetReg); .addReg(ScratchWaveOffsetReg);
BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), AMDGPU::FLAT_SCR_HI) BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), AMDGPU::FLAT_SCR_HI)
.addReg(FlatScrInitHi) .addReg(FlatScrInitHi)
.addImm(0); .addImm(0);
return; return;
} }
assert(ST.getGeneration() < AMDGPUSubtarget::GFX10);
// Copy the size in bytes. // Copy the size in bytes.
BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), AMDGPU::FLAT_SCR_LO) BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), AMDGPU::FLAT_SCR_LO)
.addReg(FlatScrInitHi, RegState::Kill); .addReg(FlatScrInitHi, RegState::Kill);
// Add wave offset in bytes to private base offset. // Add wave offset in bytes to private base offset.
// See comment in AMDKernelCodeT.h for enable_sgpr_flat_scratch_init. // See comment in AMDKernelCodeT.h for enable_sgpr_flat_scratch_init.
BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo) BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo)
.addReg(FlatScrInitLo) .addReg(FlatScrInitLo)
▲ Show 20 Lines • Show All 327 Lines • ▼ Show 20 Lines auto MMO = MF.getMachineMemOperand(PtrInfo,
16, 4); 16, 4);
unsigned Offset = Fn.getCallingConv() == CallingConv::AMDGPU_CS ? 16 : 0; unsigned Offset = Fn.getCallingConv() == CallingConv::AMDGPU_CS ? 16 : 0;
const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>(); const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
unsigned EncodedOffset = AMDGPU::getSMRDEncodedOffset(Subtarget, Offset); unsigned EncodedOffset = AMDGPU::getSMRDEncodedOffset(Subtarget, Offset);
BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg) BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)
.addReg(Rsrc01) .addReg(Rsrc01)
.addImm(EncodedOffset) // offset .addImm(EncodedOffset) // offset
.addImm(0) // glc .addImm(0) // glc
.addImm(0) // dlc
.addReg(ScratchRsrcReg, RegState::ImplicitDefine) .addReg(ScratchRsrcReg, RegState::ImplicitDefine)
.addMemOperand(MMO); .addMemOperand(MMO);
return; return;
} }
if (ST.isMesaGfxShader(Fn) if (ST.isMesaGfxShader(Fn)
|| (PreloadedPrivateBufferReg == AMDGPU::NoRegister)) { || (PreloadedPrivateBufferReg == AMDGPU::NoRegister)) {
assert(!ST.isAmdHsaOrMesa(Fn)); assert(!ST.isAmdHsaOrMesa(Fn));
const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32); const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
Show All 24 Lines if (MFI->hasImplicitBufferPtr()) {
MachineMemOperand::MOLoad | MachineMemOperand::MOLoad |
MachineMemOperand::MOInvariant | MachineMemOperand::MOInvariant |
MachineMemOperand::MODereferenceable, MachineMemOperand::MODereferenceable,
8, 4); 8, 4);
BuildMI(MBB, I, DL, LoadDwordX2, Rsrc01) BuildMI(MBB, I, DL, LoadDwordX2, Rsrc01)
.addReg(MFI->getImplicitBufferPtrUserSGPR()) .addReg(MFI->getImplicitBufferPtrUserSGPR())
.addImm(0) // offset .addImm(0) // offset
.addImm(0) // glc .addImm(0) // glc
.addImm(0) // dlc
.addMemOperand(MMO) .addMemOperand(MMO)
.addReg(ScratchRsrcReg, RegState::ImplicitDefine); .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
} }
} else { } else {
unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
BuildMI(MBB, I, DL, SMovB32, Rsrc0) BuildMI(MBB, I, DL, SMovB32, Rsrc0)
▲ Show 20 Lines • Show All 318 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp

Show First 20 Lines • Show All 4,160 Lines • ▼ Show 20 Lines if (VAddr && AMDGPU::getIfAddr64Inst(MI.getOpcode()) != -1) {
.add(*SOffset) .add(*SOffset)
.add(*Offset); .add(*Offset);
// Atomics do not have this operand. // Atomics do not have this operand.
if (const MachineOperand *GLC = if (const MachineOperand *GLC =
getNamedOperand(MI, AMDGPU::OpName::glc)) { getNamedOperand(MI, AMDGPU::OpName::glc)) {
MIB.addImm(GLC->getImm()); MIB.addImm(GLC->getImm());
} }
if (const MachineOperand *DLC =
getNamedOperand(MI, AMDGPU::OpName::dlc)) {
MIB.addImm(DLC->getImm());
}
MIB.addImm(getNamedImmOperand(MI, AMDGPU::OpName::slc)); MIB.addImm(getNamedImmOperand(MI, AMDGPU::OpName::slc));
if (const MachineOperand *TFE = if (const MachineOperand *TFE =
getNamedOperand(MI, AMDGPU::OpName::tfe)) { getNamedOperand(MI, AMDGPU::OpName::tfe)) {
MIB.addImm(TFE->getImm()); MIB.addImm(TFE->getImm());
} }
▲ Show 20 Lines • Show All 1,569 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

Show First 20 Lines • Show All 824 Lines • ▼ Show 20 Lines
def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>; def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>;
def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>; def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>; def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>; def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
def highmod : NamedOperandBit<"High", NamedMatchClass<"High">>; def highmod : NamedOperandBit<"High", NamedMatchClass<"High">>;
def DLC : NamedOperandBit<"DLC", NamedMatchClass<"DLC">>;
def GLC : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>; def GLC : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>;
def SLC : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>; def SLC : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
def TFE : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>; def TFE : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>;
def UNorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>; def UNorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>;
def DA : NamedOperandBit<"DA", NamedMatchClass<"DA">>; def DA : NamedOperandBit<"DA", NamedMatchClass<"DA">>;
def R128A16 : NamedOperandBit<"R128A16", NamedMatchClass<"R128A16">>; def R128A16 : NamedOperandBit<"R128A16", NamedMatchClass<"R128A16">>;
def D16 : NamedOperandBit<"D16", NamedMatchClass<"D16">>; def D16 : NamedOperandBit<"D16", NamedMatchClass<"D16">>;
def LWE : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>; def LWE : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
▲ Show 20 Lines • Show All 1,348 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

Show First 20 Lines • Show All 125 Lines • ▼ Show 20 Lines struct CombineInfo {
unsigned Width0; unsigned Width0;
unsigned Width1; unsigned Width1;
unsigned BaseOff; unsigned BaseOff;
InstClassEnum InstClass; InstClassEnum InstClass;
bool GLC0; bool GLC0;
bool GLC1; bool GLC1;
bool SLC0; bool SLC0;
bool SLC1; bool SLC1;
bool DLC0;
bool DLC1;
bool UseST64; bool UseST64;
SmallVector<MachineInstr *, 8> InstsToMove; SmallVector<MachineInstr *, 8> InstsToMove;
}; };
struct BaseRegisters { struct BaseRegisters {
unsigned LoReg = 0; unsigned LoReg = 0;
unsigned HiReg = 0; unsigned HiReg = 0;
▲ Show 20 Lines • Show All 176 Lines • ▼ Show 20 Linesbool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI) {
unsigned EltOffset1 = CI.Offset1 / CI.EltSize; unsigned EltOffset1 = CI.Offset1 / CI.EltSize;
CI.UseST64 = false; CI.UseST64 = false;
CI.BaseOff = 0; CI.BaseOff = 0;
// Handle SMEM and VMEM instructions. // Handle SMEM and VMEM instructions.
if ((CI.InstClass != DS_READ) && (CI.InstClass != DS_WRITE)) { if ((CI.InstClass != DS_READ) && (CI.InstClass != DS_WRITE)) {
return (EltOffset0 + CI.Width0 == EltOffset1 || return (EltOffset0 + CI.Width0 == EltOffset1 ||
EltOffset1 + CI.Width1 == EltOffset0) && EltOffset1 + CI.Width1 == EltOffset0) &&
CI.GLC0 == CI.GLC1 && CI.GLC0 == CI.GLC1 && CI.DLC0 == CI.DLC1 &&
(CI.InstClass == S_BUFFER_LOAD_IMM || CI.SLC0 == CI.SLC1); (CI.InstClass == S_BUFFER_LOAD_IMM || CI.SLC0 == CI.SLC1);
} }
// If the offset in elements doesn't fit in 8-bits, we might be able to use // If the offset in elements doesn't fit in 8-bits, we might be able to use
// the stride 64 versions. // the stride 64 versions.
if ((EltOffset0 % 64 == 0) && (EltOffset1 % 64) == 0 && if ((EltOffset0 % 64 == 0) && (EltOffset1 % 64) == 0 &&
isUInt<8>(EltOffset0 / 64) && isUInt<8>(EltOffset1 / 64)) { isUInt<8>(EltOffset0 / 64) && isUInt<8>(EltOffset1 / 64)) {
CI.Offset0 = EltOffset0 / 64; CI.Offset0 = EltOffset0 / 64;
▲ Show 20 Lines • Show All 297 Lines • ▼ Show 20 Lines if (Match) {
CI.Offset1 &= 0xffff; CI.Offset1 &= 0xffff;
} else { } else {
CI.GLC0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::glc)->getImm(); CI.GLC0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::glc)->getImm();
CI.GLC1 = TII->getNamedOperand(*MBBI, AMDGPU::OpName::glc)->getImm(); CI.GLC1 = TII->getNamedOperand(*MBBI, AMDGPU::OpName::glc)->getImm();
if (CI.InstClass != S_BUFFER_LOAD_IMM) { if (CI.InstClass != S_BUFFER_LOAD_IMM) {
CI.SLC0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::slc)->getImm(); CI.SLC0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::slc)->getImm();
CI.SLC1 = TII->getNamedOperand(*MBBI, AMDGPU::OpName::slc)->getImm(); CI.SLC1 = TII->getNamedOperand(*MBBI, AMDGPU::OpName::slc)->getImm();
} }
CI.DLC0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::dlc)->getImm();
CI.DLC1 = TII->getNamedOperand(*MBBI, AMDGPU::OpName::dlc)->getImm();
} }
// Check both offsets fit in the reduced range. // Check both offsets fit in the reduced range.
// We also need to go through the list of instructions that we plan to // We also need to go through the list of instructions that we plan to
// move and make sure they are all safe to move down past the merged // move and make sure they are all safe to move down past the merged
// instruction. // instruction.
if (widthsFit(*STM, CI) && offsetsCanBeCombined(CI)) if (widthsFit(*STM, CI) && offsetsCanBeCombined(CI))
if (canMoveInstsAcrossMemOp(*MBBI, CI.InstsToMove, AA)) if (canMoveInstsAcrossMemOp(*MBBI, CI.InstsToMove, AA))
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 LinesSILoadStoreOptimizer::mergeSBufferLoadImmPair(CombineInfo &CI) {
unsigned DestReg = MRI->createVirtualRegister(SuperRC); unsigned DestReg = MRI->createVirtualRegister(SuperRC);
unsigned MergedOffset = std::min(CI.Offset0, CI.Offset1); unsigned MergedOffset = std::min(CI.Offset0, CI.Offset1);
BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg) BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg)
.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase)) .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase))
.addImm(MergedOffset) // offset .addImm(MergedOffset) // offset
.addImm(CI.GLC0) // glc .addImm(CI.GLC0) // glc
.addImm(CI.DLC0) // dlc
.cloneMergedMemRefs({&*CI.I, &*CI.Paired}); .cloneMergedMemRefs({&*CI.I, &*CI.Paired});
std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI); std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI);
const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); const unsigned SubRegIdx0 = std::get<0>(SubRegIdx);
const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); const unsigned SubRegIdx1 = std::get<1>(SubRegIdx);
// Copy to the old destination registers. // Copy to the old destination registers.
const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
Show All 36 Lines if (Regs & VADDR)
MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr));
MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc))
.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))
.addImm(MergedOffset) // offset .addImm(MergedOffset) // offset
.addImm(CI.GLC0) // glc .addImm(CI.GLC0) // glc
.addImm(CI.SLC0) // slc .addImm(CI.SLC0) // slc
.addImm(0) // tfe .addImm(0) // tfe
.addImm(CI.DLC0) // dlc
.cloneMergedMemRefs({&*CI.I, &*CI.Paired}); .cloneMergedMemRefs({&*CI.I, &*CI.Paired});
std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI); std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI);
const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); const unsigned SubRegIdx0 = std::get<0>(SubRegIdx);
const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); const unsigned SubRegIdx1 = std::get<1>(SubRegIdx);
// Copy to the old destination registers. // Copy to the old destination registers.
const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
▲ Show 20 Lines • Show All 163 Lines • ▼ Show 20 LinesSILoadStoreOptimizer::mergeBufferStorePair(CombineInfo &CI) {
const unsigned Regs = getRegs(Opcode); const unsigned Regs = getRegs(Opcode);
if (Regs & VADDR) if (Regs & VADDR)
MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr));
MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc))
.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))
.addImm(std::min(CI.Offset0, CI.Offset1)) // offset .addImm(std::min(CI.Offset0, CI.Offset1)) // offset
.addImm(CI.GLC0) // glc .addImm(CI.GLC0) // glc
.addImm(CI.SLC0) // slc .addImm(CI.SLC0) // slc
.addImm(0) // tfe .addImm(0) // tfe
.addImm(CI.DLC0) // dlc
.cloneMergedMemRefs({&*CI.I, &*CI.Paired}); .cloneMergedMemRefs({&*CI.I, &*CI.Paired});
moveInstsAfter(MIB, CI.InstsToMove); moveInstsAfter(MIB, CI.InstsToMove);
MachineBasicBlock::iterator Next = std::next(CI.I); MachineBasicBlock::iterator Next = std::next(CI.I);
CI.I->eraseFromParent(); CI.I->eraseFromParent();
CI.Paired->eraseFromParent(); CI.Paired->eraseFromParent();
return Next; return Next;
▲ Show 20 Lines • Show All 438 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp

Show First 20 Lines • Show All 530 Lines • ▼ Show 20 Lines MachineInstrBuilder NewMI =
BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp)) BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
.add(*Reg) .add(*Reg)
.add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)) .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc))
.add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)) .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset))
.addImm(Offset) .addImm(Offset)
.addImm(0) // glc .addImm(0) // glc
.addImm(0) // slc .addImm(0) // slc
.addImm(0) // tfe .addImm(0) // tfe
.addImm(0) // dlc
.cloneMemRefs(*MI); .cloneMemRefs(*MI);
const MachineOperand *VDataIn = TII->getNamedOperand(*MI, const MachineOperand *VDataIn = TII->getNamedOperand(*MI,
AMDGPU::OpName::vdata_in); AMDGPU::OpName::vdata_in);
if (VDataIn) if (VDataIn)
NewMI.add(*VDataIn); NewMI.add(*VDataIn);
return true; return true;
} }
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += EltSize) {
auto MIB = BuildMI(*MBB, MI, DL, Desc) auto MIB = BuildMI(*MBB, MI, DL, Desc)
.addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)) .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill))
.addReg(ScratchRsrcReg) .addReg(ScratchRsrcReg)
.addReg(SOffset, SOffsetRegState) .addReg(SOffset, SOffsetRegState)
.addImm(Offset) .addImm(Offset)
.addImm(0) // glc .addImm(0) // glc
.addImm(0) // slc .addImm(0) // slc
.addImm(0) // tfe .addImm(0) // tfe
.addImm(0) // dlc
.addMemOperand(NewMMO); .addMemOperand(NewMMO);
if (NumSubRegs > 1) if (NumSubRegs > 1)
MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState); MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState);
} }
if (ScratchOffsetRegDelta != 0) { if (ScratchOffsetRegDelta != 0) {
// Subtract the offset we added to the ScratchOffset register. // Subtract the offset we added to the ScratchOffset register.
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines if (SpillToSMEM) {
.addReg(MFI->getFrameOffsetReg()); .addReg(MFI->getFrameOffsetReg());
} }
BuildMI(*MBB, MI, DL, TII->get(ScalarStoreOp)) BuildMI(*MBB, MI, DL, TII->get(ScalarStoreOp))
.addReg(SubReg, getKillRegState(IsKill)) // sdata .addReg(SubReg, getKillRegState(IsKill)) // sdata
.addReg(MFI->getScratchRSrcReg()) // sbase .addReg(MFI->getScratchRSrcReg()) // sbase
.addReg(OffsetReg, RegState::Kill) // soff .addReg(OffsetReg, RegState::Kill) // soff
.addImm(0) // glc .addImm(0) // glc
.addImm(0) // dlc
.addMemOperand(MMO); .addMemOperand(MMO);
continue; continue;
} }
if (SpillToVGPR) { if (SpillToVGPR) {
SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i];
▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines if (SpillToSMEM) {
.addImm(Offset); .addImm(Offset);
} else { } else {
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
.addReg(MFI->getFrameOffsetReg()); .addReg(MFI->getFrameOffsetReg());
} }
auto MIB = auto MIB =
BuildMI(*MBB, MI, DL, TII->get(ScalarLoadOp), SubReg) BuildMI(*MBB, MI, DL, TII->get(ScalarLoadOp), SubReg)
.addReg(MFI->getScratchRSrcReg()) // sbase .addReg(MFI->getScratchRSrcReg()) // sbase
.addReg(OffsetReg, RegState::Kill) // soff .addReg(OffsetReg, RegState::Kill) // soff
.addImm(0) // glc .addImm(0) // glc
.addImm(0) // dlc
.addMemOperand(MMO); .addMemOperand(MMO);
if (NumSubRegs > 1 && i == 0) if (NumSubRegs > 1 && i == 0)
MIB.addReg(SuperReg, RegState::ImplicitDefine); MIB.addReg(SuperReg, RegState::ImplicitDefine);
continue; continue;
} }
▲ Show 20 Lines • Show All 791 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/SMInstructions.td

Show All 34 Linesclass SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
let SchedRW = [WriteSMEM]; let SchedRW = [WriteSMEM];
string Mnemonic = opName; string Mnemonic = opName;
string AsmOperands = asmOps; string AsmOperands = asmOps;
bits<1> has_sbase = 1; bits<1> has_sbase = 1;
bits<1> has_sdst = 1; bits<1> has_sdst = 1;
bit has_glc = 0; bit has_glc = 0;
bit has_dlc = 0;
bits<1> has_offset = 1; bits<1> has_offset = 1;
bits<1> offset_is_imm = 0; bits<1> offset_is_imm = 0;
} }
class SM_Real <SM_Pseudo ps> class SM_Real <SM_Pseudo ps>
: InstSI<ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> { : InstSI<ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> {
let isPseudo = 0; let isPseudo = 0;
Show All 23 Lines
} }
class SM_Load_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> class SM_Load_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]>
: SM_Pseudo<opName, outs, ins, asmOps, pattern> { : SM_Pseudo<opName, outs, ins, asmOps, pattern> {
RegisterClass BaseClass; RegisterClass BaseClass;
let mayLoad = 1; let mayLoad = 1;
let mayStore = 0; let mayStore = 0;
let has_glc = 1; let has_glc = 1;
let has_dlc = 1;
} }
class SM_Store_Pseudo <string opName, dag ins, string asmOps, list<dag> pattern = []> class SM_Store_Pseudo <string opName, dag ins, string asmOps, list<dag> pattern = []>
: SM_Pseudo<opName, (outs), ins, asmOps, pattern> { : SM_Pseudo<opName, (outs), ins, asmOps, pattern> {
RegisterClass BaseClass; RegisterClass BaseClass;
RegisterClass SrcClass; RegisterClass SrcClass;
let mayLoad = 0; let mayLoad = 0;
let mayStore = 1; let mayStore = 1;
let has_glc = 1; let has_glc = 1;
let has_dlc = 1;
let ScalarStore = 1; let ScalarStore = 1;
} }
class SM_Discard_Pseudo <string opName, dag ins, bit isImm> class SM_Discard_Pseudo <string opName, dag ins, bit isImm>
: SM_Pseudo<opName, (outs), ins, " $sbase, $offset"> { : SM_Pseudo<opName, (outs), ins, " $sbase, $offset"> {
let mayLoad = 0; let mayLoad = 0;
let mayStore = 0; let mayStore = 0;
let has_glc = 0; let has_glc = 0;
let has_sdst = 0; let has_sdst = 0;
let ScalarStore = 0; let ScalarStore = 0;
let hasSideEffects = 1; let hasSideEffects = 1;
let offset_is_imm = isImm; let offset_is_imm = isImm;
let PseudoInstr = opName # !if(isImm, "_IMM", "_SGPR"); let PseudoInstr = opName # !if(isImm, "_IMM", "_SGPR");
} }
multiclass SM_Pseudo_Loads<string opName, multiclass SM_Pseudo_Loads<string opName,
RegisterClass baseClass, RegisterClass baseClass,
RegisterClass dstClass> { RegisterClass dstClass> {
def _IMM : SM_Load_Pseudo <opName, def _IMM : SM_Load_Pseudo <opName,
(outs dstClass:$sdst), (outs dstClass:$sdst),
(ins baseClass:$sbase, i32imm:$offset, i1imm:$glc), (ins baseClass:$sbase, i32imm:$offset, i1imm:$glc, i1imm:$dlc),
" $sdst, $sbase, $offset$glc", []> { " $sdst, $sbase, $offset$glc$dlc", []> {
let offset_is_imm = 1; let offset_is_imm = 1;
let BaseClass = baseClass; let BaseClass = baseClass;
let PseudoInstr = opName # "_IMM"; let PseudoInstr = opName # "_IMM";
let has_glc = 1; let has_glc = 1;
let has_dlc = 1;
} }
def _SGPR : SM_Load_Pseudo <opName, def _SGPR : SM_Load_Pseudo <opName,
(outs dstClass:$sdst), (outs dstClass:$sdst),
(ins baseClass:$sbase, SReg_32:$soff, i1imm:$glc), (ins baseClass:$sbase, SReg_32:$soff, i1imm:$glc, i1imm:$dlc),
" $sdst, $sbase, $offset$glc", []> { " $sdst, $sbase, $offset$glc$dlc", []> {
let BaseClass = baseClass; let BaseClass = baseClass;
let PseudoInstr = opName # "_SGPR"; let PseudoInstr = opName # "_SGPR";
let has_glc = 1; let has_glc = 1;
let has_dlc = 1;
} }
} }
multiclass SM_Pseudo_Stores<string opName, multiclass SM_Pseudo_Stores<string opName,
RegisterClass baseClass, RegisterClass baseClass,
RegisterClass srcClass> { RegisterClass srcClass> {
def _IMM : SM_Store_Pseudo <opName, def _IMM : SM_Store_Pseudo <opName,
(ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, i1imm:$glc), (ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, i1imm:$glc, i1imm:$dlc),
" $sdata, $sbase, $offset$glc", []> { " $sdata, $sbase, $offset$glc$dlc", []> {
let offset_is_imm = 1; let offset_is_imm = 1;
let BaseClass = baseClass; let BaseClass = baseClass;
let SrcClass = srcClass; let SrcClass = srcClass;
let PseudoInstr = opName # "_IMM"; let PseudoInstr = opName # "_IMM";
} }
def _SGPR : SM_Store_Pseudo <opName, def _SGPR : SM_Store_Pseudo <opName,
(ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soff, i1imm:$glc), (ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soff, i1imm:$glc, i1imm:$dlc),
" $sdata, $sbase, $offset$glc", []> { " $sdata, $sbase, $offset$glc$dlc", []> {
let BaseClass = baseClass; let BaseClass = baseClass;
let SrcClass = srcClass; let SrcClass = srcClass;
let PseudoInstr = opName # "_SGPR"; let PseudoInstr = opName # "_SGPR";
} }
} }
multiclass SM_Pseudo_Discards<string opName> { multiclass SM_Pseudo_Discards<string opName> {
def _IMM : SM_Discard_Pseudo <opName, (ins SReg_64:$sbase, smrd_offset_20:$offset), 1>; def _IMM : SM_Discard_Pseudo <opName, (ins SReg_64:$sbase, smrd_offset_20:$offset), 1>;
Show All 27 Linesclass SM_Inval_Pseudo <string opName, SDPatternOperator node = null_frag> : SM_Pseudo<
let has_offset = 0; let has_offset = 0;
} }
multiclass SM_Pseudo_Probe<string opName, RegisterClass baseClass> { multiclass SM_Pseudo_Probe<string opName, RegisterClass baseClass> {
def _IMM : SM_Probe_Pseudo <opName, (ins i8imm:$sdata, baseClass:$sbase, smrd_offset_20:$offset), 1>; def _IMM : SM_Probe_Pseudo <opName, (ins i8imm:$sdata, baseClass:$sbase, smrd_offset_20:$offset), 1>;
def _SGPR : SM_Probe_Pseudo <opName, (ins i8imm:$sdata, baseClass:$sbase, SReg_32:$offset), 0>; def _SGPR : SM_Probe_Pseudo <opName, (ins i8imm:$sdata, baseClass:$sbase, SReg_32:$offset), 0>;
} }
class SM_WaveId_Pseudo<string opName, SDPatternOperator node> : SM_Pseudo<
opName, (outs SReg_32_XM0_XEXEC:$sdst), (ins),
" $sdst", [(set i32:$sdst, (node))]> {
let hasSideEffects = 1;
let mayStore = 0;
let mayLoad = 1;
let has_sbase = 0;
let has_offset = 0;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Scalar Atomic Memory Classes // Scalar Atomic Memory Classes
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class SM_Atomic_Pseudo <string opName, class SM_Atomic_Pseudo <string opName,
dag outs, dag ins, string asmOps, bit isRet> dag outs, dag ins, string asmOps, bit isRet>
: SM_Pseudo<opName, outs, ins, asmOps, []> { : SM_Pseudo<opName, outs, ins, asmOps, []> {
bit glc = isRet; bit glc = isRet;
let mayLoad = 1; let mayLoad = 1;
let mayStore = 1; let mayStore = 1;
let has_glc = 1; let has_glc = 1;
let has_dlc = 1;
// Should these be set? // Should these be set?
let ScalarStore = 1; let ScalarStore = 1;
let hasSideEffects = 1; let hasSideEffects = 1;
let maybeAtomic = 1; let maybeAtomic = 1;
} }
class SM_Pseudo_Atomic<string opName, class SM_Pseudo_Atomic<string opName,
RegisterClass baseClass, RegisterClass baseClass,
RegisterClass dataClass, RegisterClass dataClass,
bit isImm, bit isImm,
bit isRet> : bit isRet> :
SM_Atomic_Pseudo<opName, SM_Atomic_Pseudo<opName,
!if(isRet, (outs dataClass:$sdst), (outs)), !if(isRet, (outs dataClass:$sdst), (outs)),
!if(isImm, !if(isImm,
(ins dataClass:$sdata, baseClass:$sbase, smrd_offset_20:$offset), (ins dataClass:$sdata, baseClass:$sbase, smrd_offset_20:$offset, DLC:$dlc),
(ins dataClass:$sdata, baseClass:$sbase, SReg_32:$offset)), (ins dataClass:$sdata, baseClass:$sbase, SReg_32:$offset, DLC:$dlc)),
!if(isRet, " $sdst", " $sdata") # ", $sbase, $offset" # !if(isRet, " glc", ""), !if(isRet, " $sdst", " $sdata") # ", $sbase, $offset" # !if(isRet, " glc", "") # "$dlc",
isRet> { isRet> {
let offset_is_imm = isImm; let offset_is_imm = isImm;
let PseudoInstr = opName # !if(isImm, let PseudoInstr = opName # !if(isImm,
!if(isRet, "_IMM_RTN", "_IMM"), !if(isRet, "_IMM_RTN", "_IMM"),
!if(isRet, "_SGPR_RTN", "_SGPR")); !if(isRet, "_SGPR_RTN", "_SGPR"));
let Constraints = !if(isRet, "$sdst = $sdata", ""); let Constraints = !if(isRet, "$sdst = $sdata", "");
let DisableEncoding = !if(isRet, "$sdata", ""); let DisableEncoding = !if(isRet, "$sdata", "");
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
defm S_BUFFER_LOAD_DWORDX8 : SM_Pseudo_Loads < defm S_BUFFER_LOAD_DWORDX8 : SM_Pseudo_Loads <
"s_buffer_load_dwordx8", SReg_128, SReg_256 "s_buffer_load_dwordx8", SReg_128, SReg_256
>; >;
defm S_BUFFER_LOAD_DWORDX16 : SM_Pseudo_Loads < defm S_BUFFER_LOAD_DWORDX16 : SM_Pseudo_Loads <
"s_buffer_load_dwordx16", SReg_128, SReg_512 "s_buffer_load_dwordx16", SReg_128, SReg_512
>; >;
let SubtargetPredicate = HasScalarStores in {
defm S_STORE_DWORD : SM_Pseudo_Stores <"s_store_dword", SReg_64, SReg_32_XM0_XEXEC>; defm S_STORE_DWORD : SM_Pseudo_Stores <"s_store_dword", SReg_64, SReg_32_XM0_XEXEC>;
defm S_STORE_DWORDX2 : SM_Pseudo_Stores <"s_store_dwordx2", SReg_64, SReg_64_XEXEC>; defm S_STORE_DWORDX2 : SM_Pseudo_Stores <"s_store_dwordx2", SReg_64, SReg_64_XEXEC>;
defm S_STORE_DWORDX4 : SM_Pseudo_Stores <"s_store_dwordx4", SReg_64, SReg_128>; defm S_STORE_DWORDX4 : SM_Pseudo_Stores <"s_store_dwordx4", SReg_64, SReg_128>;
defm S_BUFFER_STORE_DWORD : SM_Pseudo_Stores < defm S_BUFFER_STORE_DWORD : SM_Pseudo_Stores <
"s_buffer_store_dword", SReg_128, SReg_32_XM0_XEXEC "s_buffer_store_dword", SReg_128, SReg_32_XM0_XEXEC
>; >;
defm S_BUFFER_STORE_DWORDX2 : SM_Pseudo_Stores < defm S_BUFFER_STORE_DWORDX2 : SM_Pseudo_Stores <
"s_buffer_store_dwordx2", SReg_128, SReg_64_XEXEC "s_buffer_store_dwordx2", SReg_128, SReg_64_XEXEC
>; >;
defm S_BUFFER_STORE_DWORDX4 : SM_Pseudo_Stores < defm S_BUFFER_STORE_DWORDX4 : SM_Pseudo_Stores <
"s_buffer_store_dwordx4", SReg_128, SReg_128 "s_buffer_store_dwordx4", SReg_128, SReg_128
>; >;
} // End SubtargetPredicate = HasScalarStores
def S_MEMTIME : SM_Time_Pseudo <"s_memtime", int_amdgcn_s_memtime>; def S_MEMTIME : SM_Time_Pseudo <"s_memtime", int_amdgcn_s_memtime>;
def S_DCACHE_INV : SM_Inval_Pseudo <"s_dcache_inv", int_amdgcn_s_dcache_inv>; def S_DCACHE_INV : SM_Inval_Pseudo <"s_dcache_inv", int_amdgcn_s_dcache_inv>;
let SubtargetPredicate = isGFX7GFX8GFX9 in { let SubtargetPredicate = isGFX7GFX8GFX9 in {
def S_DCACHE_INV_VOL : SM_Inval_Pseudo <"s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>; def S_DCACHE_INV_VOL : SM_Inval_Pseudo <"s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>;
} // let SubtargetPredicate = isGFX7GFX8GFX9 } // let SubtargetPredicate = isGFX7GFX8GFX9
let SubtargetPredicate = isGFX8Plus in { let SubtargetPredicate = isGFX8Plus in {
let OtherPredicates = [HasScalarStores] in {
def S_DCACHE_WB : SM_Inval_Pseudo <"s_dcache_wb", int_amdgcn_s_dcache_wb>; def S_DCACHE_WB : SM_Inval_Pseudo <"s_dcache_wb", int_amdgcn_s_dcache_wb>;
def S_DCACHE_WB_VOL : SM_Inval_Pseudo <"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>; def S_DCACHE_WB_VOL : SM_Inval_Pseudo <"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>;
} // End OtherPredicates = [HasScalarStores]
def S_MEMREALTIME : SM_Time_Pseudo <"s_memrealtime", int_amdgcn_s_memrealtime>; def S_MEMREALTIME : SM_Time_Pseudo <"s_memrealtime", int_amdgcn_s_memrealtime>;
defm S_ATC_PROBE : SM_Pseudo_Probe <"s_atc_probe", SReg_64>; defm S_ATC_PROBE : SM_Pseudo_Probe <"s_atc_probe", SReg_64>;
defm S_ATC_PROBE_BUFFER : SM_Pseudo_Probe <"s_atc_probe_buffer", SReg_128>; defm S_ATC_PROBE_BUFFER : SM_Pseudo_Probe <"s_atc_probe_buffer", SReg_128>;
} // SubtargetPredicate = isGFX8Plus } // SubtargetPredicate = isGFX8Plus
let SubtargetPredicate = HasFlatScratchInsts, Uses = [FLAT_SCR] in { let SubtargetPredicate = isGFX10Plus in {
def S_GL1_INV : SM_Inval_Pseudo<"s_gl1_inv">;
def S_GET_WAVEID_IN_WORKGROUP : SM_WaveId_Pseudo <"s_get_waveid_in_workgroup", int_amdgcn_s_get_waveid_in_workgroup>;
} // End SubtargetPredicate = isGFX10Plus
let SubtargetPredicate = HasScalarFlatScratchInsts, Uses = [FLAT_SCR] in {
defm S_SCRATCH_LOAD_DWORD : SM_Pseudo_Loads <"s_scratch_load_dword", SReg_64, SReg_32_XM0_XEXEC>; defm S_SCRATCH_LOAD_DWORD : SM_Pseudo_Loads <"s_scratch_load_dword", SReg_64, SReg_32_XM0_XEXEC>;
defm S_SCRATCH_LOAD_DWORDX2 : SM_Pseudo_Loads <"s_scratch_load_dwordx2", SReg_64, SReg_64_XEXEC>; defm S_SCRATCH_LOAD_DWORDX2 : SM_Pseudo_Loads <"s_scratch_load_dwordx2", SReg_64, SReg_64_XEXEC>;
defm S_SCRATCH_LOAD_DWORDX4 : SM_Pseudo_Loads <"s_scratch_load_dwordx4", SReg_64, SReg_128>; defm S_SCRATCH_LOAD_DWORDX4 : SM_Pseudo_Loads <"s_scratch_load_dwordx4", SReg_64, SReg_128>;
defm S_SCRATCH_STORE_DWORD : SM_Pseudo_Stores <"s_scratch_store_dword", SReg_64, SReg_32_XM0_XEXEC>; defm S_SCRATCH_STORE_DWORD : SM_Pseudo_Stores <"s_scratch_store_dword", SReg_64, SReg_32_XM0_XEXEC>;
defm S_SCRATCH_STORE_DWORDX2 : SM_Pseudo_Stores <"s_scratch_store_dwordx2", SReg_64, SReg_64_XEXEC>; defm S_SCRATCH_STORE_DWORDX2 : SM_Pseudo_Stores <"s_scratch_store_dwordx2", SReg_64, SReg_64_XEXEC>;
defm S_SCRATCH_STORE_DWORDX4 : SM_Pseudo_Stores <"s_scratch_store_dwordx4", SReg_64, SReg_128>; defm S_SCRATCH_STORE_DWORDX4 : SM_Pseudo_Stores <"s_scratch_store_dwordx4", SReg_64, SReg_128>;
} // SubtargetPredicate = HasFlatScratchInsts } // SubtargetPredicate = HasScalarFlatScratchInsts
let SubtargetPredicate = HasScalarAtomics in { let SubtargetPredicate = HasScalarAtomics in {
defm S_BUFFER_ATOMIC_SWAP : SM_Pseudo_Atomics <"s_buffer_atomic_swap", SReg_128, SReg_32_XM0_XEXEC>; defm S_BUFFER_ATOMIC_SWAP : SM_Pseudo_Atomics <"s_buffer_atomic_swap", SReg_128, SReg_32_XM0_XEXEC>;
defm S_BUFFER_ATOMIC_CMPSWAP : SM_Pseudo_Atomics <"s_buffer_atomic_cmpswap", SReg_128, SReg_64_XEXEC>; defm S_BUFFER_ATOMIC_CMPSWAP : SM_Pseudo_Atomics <"s_buffer_atomic_cmpswap", SReg_128, SReg_64_XEXEC>;
defm S_BUFFER_ATOMIC_ADD : SM_Pseudo_Atomics <"s_buffer_atomic_add", SReg_128, SReg_32_XM0_XEXEC>; defm S_BUFFER_ATOMIC_ADD : SM_Pseudo_Atomics <"s_buffer_atomic_add", SReg_128, SReg_32_XM0_XEXEC>;
defm S_BUFFER_ATOMIC_SUB : SM_Pseudo_Atomics <"s_buffer_atomic_sub", SReg_128, SReg_32_XM0_XEXEC>; defm S_BUFFER_ATOMIC_SUB : SM_Pseudo_Atomics <"s_buffer_atomic_sub", SReg_128, SReg_32_XM0_XEXEC>;
defm S_BUFFER_ATOMIC_SMIN : SM_Pseudo_Atomics <"s_buffer_atomic_smin", SReg_128, SReg_32_XM0_XEXEC>; defm S_BUFFER_ATOMIC_SMIN : SM_Pseudo_Atomics <"s_buffer_atomic_smin", SReg_128, SReg_32_XM0_XEXEC>;
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defm S_ATOMIC_AND_X2 : SM_Pseudo_Atomics <"s_atomic_and_x2", SReg_64, SReg_64_XEXEC>; defm S_ATOMIC_AND_X2 : SM_Pseudo_Atomics <"s_atomic_and_x2", SReg_64, SReg_64_XEXEC>;
defm S_ATOMIC_OR_X2 : SM_Pseudo_Atomics <"s_atomic_or_x2", SReg_64, SReg_64_XEXEC>; defm S_ATOMIC_OR_X2 : SM_Pseudo_Atomics <"s_atomic_or_x2", SReg_64, SReg_64_XEXEC>;
defm S_ATOMIC_XOR_X2 : SM_Pseudo_Atomics <"s_atomic_xor_x2", SReg_64, SReg_64_XEXEC>; defm S_ATOMIC_XOR_X2 : SM_Pseudo_Atomics <"s_atomic_xor_x2", SReg_64, SReg_64_XEXEC>;
defm S_ATOMIC_INC_X2 : SM_Pseudo_Atomics <"s_atomic_inc_x2", SReg_64, SReg_64_XEXEC>; defm S_ATOMIC_INC_X2 : SM_Pseudo_Atomics <"s_atomic_inc_x2", SReg_64, SReg_64_XEXEC>;
defm S_ATOMIC_DEC_X2 : SM_Pseudo_Atomics <"s_atomic_dec_x2", SReg_64, SReg_64_XEXEC>; defm S_ATOMIC_DEC_X2 : SM_Pseudo_Atomics <"s_atomic_dec_x2", SReg_64, SReg_64_XEXEC>;
} // let SubtargetPredicate = HasScalarAtomics } // let SubtargetPredicate = HasScalarAtomics
let SubtargetPredicate = isGFX9Only in { let SubtargetPredicate = HasScalarAtomics in {
defm S_DCACHE_DISCARD : SM_Pseudo_Discards <"s_dcache_discard">; defm S_DCACHE_DISCARD : SM_Pseudo_Discards <"s_dcache_discard">;
defm S_DCACHE_DISCARD_X2 : SM_Pseudo_Discards <"s_dcache_discard_x2">; defm S_DCACHE_DISCARD_X2 : SM_Pseudo_Discards <"s_dcache_discard_x2">;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Targets // Targets
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Show All 19 Lines
// FIXME: Assembler should reject trying to use glc on SMRD // FIXME: Assembler should reject trying to use glc on SMRD
// instructions on SI. // instructions on SI.
multiclass SM_Real_Loads_si<bits<5> op, string ps, multiclass SM_Real_Loads_si<bits<5> op, string ps,
SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM), SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> { SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
def _IMM_si : SMRD_Real_si <op, immPs> { def _IMM_si : SMRD_Real_si <op, immPs> {
let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_8:$offset, GLC:$glc); let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_8:$offset, GLC:$glc, DLC:$dlc);
} }
// FIXME: The operand name $offset is inconsistent with $soff used // FIXME: The operand name $offset is inconsistent with $soff used
// in the pseudo // in the pseudo
def _SGPR_si : SMRD_Real_si <op, sgprPs> { def _SGPR_si : SMRD_Real_si <op, sgprPs> {
let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc); let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc, DLC:$dlc);
} }
} }
defm S_LOAD_DWORD : SM_Real_Loads_si <0x00, "S_LOAD_DWORD">; defm S_LOAD_DWORD : SM_Real_Loads_si <0x00, "S_LOAD_DWORD">;
defm S_LOAD_DWORDX2 : SM_Real_Loads_si <0x01, "S_LOAD_DWORDX2">; defm S_LOAD_DWORDX2 : SM_Real_Loads_si <0x01, "S_LOAD_DWORDX2">;
defm S_LOAD_DWORDX4 : SM_Real_Loads_si <0x02, "S_LOAD_DWORDX4">; defm S_LOAD_DWORDX4 : SM_Real_Loads_si <0x02, "S_LOAD_DWORDX4">;
defm S_LOAD_DWORDX8 : SM_Real_Loads_si <0x03, "S_LOAD_DWORDX8">; defm S_LOAD_DWORDX8 : SM_Real_Loads_si <0x03, "S_LOAD_DWORDX8">;
Show All 30 Linesclass SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
let Inst{31-26} = 0x30; //encoding let Inst{31-26} = 0x30; //encoding
let Inst{51-32} = !if(ps.has_offset, offset{19-0}, ?); let Inst{51-32} = !if(ps.has_offset, offset{19-0}, ?);
} }
multiclass SM_Real_Loads_vi<bits<8> op, string ps, multiclass SM_Real_Loads_vi<bits<8> op, string ps,
SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM), SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> { SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
def _IMM_vi : SMEM_Real_vi <op, immPs> { def _IMM_vi : SMEM_Real_vi <op, immPs> {
let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc); let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc, DLC:$dlc);
} }
def _SGPR_vi : SMEM_Real_vi <op, sgprPs> { def _SGPR_vi : SMEM_Real_vi <op, sgprPs> {
let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc); let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc, DLC:$dlc);
} }
} }
class SMEM_Real_Store_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> { class SMEM_Real_Store_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> {
// encoding // encoding
bits<7> sdata; bits<7> sdata;
let sdst = ?; let sdst = ?;
let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?); let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
} }
multiclass SM_Real_Stores_vi<bits<8> op, string ps, multiclass SM_Real_Stores_vi<bits<8> op, string ps,
SM_Store_Pseudo immPs = !cast<SM_Store_Pseudo>(ps#_IMM), SM_Store_Pseudo immPs = !cast<SM_Store_Pseudo>(ps#_IMM),
SM_Store_Pseudo sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR)> { SM_Store_Pseudo sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR)> {
// FIXME: The operand name $offset is inconsistent with $soff used // FIXME: The operand name $offset is inconsistent with $soff used
// in the pseudo // in the pseudo
def _IMM_vi : SMEM_Real_Store_vi <op, immPs> { def _IMM_vi : SMEM_Real_Store_vi <op, immPs> {
let InOperandList = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc); let InOperandList = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc, DLC:$dlc);
} }
def _SGPR_vi : SMEM_Real_Store_vi <op, sgprPs> { def _SGPR_vi : SMEM_Real_Store_vi <op, sgprPs> {
let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc); let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc, DLC:$dlc);
} }
} }
multiclass SM_Real_Probe_vi<bits<8> op, string ps> { multiclass SM_Real_Probe_vi<bits<8> op, string ps> {
def _IMM_vi : SMEM_Real_Store_vi <op, !cast<SM_Probe_Pseudo>(ps#_IMM)>; def _IMM_vi : SMEM_Real_Store_vi <op, !cast<SM_Probe_Pseudo>(ps#_IMM)>;
def _SGPR_vi : SMEM_Real_Store_vi <op, !cast<SM_Probe_Pseudo>(ps#_SGPR)>; def _SGPR_vi : SMEM_Real_Store_vi <op, !cast<SM_Probe_Pseudo>(ps#_SGPR)>;
} }
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} }
class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> : class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> :
SM_Real<ps>, SM_Real<ps>,
Enc64 { Enc64 {
let AssemblerPredicates = [isGFX7Only]; let AssemblerPredicates = [isGFX7Only];
let DecoderNamespace = "GFX7"; let DecoderNamespace = "GFX7";
let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, GLC:$glc); let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, GLC:$glc, DLC:$dlc);
let LGKM_CNT = ps.LGKM_CNT; let LGKM_CNT = ps.LGKM_CNT;
let SMRD = ps.SMRD; let SMRD = ps.SMRD;
let mayLoad = ps.mayLoad; let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore; let mayStore = ps.mayStore;
let hasSideEffects = ps.hasSideEffects; let hasSideEffects = ps.hasSideEffects;
let SchedRW = ps.SchedRW; let SchedRW = ps.SchedRW;
let UseNamedOperandTable = ps.UseNamedOperandTable; let UseNamedOperandTable = ps.UseNamedOperandTable;
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def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">; def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">; def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
multiclass SMRD_Pattern <string Instr, ValueType vt> { multiclass SMRD_Pattern <string Instr, ValueType vt> {
// 1. IMM offset // 1. IMM offset
def : GCNPat < def : GCNPat <
(smrd_load (SMRDImm i64:$sbase, i32:$offset)), (smrd_load (SMRDImm i64:$sbase, i32:$offset)),
(vt (!cast<SM_Pseudo>(Instr#"_IMM") $sbase, $offset, 0)) (vt (!cast<SM_Pseudo>(Instr#"_IMM") $sbase, $offset, 0, 0))
>; >;
// 2. 32-bit IMM offset on CI // 2. 32-bit IMM offset on CI
def : GCNPat < def : GCNPat <
(smrd_load (SMRDImm32 i64:$sbase, i32:$offset)), (smrd_load (SMRDImm32 i64:$sbase, i32:$offset)),
(vt (!cast<InstSI>(Instr#"_IMM_ci") $sbase, $offset, 0))> { (vt (!cast<InstSI>(Instr#"_IMM_ci") $sbase, $offset, 0, 0))> {
let OtherPredicates = [isGFX7Only]; let OtherPredicates = [isGFX7Only];
} }
// 3. SGPR offset // 3. SGPR offset
def : GCNPat < def : GCNPat <
(smrd_load (SMRDSgpr i64:$sbase, i32:$offset)), (smrd_load (SMRDSgpr i64:$sbase, i32:$offset)),
(vt (!cast<SM_Pseudo>(Instr#"_SGPR") $sbase, $offset, 0)) (vt (!cast<SM_Pseudo>(Instr#"_SGPR") $sbase, $offset, 0, 0))
>; >;
// 4. No offset // 4. No offset
def : GCNPat < def : GCNPat <
(vt (smrd_load (i64 SReg_64:$sbase))), (vt (smrd_load (i64 SReg_64:$sbase))),
(vt (!cast<SM_Pseudo>(Instr#"_IMM") i64:$sbase, 0, 0)) (vt (!cast<SM_Pseudo>(Instr#"_IMM") i64:$sbase, 0, 0, 0))
>; >;
} }
multiclass SMLoad_Pattern <string Instr, ValueType vt> { multiclass SMLoad_Pattern <string Instr, ValueType vt> {
// 1. Offset as an immediate // 1. Offset as an immediate
def : GCNPat < def : GCNPat <
(SIsbuffer_load v4i32:$sbase, (SMRDBufferImm i32:$offset), i1:$glc), (SIsbuffer_load v4i32:$sbase, (SMRDBufferImm i32:$offset), i1:$glc),
(vt (!cast<SM_Pseudo>(Instr#"_IMM") $sbase, $offset, (as_i1imm $glc))) (vt (!cast<SM_Pseudo>(Instr#"_IMM") $sbase, $offset, (as_i1imm $glc), 0))
>; >;
// 2. 32-bit IMM offset on CI // 2. 32-bit IMM offset on CI
def : GCNPat < def : GCNPat <
(vt (SIsbuffer_load v4i32:$sbase, (SMRDBufferImm32 i32:$offset), i1:$glc)), (vt (SIsbuffer_load v4i32:$sbase, (SMRDBufferImm32 i32:$offset), i1:$glc)),
(!cast<InstSI>(Instr#"_IMM_ci") $sbase, $offset, (as_i1imm $glc))> { (!cast<InstSI>(Instr#"_IMM_ci") $sbase, $offset, (as_i1imm $glc), 0)> {
let OtherPredicates = [isGFX7Only]; let OtherPredicates = [isGFX7Only];
} }
// 3. Offset loaded in an 32bit SGPR // 3. Offset loaded in an 32bit SGPR
def : GCNPat < def : GCNPat <
(SIsbuffer_load v4i32:$sbase, i32:$offset, i1:$glc), (SIsbuffer_load v4i32:$sbase, i32:$offset, i1:$glc),
(vt (!cast<SM_Pseudo>(Instr#"_SGPR") $sbase, $offset, (as_i1imm $glc))) (vt (!cast<SM_Pseudo>(Instr#"_SGPR") $sbase, $offset, (as_i1imm $glc), 0))
>; >;
} }
// Global and constant loads can be selected to either MUBUF or SMRD // Global and constant loads can be selected to either MUBUF or SMRD
// instructions, but SMRD instructions are faster so we want the instruction // instructions, but SMRD instructions are faster so we want the instruction
// selector to prefer those. // selector to prefer those.
let AddedComplexity = 100 in { let AddedComplexity = 100 in {
Show All 26 Lines
let OtherPredicates = [isGFX8Plus] in { let OtherPredicates = [isGFX8Plus] in {
def : GCNPat < def : GCNPat <
(i64 (readcyclecounter)), (i64 (readcyclecounter)),
(S_MEMREALTIME) (S_MEMREALTIME)
>; >;
} // let OtherPredicates = [isGFX8Plus] } // let OtherPredicates = [isGFX8Plus]
//===----------------------------------------------------------------------===//
// GFX10.
//===----------------------------------------------------------------------===//
class SMEM_Real_gfx10<bits<8> op, SM_Pseudo ps> :
SM_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX10>, Enc64 {
bit glc;
bit dlc;
let AssemblerPredicates = [isGFX10Plus];
let DecoderNamespace = "GFX10";
let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?);
let Inst{14} = !if(ps.has_dlc, dlc, ?);
let Inst{16} = !if(ps.has_glc, glc, ?);
let Inst{25-18} = op;
let Inst{31-26} = 0x3d;
let Inst{51-32} = !if(ps.offset_is_imm, !if(ps.has_offset, offset{19-0}, ?), ?);
let Inst{63-57} = !if(ps.offset_is_imm, !cast<int>(SGPR_NULL.HWEncoding),
!if(ps.has_offset, offset{6-0}, ?));
}
multiclass SM_Real_Loads_gfx10<bits<8> op, string ps,
SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
def _IMM_gfx10 : SMEM_Real_gfx10<op, immPs> {
let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc, DLC:$dlc);
}
def _SGPR_gfx10 : SMEM_Real_gfx10<op, sgprPs> {
let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc, DLC:$dlc);
}
}
class SMEM_Real_Store_gfx10<bits<8> op, SM_Pseudo ps> : SMEM_Real_gfx10<op, ps> {
bits<7> sdata;
let sdst = ?;
let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
}
multiclass SM_Real_Stores_gfx10<bits<8> op, string ps,
SM_Store_Pseudo immPs = !cast<SM_Store_Pseudo>(ps#_IMM),
SM_Store_Pseudo sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR)> {
// FIXME: The operand name $offset is inconsistent with $soff used
// in the pseudo
def _IMM_gfx10 : SMEM_Real_Store_gfx10 <op, immPs> {
let InOperandList = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc, DLC:$dlc);
}
def _SGPR_gfx10 : SMEM_Real_Store_gfx10 <op, sgprPs> {
let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc, DLC:$dlc);
}
}
defm S_LOAD_DWORD : SM_Real_Loads_gfx10<0x000, "S_LOAD_DWORD">;
defm S_LOAD_DWORDX2 : SM_Real_Loads_gfx10<0x001, "S_LOAD_DWORDX2">;
defm S_LOAD_DWORDX4 : SM_Real_Loads_gfx10<0x002, "S_LOAD_DWORDX4">;
defm S_LOAD_DWORDX8 : SM_Real_Loads_gfx10<0x003, "S_LOAD_DWORDX8">;
defm S_LOAD_DWORDX16 : SM_Real_Loads_gfx10<0x004, "S_LOAD_DWORDX16">;
let SubtargetPredicate = HasScalarFlatScratchInsts in {
defm S_SCRATCH_LOAD_DWORD : SM_Real_Loads_gfx10<0x005, "S_SCRATCH_LOAD_DWORD">;
defm S_SCRATCH_LOAD_DWORDX2 : SM_Real_Loads_gfx10<0x006, "S_SCRATCH_LOAD_DWORDX2">;
defm S_SCRATCH_LOAD_DWORDX4 : SM_Real_Loads_gfx10<0x007, "S_SCRATCH_LOAD_DWORDX4">;
} // End SubtargetPredicate = HasScalarFlatScratchInsts
defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_gfx10<0x008, "S_BUFFER_LOAD_DWORD">;
defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_gfx10<0x009, "S_BUFFER_LOAD_DWORDX2">;
defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_gfx10<0x00a, "S_BUFFER_LOAD_DWORDX4">;
defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_gfx10<0x00b, "S_BUFFER_LOAD_DWORDX8">;
defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_gfx10<0x00c, "S_BUFFER_LOAD_DWORDX16">;
let SubtargetPredicate = HasScalarStores in {
defm S_STORE_DWORD : SM_Real_Stores_gfx10<0x010, "S_STORE_DWORD">;
defm S_STORE_DWORDX2 : SM_Real_Stores_gfx10<0x011, "S_STORE_DWORDX2">;
defm S_STORE_DWORDX4 : SM_Real_Stores_gfx10<0x012, "S_STORE_DWORDX4">;
let OtherPredicates = [HasScalarFlatScratchInsts] in {
defm S_SCRATCH_STORE_DWORD : SM_Real_Stores_gfx10<0x015, "S_SCRATCH_STORE_DWORD">;
defm S_SCRATCH_STORE_DWORDX2 : SM_Real_Stores_gfx10<0x016, "S_SCRATCH_STORE_DWORDX2">;
defm S_SCRATCH_STORE_DWORDX4 : SM_Real_Stores_gfx10<0x017, "S_SCRATCH_STORE_DWORDX4">;
} // End OtherPredicates = [HasScalarFlatScratchInsts]
defm S_BUFFER_STORE_DWORD : SM_Real_Stores_gfx10<0x018, "S_BUFFER_STORE_DWORD">;
defm S_BUFFER_STORE_DWORDX2 : SM_Real_Stores_gfx10<0x019, "S_BUFFER_STORE_DWORDX2">;
defm S_BUFFER_STORE_DWORDX4 : SM_Real_Stores_gfx10<0x01a, "S_BUFFER_STORE_DWORDX4">;
} // End SubtargetPredicate = HasScalarStores
def S_MEMREALTIME_gfx10 : SMEM_Real_gfx10<0x025, S_MEMREALTIME>;
def S_MEMTIME_gfx10 : SMEM_Real_gfx10<0x024, S_MEMTIME>;
def S_GL1_INV_gfx10 : SMEM_Real_gfx10<0x01f, S_GL1_INV>;
def S_GET_WAVEID_IN_WORKGROUP_gfx10 : SMEM_Real_gfx10<0x02a, S_GET_WAVEID_IN_WORKGROUP>;
def S_DCACHE_INV_gfx10 : SMEM_Real_gfx10<0x020, S_DCACHE_INV>;
let SubtargetPredicate = HasScalarStores in {
def S_DCACHE_WB_gfx10 : SMEM_Real_gfx10<0x021, S_DCACHE_WB>;
} // End SubtargetPredicate = HasScalarStores
multiclass SM_Real_Probe_gfx10<bits<8> op, string ps> {
def _IMM_gfx10 : SMEM_Real_Store_gfx10 <op, !cast<SM_Pseudo>(ps#_IMM)>;
def _SGPR_gfx10 : SMEM_Real_Store_gfx10 <op, !cast<SM_Pseudo>(ps#_SGPR)>;
}
defm S_ATC_PROBE : SM_Real_Probe_gfx10 <0x26, "S_ATC_PROBE">;
defm S_ATC_PROBE_BUFFER : SM_Real_Probe_gfx10 <0x27, "S_ATC_PROBE_BUFFER">;
class SMEM_Atomic_Real_gfx10 <bits<8> op, SM_Atomic_Pseudo ps>
: SMEM_Real_gfx10 <op, ps> {
bits<7> sdata;
bit dlc;
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
let glc = ps.glc;
let Inst{14} = !if(ps.has_dlc, dlc, 0);
let Inst{12-6} = !if(glc, sdst{6-0}, sdata{6-0});
}
multiclass SM_Real_Atomics_gfx10<bits<8> op, string ps> {
def _IMM_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_IMM)>;
def _SGPR_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR)>;
def _IMM_RTN_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_IMM_RTN)>;
def _SGPR_RTN_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_RTN)>;
}
let SubtargetPredicate = HasScalarAtomics in {
defm S_BUFFER_ATOMIC_SWAP : SM_Real_Atomics_gfx10 <0x40, "S_BUFFER_ATOMIC_SWAP">;
defm S_BUFFER_ATOMIC_CMPSWAP : SM_Real_Atomics_gfx10 <0x41, "S_BUFFER_ATOMIC_CMPSWAP">;
defm S_BUFFER_ATOMIC_ADD : SM_Real_Atomics_gfx10 <0x42, "S_BUFFER_ATOMIC_ADD">;
defm S_BUFFER_ATOMIC_SUB : SM_Real_Atomics_gfx10 <0x43, "S_BUFFER_ATOMIC_SUB">;
defm S_BUFFER_ATOMIC_SMIN : SM_Real_Atomics_gfx10 <0x44, "S_BUFFER_ATOMIC_SMIN">;
defm S_BUFFER_ATOMIC_UMIN : SM_Real_Atomics_gfx10 <0x45, "S_BUFFER_ATOMIC_UMIN">;
defm S_BUFFER_ATOMIC_SMAX : SM_Real_Atomics_gfx10 <0x46, "S_BUFFER_ATOMIC_SMAX">;
defm S_BUFFER_ATOMIC_UMAX : SM_Real_Atomics_gfx10 <0x47, "S_BUFFER_ATOMIC_UMAX">;
defm S_BUFFER_ATOMIC_AND : SM_Real_Atomics_gfx10 <0x48, "S_BUFFER_ATOMIC_AND">;
defm S_BUFFER_ATOMIC_OR : SM_Real_Atomics_gfx10 <0x49, "S_BUFFER_ATOMIC_OR">;
defm S_BUFFER_ATOMIC_XOR : SM_Real_Atomics_gfx10 <0x4a, "S_BUFFER_ATOMIC_XOR">;
defm S_BUFFER_ATOMIC_INC : SM_Real_Atomics_gfx10 <0x4b, "S_BUFFER_ATOMIC_INC">;
defm S_BUFFER_ATOMIC_DEC : SM_Real_Atomics_gfx10 <0x4c, "S_BUFFER_ATOMIC_DEC">;
defm S_BUFFER_ATOMIC_SWAP_X2 : SM_Real_Atomics_gfx10 <0x60, "S_BUFFER_ATOMIC_SWAP_X2">;
defm S_BUFFER_ATOMIC_CMPSWAP_X2 : SM_Real_Atomics_gfx10 <0x61, "S_BUFFER_ATOMIC_CMPSWAP_X2">;
defm S_BUFFER_ATOMIC_ADD_X2 : SM_Real_Atomics_gfx10 <0x62, "S_BUFFER_ATOMIC_ADD_X2">;
defm S_BUFFER_ATOMIC_SUB_X2 : SM_Real_Atomics_gfx10 <0x63, "S_BUFFER_ATOMIC_SUB_X2">;
defm S_BUFFER_ATOMIC_SMIN_X2 : SM_Real_Atomics_gfx10 <0x64, "S_BUFFER_ATOMIC_SMIN_X2">;
defm S_BUFFER_ATOMIC_UMIN_X2 : SM_Real_Atomics_gfx10 <0x65, "S_BUFFER_ATOMIC_UMIN_X2">;
defm S_BUFFER_ATOMIC_SMAX_X2 : SM_Real_Atomics_gfx10 <0x66, "S_BUFFER_ATOMIC_SMAX_X2">;
defm S_BUFFER_ATOMIC_UMAX_X2 : SM_Real_Atomics_gfx10 <0x67, "S_BUFFER_ATOMIC_UMAX_X2">;
defm S_BUFFER_ATOMIC_AND_X2 : SM_Real_Atomics_gfx10 <0x68, "S_BUFFER_ATOMIC_AND_X2">;
defm S_BUFFER_ATOMIC_OR_X2 : SM_Real_Atomics_gfx10 <0x69, "S_BUFFER_ATOMIC_OR_X2">;
defm S_BUFFER_ATOMIC_XOR_X2 : SM_Real_Atomics_gfx10 <0x6a, "S_BUFFER_ATOMIC_XOR_X2">;
defm S_BUFFER_ATOMIC_INC_X2 : SM_Real_Atomics_gfx10 <0x6b, "S_BUFFER_ATOMIC_INC_X2">;
defm S_BUFFER_ATOMIC_DEC_X2 : SM_Real_Atomics_gfx10 <0x6c, "S_BUFFER_ATOMIC_DEC_X2">;
defm S_ATOMIC_SWAP : SM_Real_Atomics_gfx10 <0x80, "S_ATOMIC_SWAP">;
defm S_ATOMIC_CMPSWAP : SM_Real_Atomics_gfx10 <0x81, "S_ATOMIC_CMPSWAP">;
defm S_ATOMIC_ADD : SM_Real_Atomics_gfx10 <0x82, "S_ATOMIC_ADD">;
defm S_ATOMIC_SUB : SM_Real_Atomics_gfx10 <0x83, "S_ATOMIC_SUB">;
defm S_ATOMIC_SMIN : SM_Real_Atomics_gfx10 <0x84, "S_ATOMIC_SMIN">;
defm S_ATOMIC_UMIN : SM_Real_Atomics_gfx10 <0x85, "S_ATOMIC_UMIN">;
defm S_ATOMIC_SMAX : SM_Real_Atomics_gfx10 <0x86, "S_ATOMIC_SMAX">;
defm S_ATOMIC_UMAX : SM_Real_Atomics_gfx10 <0x87, "S_ATOMIC_UMAX">;
defm S_ATOMIC_AND : SM_Real_Atomics_gfx10 <0x88, "S_ATOMIC_AND">;
defm S_ATOMIC_OR : SM_Real_Atomics_gfx10 <0x89, "S_ATOMIC_OR">;
defm S_ATOMIC_XOR : SM_Real_Atomics_gfx10 <0x8a, "S_ATOMIC_XOR">;
defm S_ATOMIC_INC : SM_Real_Atomics_gfx10 <0x8b, "S_ATOMIC_INC">;
defm S_ATOMIC_DEC : SM_Real_Atomics_gfx10 <0x8c, "S_ATOMIC_DEC">;
defm S_ATOMIC_SWAP_X2 : SM_Real_Atomics_gfx10 <0xa0, "S_ATOMIC_SWAP_X2">;
defm S_ATOMIC_CMPSWAP_X2 : SM_Real_Atomics_gfx10 <0xa1, "S_ATOMIC_CMPSWAP_X2">;
defm S_ATOMIC_ADD_X2 : SM_Real_Atomics_gfx10 <0xa2, "S_ATOMIC_ADD_X2">;
defm S_ATOMIC_SUB_X2 : SM_Real_Atomics_gfx10 <0xa3, "S_ATOMIC_SUB_X2">;
defm S_ATOMIC_SMIN_X2 : SM_Real_Atomics_gfx10 <0xa4, "S_ATOMIC_SMIN_X2">;
defm S_ATOMIC_UMIN_X2 : SM_Real_Atomics_gfx10 <0xa5, "S_ATOMIC_UMIN_X2">;
defm S_ATOMIC_SMAX_X2 : SM_Real_Atomics_gfx10 <0xa6, "S_ATOMIC_SMAX_X2">;
defm S_ATOMIC_UMAX_X2 : SM_Real_Atomics_gfx10 <0xa7, "S_ATOMIC_UMAX_X2">;
defm S_ATOMIC_AND_X2 : SM_Real_Atomics_gfx10 <0xa8, "S_ATOMIC_AND_X2">;
defm S_ATOMIC_OR_X2 : SM_Real_Atomics_gfx10 <0xa9, "S_ATOMIC_OR_X2">;
defm S_ATOMIC_XOR_X2 : SM_Real_Atomics_gfx10 <0xaa, "S_ATOMIC_XOR_X2">;
defm S_ATOMIC_INC_X2 : SM_Real_Atomics_gfx10 <0xab, "S_ATOMIC_INC_X2">;
defm S_ATOMIC_DEC_X2 : SM_Real_Atomics_gfx10 <0xac, "S_ATOMIC_DEC_X2">;
multiclass SM_Real_Discard_gfx10<bits<8> op, string ps> {
def _IMM_gfx10 : SMEM_Real_gfx10 <op, !cast<SM_Pseudo>(ps#_IMM)>;
def _SGPR_gfx10 : SMEM_Real_gfx10 <op, !cast<SM_Pseudo>(ps#_SGPR)>;
}
defm S_DCACHE_DISCARD : SM_Real_Discard_gfx10 <0x28, "S_DCACHE_DISCARD">;
defm S_DCACHE_DISCARD_X2 : SM_Real_Discard_gfx10 <0x29, "S_DCACHE_DISCARD_X2">;
} // End SubtargetPredicate = HasScalarAtomics

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir

Show All 12 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr2_sgpr3 liveins: $sgpr2_sgpr3
; GCN-LABEL: name: copy ; GCN-LABEL: name: copy
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3 ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[COPY]] ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[COPY]]
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN: FLAT_STORE_DWORD [[COPY1]], [[DEF]], 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: FLAT_STORE_DWORD [[COPY1]], [[DEF]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%0:sgpr(p1) = COPY $sgpr2_sgpr3 %0:sgpr(p1) = COPY $sgpr2_sgpr3
%1:vgpr(p1) = COPY %0 %1:vgpr(p1) = COPY %0
%2:vgpr(s32) = G_IMPLICIT_DEF %2:vgpr(s32) = G_IMPLICIT_DEF
G_STORE %2, %1 :: (store 4 into %ir.global0) G_STORE %2, %1 :: (store 4 into %ir.global0)
... ...
--- ---

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN # RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
--- ---
name: implicit_def_s32 name: implicit_def_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr3_vgpr4 liveins: $vgpr3_vgpr4
; GCN-LABEL: name: implicit_def_s32 ; GCN-LABEL: name: implicit_def_s32
; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN: FLAT_STORE_DWORD [[COPY]], [[DEF]], 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: FLAT_STORE_DWORD [[COPY]], [[DEF]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%0:vgpr(p1) = COPY $vgpr3_vgpr4 %0:vgpr(p1) = COPY $vgpr3_vgpr4
%1:vgpr(s32) = G_IMPLICIT_DEF %1:vgpr(s32) = G_IMPLICIT_DEF
G_STORE %1, %0 :: (store 4, addrspace 1) G_STORE %1, %0 :: (store 4, addrspace 1)
... ...
--- ---
name: implicit_def_s64 name: implicit_def_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr3_vgpr4 liveins: $vgpr3_vgpr4
; GCN-LABEL: name: implicit_def_s64 ; GCN-LABEL: name: implicit_def_s64
; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: FLAT_STORE_DWORDX2 [[COPY]], [[DEF]], 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: FLAT_STORE_DWORDX2 [[COPY]], [[DEF]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%0:vgpr(p1) = COPY $vgpr3_vgpr4 %0:vgpr(p1) = COPY $vgpr3_vgpr4
%1:vgpr(s64) = G_IMPLICIT_DEF %1:vgpr(s64) = G_IMPLICIT_DEF
G_STORE %1, %0 :: (store 8, addrspace 1) G_STORE %1, %0 :: (store 8, addrspace 1)
--- ---
--- ---
name: implicit_def_p0 name: implicit_def_p0
Show All 13 Lines
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: implicit_def_p1 ; GCN-LABEL: name: implicit_def_p1
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%0:vgpr(p1) = G_IMPLICIT_DEF %0:vgpr(p1) = G_IMPLICIT_DEF
%1:vgpr(s32) = G_CONSTANT i32 4 %1:vgpr(s32) = G_CONSTANT i32 4
G_STORE %1, %0 :: (store 4, addrspace 1) G_STORE %1, %0 :: (store 4, addrspace 1)
... ...
--- ---
name: implicit_def_p3 name: implicit_def_p3
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: implicit_def_p3 ; GCN-LABEL: name: implicit_def_p3
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%0:vgpr(p3) = G_IMPLICIT_DEF %0:vgpr(p3) = G_IMPLICIT_DEF
%1:vgpr(s32) = G_CONSTANT i32 4 %1:vgpr(s32) = G_CONSTANT i32 4
G_STORE %1, %0 :: (store 4, addrspace 1) G_STORE %1, %0 :: (store 4, addrspace 1)
... ...
--- ---
name: implicit_def_p4 name: implicit_def_p4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: implicit_def_p4 ; GCN-LABEL: name: implicit_def_p4
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%0:vgpr(p4) = G_IMPLICIT_DEF %0:vgpr(p4) = G_IMPLICIT_DEF
%1:vgpr(s32) = G_CONSTANT i32 4 %1:vgpr(s32) = G_CONSTANT i32 4
G_STORE %1, %0 :: (store 4, addrspace 1) G_STORE %1, %0 :: (store 4, addrspace 1)
... ...

llvm/trunk/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir

# RUN: llc -march=amdgcn -mcpu=carrizo -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK %s # RUN: llc -march=amdgcn -mcpu=carrizo -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK %s
# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK %s # RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK %s
--- ---
# Trivial clause at beginning of program # Trivial clause at beginning of program
name: trivial_smem_clause_load_smrd4_x1 name: trivial_smem_clause_load_smrd4_x1
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x1 ; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x1
; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Trivial clause at beginning of program # Trivial clause at beginning of program
name: trivial_smem_clause_load_smrd4_x2 name: trivial_smem_clause_load_smrd4_x2
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x2 ; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x2
; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr1 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 ; GCN-NEXT: $sgpr1 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr1 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 $sgpr1 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Trivial clause at beginning of program # Trivial clause at beginning of program
name: trivial_smem_clause_load_smrd4_x3 name: trivial_smem_clause_load_smrd4_x3
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x3 ; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x3
; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
; GCN-NEXT: $sgpr1 = S_LOAD_DWORD_IMM $sgpr6_sgpr7, 0, 0 ; GCN-NEXT: $sgpr1 = S_LOAD_DWORD_IMM $sgpr6_sgpr7, 0, 0, 0
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0 ; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr0 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 $sgpr0 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
$sgpr1 = S_LOAD_DWORD_IMM $sgpr6_sgpr7, 0, 0 $sgpr1 = S_LOAD_DWORD_IMM $sgpr6_sgpr7, 0, 0, 0
$sgpr2 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0 $sgpr2 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Trivial clause at beginning of program # Trivial clause at beginning of program
name: trivial_smem_clause_load_smrd4_x4 name: trivial_smem_clause_load_smrd4_x4
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x4 ; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x4
; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
; GCN-NEXT: $sgpr1 = S_LOAD_DWORD_IMM $sgpr8_sgpr9, 0, 0 ; GCN-NEXT: $sgpr1 = S_LOAD_DWORD_IMM $sgpr8_sgpr9, 0, 0, 0
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0 ; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0, 0
; GCN-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr16_sgpr17, 0, 0 ; GCN-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr16_sgpr17, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr0 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 $sgpr0 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
$sgpr1 = S_LOAD_DWORD_IMM $sgpr8_sgpr9, 0, 0 $sgpr1 = S_LOAD_DWORD_IMM $sgpr8_sgpr9, 0, 0, 0
$sgpr2 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0 $sgpr2 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0, 0
$sgpr3 = S_LOAD_DWORD_IMM $sgpr16_sgpr17, 0, 0 $sgpr3 = S_LOAD_DWORD_IMM $sgpr16_sgpr17, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Reuse of same input pointer is OK # Reuse of same input pointer is OK
name: trivial_smem_clause_load_smrd4_x2_sameptr name: trivial_smem_clause_load_smrd4_x2_sameptr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x2_sameptr ; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x2_sameptr
; GCN: $sgpr12 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr12 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr13 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr13 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr12 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr12 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr13 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr13 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# 32-bit load partially clobbers its own ptr reg # 32-bit load partially clobbers its own ptr reg
name: smrd_load4_overwrite_ptr_lo name: smrd_load4_overwrite_ptr_lo
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: smrd_load4_overwrite_ptr_lo ; GCN-LABEL: name: smrd_load4_overwrite_ptr_lo
; GCN: $sgpr10 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr10 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr10 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr10 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# 32-bit load partially clobbers its own ptr reg # 32-bit load partially clobbers its own ptr reg
name: smrd_load4_overwrite_ptr_hi name: smrd_load4_overwrite_ptr_hi
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: smrd_load4_overwrite_ptr_hi ; GCN-LABEL: name: smrd_load4_overwrite_ptr_hi
; GCN: $sgpr11 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr11 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr11 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr11 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# 64-bit load clobbers its own ptr reg # 64-bit load clobbers its own ptr reg
name: smrd_load8_overwrite_ptr name: smrd_load8_overwrite_ptr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: smrd_load8_overwrite_ptr ; GCN-LABEL: name: smrd_load8_overwrite_ptr
; GCN: $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0 $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# vmcnt has 4 bits, so maximum 16 outstanding loads. The waitcnt # vmcnt has 4 bits, so maximum 16 outstanding loads. The waitcnt
# breaks the clause. # breaks the clause.
name: break_smem_clause_at_max_smem_clause_size_smrd_load4 name: break_smem_clause_at_max_smem_clause_size_smrd_load4
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_smem_clause_at_max_smem_clause_size_smrd_load4 ; GCN-LABEL: name: break_smem_clause_at_max_smem_clause_size_smrd_load4
; GCN: $sgpr13 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr13 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr14 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr14 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr15 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr15 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr16 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr16 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr17 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr17 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr18 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr18 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr19 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr19 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr20 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr20 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr21 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr21 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr22 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr22 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr23 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr23 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr24 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr24 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr25 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr25 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr26 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr26 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr27 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr27 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr28 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN-NEXT: $sgpr28 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr30_sgpr31, 0, 0 ; GCN-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr30_sgpr31, 0, 0, 0
; GCN-NEXT: $sgpr0 = S_MOV_B32 $sgpr0, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28 ; GCN-NEXT: $sgpr0 = S_MOV_B32 $sgpr0, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr13 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr13 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr14 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr14 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr15 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr15 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr16 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr16 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr17 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr17 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr18 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr18 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr19 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr19 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr20 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr20 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr21 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr21 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr22 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr22 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr23 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr23 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr24 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr24 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr25 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr25 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr26 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr26 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr27 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr27 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr28 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr28 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr0 = S_LOAD_DWORD_IMM $sgpr30_sgpr31, 0, 0 $sgpr0 = S_LOAD_DWORD_IMM $sgpr30_sgpr31, 0, 0, 0
$sgpr0 = S_MOV_B32 $sgpr0, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28 $sgpr0 = S_MOV_B32 $sgpr0, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: break_smem_clause_simple_load_smrd4_lo_ptr name: break_smem_clause_simple_load_smrd4_lo_ptr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_smem_clause_simple_load_smrd4_lo_ptr ; GCN-LABEL: name: break_smem_clause_simple_load_smrd4_lo_ptr
; GCN: $sgpr10 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr10 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $sgpr12 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 ; GCN-NEXT: $sgpr12 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr10 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr10 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr12 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 $sgpr12 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: break_smem_clause_simple_load_smrd4_hi_ptr name: break_smem_clause_simple_load_smrd4_hi_ptr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_smem_clause_simple_load_smrd4_hi_ptr ; GCN-LABEL: name: break_smem_clause_simple_load_smrd4_hi_ptr
; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 ; GCN-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr3 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 $sgpr3 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: break_smem_clause_simple_load_smrd8_ptr name: break_smem_clause_simple_load_smrd8_ptr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_smem_clause_simple_load_smrd8_ptr ; GCN-LABEL: name: break_smem_clause_simple_load_smrd8_ptr
; GCN: $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, 0
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0 ; GCN-NEXT: $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0 $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0 $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: break_smem_clause_simple_load_smrd16_ptr name: break_smem_clause_simple_load_smrd16_ptr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_smem_clause_simple_load_smrd16_ptr ; GCN-LABEL: name: break_smem_clause_simple_load_smrd16_ptr
; GCN: $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr12_sgpr13_sgpr14_sgpr15 = S_LOAD_DWORDX4_IMM $sgpr6_sgpr7, 0, 0 ; GCN-NEXT: $sgpr12_sgpr13_sgpr14_sgpr15 = S_LOAD_DWORDX4_IMM $sgpr6_sgpr7, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0 $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr12_sgpr13_sgpr14_sgpr15 = S_LOAD_DWORDX4_IMM $sgpr6_sgpr7, 0, 0 $sgpr12_sgpr13_sgpr14_sgpr15 = S_LOAD_DWORDX4_IMM $sgpr6_sgpr7, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: break_smem_clause_block_boundary_load_smrd8_ptr name: break_smem_clause_block_boundary_load_smrd8_ptr
body: | body: |
; GCN-LABEL: name: break_smem_clause_block_boundary_load_smrd8_ptr ; GCN-LABEL: name: break_smem_clause_block_boundary_load_smrd8_ptr
; GCN: bb.0: ; GCN: bb.0:
; GCN: successors: %bb.1(0x80000000) ; GCN: successors: %bb.1(0x80000000)
; GCN: $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN: bb.1: ; GCN: bb.1:
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0 ; GCN-NEXT: $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
bb.0: bb.0:
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0 $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, 0
bb.1: bb.1:
$sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0 $sgpr10_sgpr11 = S_LOAD_DWORDX2_IMM $sgpr12_sgpr13, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# The load clobbers the pointer of the store, so it needs to break. # The load clobbers the pointer of the store, so it needs to break.
name: break_smem_clause_store_load_into_ptr_smrd4 name: break_smem_clause_store_load_into_ptr_smrd4
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_smem_clause_store_load_into_ptr_smrd4 ; GCN-LABEL: name: break_smem_clause_store_load_into_ptr_smrd4
; GCN: S_STORE_DWORD_IMM $sgpr16, $sgpr10_sgpr11, 0, 0 ; GCN: S_STORE_DWORD_IMM $sgpr16, $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr12 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0 ; GCN-NEXT: $sgpr12 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
S_STORE_DWORD_IMM $sgpr16, $sgpr10_sgpr11, 0, 0 S_STORE_DWORD_IMM $sgpr16, $sgpr10_sgpr11, 0, 0, 0
$sgpr12 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0 $sgpr12 = S_LOAD_DWORD_IMM $sgpr14_sgpr15, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# The load clobbers the data of the store, so it needs to break. # The load clobbers the data of the store, so it needs to break.
# FIXME: Would it be better to s_nop and wait later? # FIXME: Would it be better to s_nop and wait later?
name: break_smem_clause_store_load_into_data_smrd4 name: break_smem_clause_store_load_into_data_smrd4
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_smem_clause_store_load_into_data_smrd4 ; GCN-LABEL: name: break_smem_clause_store_load_into_data_smrd4
; GCN: S_STORE_DWORD_IMM $sgpr8, $sgpr10_sgpr11, 0, 0 ; GCN: S_STORE_DWORD_IMM $sgpr8, $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr8 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 ; GCN-NEXT: $sgpr8 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
S_STORE_DWORD_IMM $sgpr8, $sgpr10_sgpr11, 0, 0 S_STORE_DWORD_IMM $sgpr8, $sgpr10_sgpr11, 0, 0, 0
$sgpr8 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 $sgpr8 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Regular VALU instruction breaks clause, no nop needed # Regular VALU instruction breaks clause, no nop needed
name: valu_inst_breaks_smem_clause name: valu_inst_breaks_smem_clause
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: valu_inst_breaks_smem_clause ; GCN-LABEL: name: valu_inst_breaks_smem_clause
; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $vgpr8 = V_MOV_B32_e32 0, implicit $exec ; GCN-NEXT: $vgpr8 = V_MOV_B32_e32 0, implicit $exec
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 ; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$vgpr8 = V_MOV_B32_e32 0, implicit $exec $vgpr8 = V_MOV_B32_e32 0, implicit $exec
$sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Regular SALU instruction breaks clause, no nop needed # Regular SALU instruction breaks clause, no nop needed
name: salu_inst_breaks_smem_clause name: salu_inst_breaks_smem_clause
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: salu_inst_breaks_smem_clause ; GCN-LABEL: name: salu_inst_breaks_smem_clause
; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $sgpr8 = S_MOV_B32 0 ; GCN-NEXT: $sgpr8 = S_MOV_B32 0
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 ; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$sgpr8 = S_MOV_B32 0 $sgpr8 = S_MOV_B32 0
$sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: ds_inst_breaks_smem_clause name: ds_inst_breaks_smem_clause
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: ds_inst_breaks_smem_clause ; GCN-LABEL: name: ds_inst_breaks_smem_clause
; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $vgpr8 = DS_READ_B32 $vgpr9, 0, 0, implicit $m0, implicit $exec ; GCN-NEXT: $vgpr8 = DS_READ_B32 $vgpr9, 0, 0, implicit $m0, implicit $exec
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 ; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$vgpr8 = DS_READ_B32 $vgpr9, 0, 0, implicit $m0, implicit $exec $vgpr8 = DS_READ_B32 $vgpr9, 0, 0, implicit $m0, implicit $exec
$sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: flat_inst_breaks_smem_clause name: flat_inst_breaks_smem_clause
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: flat_inst_breaks_smem_clause ; GCN-LABEL: name: flat_inst_breaks_smem_clause
; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 ; GCN: $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
; GCN-NEXT: $vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 ; GCN-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0 $sgpr0 = S_LOAD_DWORD_IMM $sgpr10_sgpr11, 0, 0, 0
$vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0 $sgpr2 = S_LOAD_DWORD_IMM $sgpr12_sgpr13, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# FIXME: Should this be handled? # FIXME: Should this be handled?
name: implicit_use_breaks_smem_clause name: implicit_use_breaks_smem_clause
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: implicit_use_breaks_smem_clause ; GCN-LABEL: name: implicit_use_breaks_smem_clause
; GCN: $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, implicit $sgpr12_sgpr13 ; GCN: $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, 0, implicit $sgpr12_sgpr13
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $sgpr12_sgpr13 = S_LOAD_DWORDX2_IMM $sgpr6_sgpr7, 0, 0 ; GCN-NEXT: $sgpr12_sgpr13 = S_LOAD_DWORDX2_IMM $sgpr6_sgpr7, 0, 0, 0
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, implicit $sgpr12_sgpr13 $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, 0, implicit $sgpr12_sgpr13
$sgpr12_sgpr13 = S_LOAD_DWORDX2_IMM $sgpr6_sgpr7, 0, 0 $sgpr12_sgpr13 = S_LOAD_DWORDX2_IMM $sgpr6_sgpr7, 0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir

# RUN: llc -march=amdgcn -mcpu=carrizo -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK %s # RUN: llc -march=amdgcn -mcpu=carrizo -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK %s
# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK %s # RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK %s
--- ---
# Trivial clause at beginning of program # Trivial clause at beginning of program
name: trivial_clause_load_flat4_x1 name: trivial_clause_load_flat4_x1
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: trivial_clause_load_flat4_x1 ; GCN-LABEL: name: trivial_clause_load_flat4_x1
; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Trivial clause at beginning of program # Trivial clause at beginning of program
name: trivial_clause_load_flat4_x2 name: trivial_clause_load_flat4_x2
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: trivial_clause_load_flat4_x2 ; GCN-LABEL: name: trivial_clause_load_flat4_x2
; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr1 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr1 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Trivial clause at beginning of program # Trivial clause at beginning of program
name: trivial_clause_load_flat4_x3 name: trivial_clause_load_flat4_x3
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: trivial_clause_load_flat4_x3 ; GCN-LABEL: name: trivial_clause_load_flat4_x3
; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr3_vgpr4, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr3_vgpr4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr5_vgpr6, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr5_vgpr6, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr7_vgpr8, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr7_vgpr8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0 = FLAT_LOAD_DWORD $vgpr3_vgpr4, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr3_vgpr4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr1 = FLAT_LOAD_DWORD $vgpr5_vgpr6, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr1 = FLAT_LOAD_DWORD $vgpr5_vgpr6, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr2 = FLAT_LOAD_DWORD $vgpr7_vgpr8, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2 = FLAT_LOAD_DWORD $vgpr7_vgpr8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Trivial clause at beginning of program # Trivial clause at beginning of program
name: trivial_clause_load_flat4_x4 name: trivial_clause_load_flat4_x4
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: trivial_clause_load_flat4_x4 ; GCN-LABEL: name: trivial_clause_load_flat4_x4
; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr6_vgpr7, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr6_vgpr7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr8_vgpr9, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr8_vgpr9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr3 = FLAT_LOAD_DWORD $vgpr10_vgpr11, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr3 = FLAT_LOAD_DWORD $vgpr10_vgpr11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr1 = FLAT_LOAD_DWORD $vgpr6_vgpr7, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr1 = FLAT_LOAD_DWORD $vgpr6_vgpr7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr2 = FLAT_LOAD_DWORD $vgpr8_vgpr9, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2 = FLAT_LOAD_DWORD $vgpr8_vgpr9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr3 = FLAT_LOAD_DWORD $vgpr10_vgpr11, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr3 = FLAT_LOAD_DWORD $vgpr10_vgpr11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Reuse of same input pointer is OK # Reuse of same input pointer is OK
name: trivial_clause_load_flat4_x2_sameptr name: trivial_clause_load_flat4_x2_sameptr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: trivial_clause_load_flat4_x2_sameptr ; GCN-LABEL: name: trivial_clause_load_flat4_x2_sameptr
; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr1 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr1 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# 32-bit load partially clobbers its own ptr reg # 32-bit load partially clobbers its own ptr reg
name: flat_load4_overwrite_ptr_lo name: flat_load4_overwrite_ptr_lo
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: flat_load4_overwrite_ptr_lo ; GCN-LABEL: name: flat_load4_overwrite_ptr_lo
; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# 32-bit load partially clobbers its own ptr reg # 32-bit load partially clobbers its own ptr reg
name: flat_load4_overwrite_ptr_hi name: flat_load4_overwrite_ptr_hi
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: flat_load4_overwrite_ptr_hi ; GCN-LABEL: name: flat_load4_overwrite_ptr_hi
; GCN: $vgpr1 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr1 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr1 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr1 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# 64-bit load clobbers its own ptr reg # 64-bit load clobbers its own ptr reg
name: flat_load8_overwrite_ptr name: flat_load8_overwrite_ptr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: flat_load8_overwrite_ptr ; GCN-LABEL: name: flat_load8_overwrite_ptr
; GCN: $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# vmcnt has 4 bits, so maximum 16 outstanding loads. The waitcnt # vmcnt has 4 bits, so maximum 16 outstanding loads. The waitcnt
# breaks the clause. # breaks the clause.
name: break_clause_at_max_clause_size_flat_load4 name: break_clause_at_max_clause_size_flat_load4
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_clause_at_max_clause_size_flat_load4 ; GCN-LABEL: name: break_clause_at_max_clause_size_flat_load4
; GCN: $vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr3 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr3 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr4 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr4 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr5 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr5 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr6 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr6 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr7 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr7 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr8 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr8 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr9 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr9 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr10 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr10 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr11 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr11 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr12 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr12 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr13 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr13 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr14 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr14 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr15 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr15 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr16 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr16 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr17 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr17 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $sgpr0 = S_MOV_B32 $sgpr0, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18 ; GCN-NEXT: $sgpr0 = S_MOV_B32 $sgpr0, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr3 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr3 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr4 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr4 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr5 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr5 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr6 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr6 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr7 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr7 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr8 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr8 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr9 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr9 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr10 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr10 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr11 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr11 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr12 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr12 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr13 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr13 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr14 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr14 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr15 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr15 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr16 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr16 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr17 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr17 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$sgpr0 = S_MOV_B32 $sgpr0, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18 $sgpr0 = S_MOV_B32 $sgpr0, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: break_clause_simple_load_flat4_lo_ptr name: break_clause_simple_load_flat4_lo_ptr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_clause_simple_load_flat4_lo_ptr ; GCN-LABEL: name: break_clause_simple_load_flat4_lo_ptr
; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: break_clause_simple_load_flat4_hi_ptr name: break_clause_simple_load_flat4_hi_ptr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_clause_simple_load_flat4_hi_ptr ; GCN-LABEL: name: break_clause_simple_load_flat4_hi_ptr
; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $vgpr3 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr3 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr3 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr3 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: break_clause_simple_load_flat8_ptr name: break_clause_simple_load_flat8_ptr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_clause_simple_load_flat8_ptr ; GCN-LABEL: name: break_clause_simple_load_flat8_ptr
; GCN: $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: break_clause_simple_load_flat16_ptr name: break_clause_simple_load_flat16_ptr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_clause_simple_load_flat16_ptr ; GCN-LABEL: name: break_clause_simple_load_flat16_ptr
; GCN: $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $vgpr2_vgpr3_vgpr4_vgpr5 = FLAT_LOAD_DWORDX4 $vgpr6_vgpr7, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr2_vgpr3_vgpr4_vgpr5 = FLAT_LOAD_DWORDX4 $vgpr6_vgpr7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr2_vgpr3_vgpr4_vgpr5 = FLAT_LOAD_DWORDX4 $vgpr6_vgpr7, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2_vgpr3_vgpr4_vgpr5 = FLAT_LOAD_DWORDX4 $vgpr6_vgpr7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# The clause is broken by the waitcnt inserted at the end of the # The clause is broken by the waitcnt inserted at the end of the
# block, so no nop is needed. # block, so no nop is needed.
name: break_clause_block_boundary_load_flat8_ptr name: break_clause_block_boundary_load_flat8_ptr
body: | body: |
; GCN-LABEL: name: break_clause_block_boundary_load_flat8_ptr ; GCN-LABEL: name: break_clause_block_boundary_load_flat8_ptr
; GCN: bb.0: ; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x80000000) ; GCN-NEXT: successors: %bb.1(0x80000000)
; GCN: $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN: bb.1: ; GCN: bb.1:
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
bb.0: bb.0:
$vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
bb.1: bb.1:
$vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2_vgpr3 = FLAT_LOAD_DWORDX2 $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# The load clobbers the pointer of the store, so it needs to break. # The load clobbers the pointer of the store, so it needs to break.
name: break_clause_store_load_into_ptr_flat4 name: break_clause_store_load_into_ptr_flat4
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_clause_store_load_into_ptr_flat4 ; GCN-LABEL: name: break_clause_store_load_into_ptr_flat4
; GCN: FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# The load clobbers the data of the store, so it needs to break. # The load clobbers the data of the store, so it needs to break.
# FIXME: Would it be better to s_nop and wait later? # FIXME: Would it be better to s_nop and wait later?
name: break_clause_store_load_into_data_flat4 name: break_clause_store_load_into_data_flat4
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_clause_store_load_into_data_flat4 ; GCN-LABEL: name: break_clause_store_load_into_data_flat4
; GCN: FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr0 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr0 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr0 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Regular VALU instruction breaks clause, no nop needed # Regular VALU instruction breaks clause, no nop needed
name: valu_inst_breaks_clause name: valu_inst_breaks_clause
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: valu_inst_breaks_clause ; GCN-LABEL: name: valu_inst_breaks_clause
; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr8 = V_MOV_B32_e32 0, implicit $exec ; GCN-NEXT: $vgpr8 = V_MOV_B32_e32 0, implicit $exec
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr8 = V_MOV_B32_e32 0, implicit $exec $vgpr8 = V_MOV_B32_e32 0, implicit $exec
$vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Regular SALU instruction breaks clause, no nop needed # Regular SALU instruction breaks clause, no nop needed
name: salu_inst_breaks_clause name: salu_inst_breaks_clause
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: salu_inst_breaks_clause ; GCN-LABEL: name: salu_inst_breaks_clause
; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $sgpr8 = S_MOV_B32 0 ; GCN-NEXT: $sgpr8 = S_MOV_B32 0
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$sgpr8 = S_MOV_B32 0 $sgpr8 = S_MOV_B32 0
$vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: ds_inst_breaks_clause name: ds_inst_breaks_clause
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: ds_inst_breaks_clause ; GCN-LABEL: name: ds_inst_breaks_clause
; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr8 = DS_READ_B32 $vgpr9, 0, 0, implicit $m0, implicit $exec ; GCN-NEXT: $vgpr8 = DS_READ_B32 $vgpr9, 0, 0, implicit $m0, implicit $exec
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr8 = DS_READ_B32 $vgpr9, 0, 0, implicit $m0, implicit $exec $vgpr8 = DS_READ_B32 $vgpr9, 0, 0, implicit $m0, implicit $exec
$vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: smrd_inst_breaks_clause name: smrd_inst_breaks_clause
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: smrd_inst_breaks_clause ; GCN-LABEL: name: smrd_inst_breaks_clause
; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $sgpr8 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0 ; GCN-NEXT: $sgpr8 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$sgpr8 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0 $sgpr8 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
$vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# FIXME: Should this be handled? # FIXME: Should this be handled?
name: implicit_use_breaks_clause name: implicit_use_breaks_clause
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: implicit_use_breaks_clause ; GCN-LABEL: name: implicit_use_breaks_clause
; GCN: $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr4_vgpr5 ; GCN: $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr4_vgpr5
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $vgpr4_vgpr5 = FLAT_LOAD_DWORDX2 $vgpr6_vgpr7, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr4_vgpr5 = FLAT_LOAD_DWORDX2 $vgpr6_vgpr7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr4_vgpr5 $vgpr0_vgpr1 = FLAT_LOAD_DWORDX2 $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr4_vgpr5
$vgpr4_vgpr5 = FLAT_LOAD_DWORDX2 $vgpr6_vgpr7, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr4_vgpr5 = FLAT_LOAD_DWORDX2 $vgpr6_vgpr7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: trivial_clause_load_mubuf4_x2 name: trivial_clause_load_mubuf4_x2
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: trivial_clause_load_mubuf4_x2 ; GCN-LABEL: name: trivial_clause_load_mubuf4_x2
; GCN: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec ; GCN: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
; GCN-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFEN $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec ; GCN-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFEN $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
$vgpr3 = BUFFER_LOAD_DWORD_OFFEN $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec $vgpr3 = BUFFER_LOAD_DWORD_OFFEN $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: break_clause_simple_load_mubuf_offen_ptr name: break_clause_simple_load_mubuf_offen_ptr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_clause_simple_load_mubuf_offen_ptr ; GCN-LABEL: name: break_clause_simple_load_mubuf_offen_ptr
; GCN: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec ; GCN: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec ; GCN-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
$vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec $vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# BUFFER instructions overwriting their own inputs is supposedly OK. # BUFFER instructions overwriting their own inputs is supposedly OK.
name: mubuf_load4_overwrite_ptr name: mubuf_load4_overwrite_ptr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: mubuf_load4_overwrite_ptr ; GCN-LABEL: name: mubuf_load4_overwrite_ptr
; GCN: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec ; GCN: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
; GCN-NEXT: $vgpr1 = V_MOV_B32_e32 0, implicit $exec ; GCN-NEXT: $vgpr1 = V_MOV_B32_e32 0, implicit $exec
; GCN-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec ; GCN-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
$vgpr1 = V_MOV_B32_e32 0, implicit $exec $vgpr1 = V_MOV_B32_e32 0, implicit $exec
$vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Break a clause from interference between mubuf and flat instructions # Break a clause from interference between mubuf and flat instructions
name: break_clause_flat_load_mubuf_load name: break_clause_flat_load_mubuf_load
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_clause_flat_load_mubuf_load ; GCN-LABEL: name: break_clause_flat_load_mubuf_load
; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec ; GCN-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec $vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
# Break a clause from interference between mubuf and flat instructions # Break a clause from interference between mubuf and flat instructions
# GCN-LABEL: name: break_clause_mubuf_load_flat_load # GCN-LABEL: name: break_clause_mubuf_load_flat_load
# GCN: bb.0: # GCN: bb.0:
# GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4 # GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
# XNACK-NEXT: S_NOP 0 # XNACK-NEXT: S_NOP 0
# GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr2_vgpr3 # GCN-NEXT: $vgpr1 = FLAT_LOAD_DWORD $vgpr2_vgpr3
# GCN-NEXT: S_ENDPGM 0 # GCN-NEXT: S_ENDPGM 0
name: break_clause_mubuf_load_flat_load name: break_clause_mubuf_load_flat_load
body: | body: |
bb.0: bb.0:
$vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
$vgpr1 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr1 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: break_clause_atomic_rtn_into_ptr_flat4 name: break_clause_atomic_rtn_into_ptr_flat4
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_clause_atomic_rtn_into_ptr_flat4 ; GCN-LABEL: name: break_clause_atomic_rtn_into_ptr_flat4
; GCN: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $vgpr4 = FLAT_ATOMIC_ADD_RTN $vgpr5_vgpr6, $vgpr7, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr4 = FLAT_ATOMIC_ADD_RTN $vgpr5_vgpr6, $vgpr7, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr4 = FLAT_ATOMIC_ADD_RTN $vgpr5_vgpr6, $vgpr7, 0, 0, implicit $exec, implicit $flat_scr $vgpr4 = FLAT_ATOMIC_ADD_RTN $vgpr5_vgpr6, $vgpr7, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: break_clause_atomic_nortn_ptr_load_flat4 name: break_clause_atomic_nortn_ptr_load_flat4
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_clause_atomic_nortn_ptr_load_flat4 ; GCN-LABEL: name: break_clause_atomic_nortn_ptr_load_flat4
; GCN: FLAT_ATOMIC_ADD $vgpr0_vgpr1, $vgpr2, 0, 0, implicit $exec, implicit $flat_scr ; GCN: FLAT_ATOMIC_ADD $vgpr0_vgpr1, $vgpr2, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr3_vgpr4, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr3_vgpr4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
FLAT_ATOMIC_ADD $vgpr0_vgpr1, $vgpr2, 0, 0, implicit $exec, implicit $flat_scr FLAT_ATOMIC_ADD $vgpr0_vgpr1, $vgpr2, 0, 0, implicit $exec, implicit $flat_scr
$vgpr2 = FLAT_LOAD_DWORD $vgpr3_vgpr4, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr2 = FLAT_LOAD_DWORD $vgpr3_vgpr4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: break_clause_atomic_rtn_into_ptr_mubuf4 name: break_clause_atomic_rtn_into_ptr_mubuf4
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_clause_atomic_rtn_into_ptr_mubuf4 ; GCN-LABEL: name: break_clause_atomic_rtn_into_ptr_mubuf4
; GCN: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec ; GCN: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: $vgpr2 = BUFFER_ATOMIC_ADD_OFFEN_RTN $vgpr2, $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, implicit $exec ; GCN-NEXT: $vgpr2 = BUFFER_ATOMIC_ADD_OFFEN_RTN $vgpr2, $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
$vgpr2 = BUFFER_ATOMIC_ADD_OFFEN_RTN $vgpr2, $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, implicit $exec $vgpr2 = BUFFER_ATOMIC_ADD_OFFEN_RTN $vgpr2, $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: break_clause_atomic_nortn_ptr_load_mubuf4 name: break_clause_atomic_nortn_ptr_load_mubuf4
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: break_clause_atomic_nortn_ptr_load_mubuf4 ; GCN-LABEL: name: break_clause_atomic_nortn_ptr_load_mubuf4
; GCN: BUFFER_ATOMIC_ADD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, implicit $exec ; GCN: BUFFER_ATOMIC_ADD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, implicit $exec
; GCN-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec ; GCN-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
BUFFER_ATOMIC_ADD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, implicit $exec BUFFER_ATOMIC_ADD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, implicit $exec
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Make sure there is no assert on mubuf instructions which do not have # Make sure there is no assert on mubuf instructions which do not have
# vaddr, and don't add register to track. # vaddr, and don't add register to track.
name: no_break_clause_mubuf_load_novaddr name: no_break_clause_mubuf_load_novaddr
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: no_break_clause_mubuf_load_novaddr ; GCN-LABEL: name: no_break_clause_mubuf_load_novaddr
; GCN: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec ; GCN: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
; GCN-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec ; GCN-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
$vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
$vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Loads and stores using different addresses theoretically does not # Loads and stores using different addresses theoretically does not
# need a nop # need a nop
name: mix_load_store_clause name: mix_load_store_clause
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: mix_load_store_clause ; GCN-LABEL: name: mix_load_store_clause
; GCN: FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr10 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr10 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr6, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr6, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr11 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr11 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr10 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr10 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr6, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD $vgpr2_vgpr3, $vgpr6, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr11 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr11 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Loads and stores using the same address needs a nop. # Loads and stores using the same address needs a nop.
name: mix_load_store_clause_same_address name: mix_load_store_clause_same_address
body: | body: |
bb.0: bb.0:
; GCN-LABEL: name: mix_load_store_clause_same_address ; GCN-LABEL: name: mix_load_store_clause_same_address
; GCN: FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN: FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr10 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr10 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; XNACK-NEXT: S_NOP 0 ; XNACK-NEXT: S_NOP 0
; GCN-NEXT: FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr6, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr6, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: $vgpr11 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr ; GCN-NEXT: $vgpr11 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr10 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr10 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr6, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr6, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr11 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr11 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/clamp-omod-special-case.mir

Show All 37 Linesliveins:
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
- { reg: '$vgpr0', virtual-reg: '%3' } - { reg: '$vgpr0', virtual-reg: '%3' }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0:: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%24 = V_ASHRREV_I32_e32 31, %3, implicit $exec %24 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%25 = REG_SEQUENCE %3, 1, %24, 2 %25 = REG_SEQUENCE %3, 1, %24, 2
%10 = S_MOV_B32 61440 %10 = S_MOV_B32 61440
%11 = S_MOV_B32 0 %11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18 %13 = REG_SEQUENCE killed %5, 17, %12, 18
%14 = S_MOV_B32 2 %14 = S_MOV_B32 2
%26 = V_LSHL_B64 killed %25, 2, implicit $exec %26 = V_LSHL_B64 killed %25, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18 %16 = REG_SEQUENCE killed %4, 17, %12, 18
%18 = COPY %26 %18 = COPY %26
%17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit $exec %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, implicit $exec
%20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
%21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 0, 0, implicit $exec %21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 0, 0, implicit $exec
BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: v_clamp_omod_already_set_f32 # GCN-LABEL: name: v_clamp_omod_already_set_f32
# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
# GCN: %21:vgpr_32 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit $exec # GCN: %21:vgpr_32 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit $exec
name: v_clamp_omod_already_set_f32 name: v_clamp_omod_already_set_f32
Show All 30 Linesliveins:
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
- { reg: '$vgpr0', virtual-reg: '%3' } - { reg: '$vgpr0', virtual-reg: '%3' }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%24 = V_ASHRREV_I32_e32 31, %3, implicit $exec %24 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%25 = REG_SEQUENCE %3, 1, %24, 2 %25 = REG_SEQUENCE %3, 1, %24, 2
%10 = S_MOV_B32 61440 %10 = S_MOV_B32 61440
%11 = S_MOV_B32 0 %11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18 %13 = REG_SEQUENCE killed %5, 17, %12, 18
%14 = S_MOV_B32 2 %14 = S_MOV_B32 2
%26 = V_LSHL_B64 killed %25, 2, implicit $exec %26 = V_LSHL_B64 killed %25, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18 %16 = REG_SEQUENCE killed %4, 17, %12, 18
%18 = COPY %26 %18 = COPY %26
%17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit $exec %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, implicit $exec
%20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
%21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit $exec %21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit $exec
BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Don't fold a mul that looks like an omod if itself has omod set # Don't fold a mul that looks like an omod if itself has omod set
# GCN-LABEL: name: v_omod_mul_omod_already_set_f32 # GCN-LABEL: name: v_omod_mul_omod_already_set_f32
# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
# GCN-NEXT: %21:vgpr_32 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 0, 3, implicit $exec # GCN-NEXT: %21:vgpr_32 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 0, 3, implicit $exec
Show All 31 Linesliveins:
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
- { reg: '$vgpr0', virtual-reg: '%3' } - { reg: '$vgpr0', virtual-reg: '%3' }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%24 = V_ASHRREV_I32_e32 31, %3, implicit $exec %24 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%25 = REG_SEQUENCE %3, 1, %24, 2 %25 = REG_SEQUENCE %3, 1, %24, 2
%10 = S_MOV_B32 61440 %10 = S_MOV_B32 61440
%11 = S_MOV_B32 0 %11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18 %13 = REG_SEQUENCE killed %5, 17, %12, 18
%14 = S_MOV_B32 2 %14 = S_MOV_B32 2
%26 = V_LSHL_B64 killed %25, 2, implicit $exec %26 = V_LSHL_B64 killed %25, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18 %16 = REG_SEQUENCE killed %4, 17, %12, 18
%18 = COPY %26 %18 = COPY %26
%17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit $exec %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, implicit $exec
%20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
%21 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 0, 3, implicit $exec %21 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 0, 3, implicit $exec
BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Don't fold a mul that looks like an omod if itself has clamp set # Don't fold a mul that looks like an omod if itself has clamp set
# This might be OK, but would require folding the clamp at the same time. # This might be OK, but would require folding the clamp at the same time.
# GCN-LABEL: name: v_omod_mul_clamp_already_set_f32 # GCN-LABEL: name: v_omod_mul_clamp_already_set_f32
# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
Show All 33 Linesliveins:
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
- { reg: '$vgpr0', virtual-reg: '%3' } - { reg: '$vgpr0', virtual-reg: '%3' }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%24 = V_ASHRREV_I32_e32 31, %3, implicit $exec %24 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%25 = REG_SEQUENCE %3, 1, %24, 2 %25 = REG_SEQUENCE %3, 1, %24, 2
%10 = S_MOV_B32 61440 %10 = S_MOV_B32 61440
%11 = S_MOV_B32 0 %11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18 %13 = REG_SEQUENCE killed %5, 17, %12, 18
%14 = S_MOV_B32 2 %14 = S_MOV_B32 2
%26 = V_LSHL_B64 killed %25, 2, implicit $exec %26 = V_LSHL_B64 killed %25, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18 %16 = REG_SEQUENCE killed %4, 17, %12, 18
%18 = COPY %26 %18 = COPY %26
%17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit $exec %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, implicit $exec
%20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
%21 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 1, 0, implicit $exec %21 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 1, 0, implicit $exec
BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Linesliveins:
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
- { reg: '$vgpr0', virtual-reg: '%3' } - { reg: '$vgpr0', virtual-reg: '%3' }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%24 = V_ASHRREV_I32_e32 31, %3, implicit $exec %24 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%25 = REG_SEQUENCE %3, 1, %24, 2 %25 = REG_SEQUENCE %3, 1, %24, 2
%10 = S_MOV_B32 61440 %10 = S_MOV_B32 61440
%11 = S_MOV_B32 0 %11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18 %13 = REG_SEQUENCE killed %5, 17, %12, 18
%14 = S_MOV_B32 2 %14 = S_MOV_B32 2
%26 = V_LSHL_B64 killed %25, 2, implicit $exec %26 = V_LSHL_B64 killed %25, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18 %16 = REG_SEQUENCE killed %4, 17, %12, 18
%18 = COPY %26 %18 = COPY %26
%17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit $exec %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, implicit $exec
%20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
%21 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 0, 3, implicit $exec %21 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 0, 3, implicit $exec
BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Don't fold a mul that looks like an omod if itself has clamp set # Don't fold a mul that looks like an omod if itself has clamp set
# This might be OK, but would require folding the clamp at the same time. # This might be OK, but would require folding the clamp at the same time.
# GCN-LABEL: name: v_omod_add_clamp_already_set_f32 # GCN-LABEL: name: v_omod_add_clamp_already_set_f32
# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
Show All 33 Linesliveins:
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
- { reg: '$vgpr0', virtual-reg: '%3' } - { reg: '$vgpr0', virtual-reg: '%3' }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%24 = V_ASHRREV_I32_e32 31, %3, implicit $exec %24 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%25 = REG_SEQUENCE %3, 1, %24, 2 %25 = REG_SEQUENCE %3, 1, %24, 2
%10 = S_MOV_B32 61440 %10 = S_MOV_B32 61440
%11 = S_MOV_B32 0 %11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18 %13 = REG_SEQUENCE killed %5, 17, %12, 18
%14 = S_MOV_B32 2 %14 = S_MOV_B32 2
%26 = V_LSHL_B64 killed %25, 2, implicit $exec %26 = V_LSHL_B64 killed %25, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18 %16 = REG_SEQUENCE killed %4, 17, %12, 18
%18 = COPY %26 %18 = COPY %26
%17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit $exec %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, implicit $exec
%20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
%21 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 1, 0, implicit $exec %21 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 1, 0, implicit $exec
BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Pass used to crash with immediate second operand of max # Pass used to crash with immediate second operand of max
name: v_max_reg_imm_f32 name: v_max_reg_imm_f32
tracksRegLiveness: true tracksRegLiveness: true
Show All 11 Lines

llvm/trunk/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir

Show All 11 Lines
liveins: liveins:
- { reg: '$vgpr0' } - { reg: '$vgpr0' }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
$vgpr0_vgpr1 = IMPLICIT_DEF $vgpr0_vgpr1 = IMPLICIT_DEF
$vgpr4_vgpr5 = IMPLICIT_DEF $vgpr4_vgpr5 = IMPLICIT_DEF
$vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) $vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
$vgpr4 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) $vgpr4 = FLAT_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
$vgpr2 = IMPLICIT_DEF $vgpr2 = IMPLICIT_DEF
$vgpr3 = IMPLICIT_DEF $vgpr3 = IMPLICIT_DEF
$vgpr6 = IMPLICIT_DEF $vgpr6 = IMPLICIT_DEF
$vgpr0 = V_ADD_I32_e32 16, $vgpr2, implicit-def $vcc, implicit $exec $vgpr0 = V_ADD_I32_e32 16, $vgpr2, implicit-def $vcc, implicit $exec
$vgpr1 = V_ADDC_U32_e32 $vgpr3, killed $vgpr6, implicit-def dead $vcc, implicit $vcc, implicit $exec $vgpr1 = V_ADDC_U32_e32 $vgpr3, killed $vgpr6, implicit-def dead $vcc, implicit $vcc, implicit $exec
FLAT_STORE_DWORD $vgpr2_vgpr3, killed $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) FLAT_STORE_DWORD $vgpr2_vgpr3, killed $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
FLAT_STORE_DWORD $vgpr0_vgpr1, killed $vgpr4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) FLAT_STORE_DWORD $vgpr0_vgpr1, killed $vgpr4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/cluster-flat-loads.mir

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass machine-scheduler %s -o - | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass machine-scheduler %s -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: cluster_flat_loads # GCN-LABEL: name: cluster_flat_loads
# GCN: FLAT_LOAD_DWORD %0, 0 # GCN: FLAT_LOAD_DWORD %0, 0
# GCN-NEXT: FLAT_LOAD_DWORD %0, 4 # GCN-NEXT: FLAT_LOAD_DWORD %0, 4
# GCN-NEXT: V_ADD_F32_e64 # GCN-NEXT: V_ADD_F32_e64
name: cluster_flat_loads name: cluster_flat_loads
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_64 } - { id: 0, class: vreg_64 }
- { id: 1, class: vgpr_32 } - { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 } - { id: 2, class: vgpr_32 }
- { id: 3, class: vgpr_32 } - { id: 3, class: vgpr_32 }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
%2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec
%3 = FLAT_LOAD_DWORD %0, 4, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %3 = FLAT_LOAD_DWORD %0, 4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
... ...

llvm/trunk/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir

Show All 24 Lines bb.0:
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.1: bb.1:
%11:vgpr_32 = V_OR_B32_e32 %12.sub0, %12.sub1, implicit $exec %11:vgpr_32 = V_OR_B32_e32 %12.sub0, %12.sub1, implicit $exec
%13:vgpr_32 = V_OR_B32_e32 %11, %12.sub2, implicit $exec %13:vgpr_32 = V_OR_B32_e32 %11, %12.sub2, implicit $exec
%14:vgpr_32 = V_AND_B32_e32 1, %13, implicit $exec %14:vgpr_32 = V_AND_B32_e32 1, %13, implicit $exec
%15:sreg_64_xexec = V_CMP_EQ_U32_e64 0, %14, implicit $exec %15:sreg_64_xexec = V_CMP_EQ_U32_e64 0, %14, implicit $exec
%16:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %15, implicit $exec %16:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %15, implicit $exec
BUFFER_STORE_DWORD_OFFEN_exact %16, undef %17:vgpr_32, undef %18:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into constant-pool, align 1, addrspace 4) BUFFER_STORE_DWORD_OFFEN_exact %16, undef %17:vgpr_32, undef %18:sreg_128, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into constant-pool, align 1, addrspace 4)
S_ENDPGM 0 S_ENDPGM 0
bb.2: bb.2:
successors: %bb.3, %bb.4 successors: %bb.3, %bb.4
%19:sreg_64 = V_CMP_EQ_U32_e64 1, %7, implicit $exec %19:sreg_64 = V_CMP_EQ_U32_e64 1, %7, implicit $exec
%20:sreg_64 = COPY $exec, implicit-def $exec %20:sreg_64 = COPY $exec, implicit-def $exec
%21:sreg_64 = S_AND_B64 %20, %19, implicit-def dead $scc %21:sreg_64 = S_AND_B64 %20, %19, implicit-def dead $scc
$exec = S_MOV_B64_term %21 $exec = S_MOV_B64_term %21
Show All 31 Lines bb.7:
%29:sreg_64 = COPY $exec, implicit-def $exec %29:sreg_64 = COPY $exec, implicit-def $exec
%30:sreg_64 = S_AND_B64 %29, %26, implicit-def dead $scc %30:sreg_64 = S_AND_B64 %29, %26, implicit-def dead $scc
$exec = S_MOV_B64_term %30 $exec = S_MOV_B64_term %30
SI_MASK_BRANCH %bb.10, implicit $exec SI_MASK_BRANCH %bb.10, implicit $exec
S_BRANCH %bb.8 S_BRANCH %bb.8
bb.8: bb.8:
successors: %bb.10 successors: %bb.10
%31:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %32:vgpr_32, undef %33:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4) %31:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %32:vgpr_32, undef %33:sreg_128, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
%34:sreg_64_xexec = V_CMP_NE_U32_e64 0, %31, implicit $exec %34:sreg_64_xexec = V_CMP_NE_U32_e64 0, %31, implicit $exec
%35:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, %34, implicit $exec %35:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, %34, implicit $exec
%28:vreg_1 = COPY %35 %28:vreg_1 = COPY %35
S_BRANCH %bb.10 S_BRANCH %bb.10
bb.9: bb.9:
successors: %bb.11 successors: %bb.11
S_BRANCH %bb.11 S_BRANCH %bb.11
Show All 27 Lines

llvm/trunk/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Linesbody: |
bb.8: bb.8:
successors: %bb.9(0x40000000), %bb.11(0x40000000) successors: %bb.9(0x40000000), %bb.11(0x40000000)
%18:vgpr_32 = V_MUL_LO_I32 %15.sub1, target-flags(amdgpu-gotprel32-lo) 7, implicit $exec %18:vgpr_32 = V_MUL_LO_I32 %15.sub1, target-flags(amdgpu-gotprel32-lo) 7, implicit $exec
S_CBRANCH_SCC1 %bb.11, implicit undef $scc S_CBRANCH_SCC1 %bb.11, implicit undef $scc
S_BRANCH %bb.9 S_BRANCH %bb.9
bb.9: bb.9:
successors: %bb.10(0x80000000) successors: %bb.10(0x80000000)
%19:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %18, undef %20:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4) %19:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %18, undef %20:sreg_128, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
%21:sreg_64 = V_CMP_NE_U32_e64 target-flags(amdgpu-gotprel) 0, killed %19.sub0, implicit $exec %21:sreg_64 = V_CMP_NE_U32_e64 target-flags(amdgpu-gotprel) 0, killed %19.sub0, implicit $exec
%22:sreg_64 = COPY $exec, implicit-def $exec %22:sreg_64 = COPY $exec, implicit-def $exec
%23:sreg_64 = S_AND_B64 %22, %21, implicit-def dead $scc %23:sreg_64 = S_AND_B64 %22, %21, implicit-def dead $scc
$exec = S_MOV_B64_term killed %23 $exec = S_MOV_B64_term killed %23
bb.10: bb.10:
successors: %bb.12(0x80000000) successors: %bb.12(0x80000000)
$exec = S_OR_B64 $exec, killed %22, implicit-def $scc $exec = S_OR_B64 $exec, killed %22, implicit-def $scc
Show All 39 Lines

llvm/trunk/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Linesbody: |
bb.4: bb.4:
successors: %bb.8(0x40000000), %bb.9(0x40000000) successors: %bb.8(0x40000000), %bb.9(0x40000000)
%21:vreg_128 = COPY killed %19 %21:vreg_128 = COPY killed %19
%22:vgpr_32 = COPY killed %18 %22:vgpr_32 = COPY killed %18
%23:vreg_128 = COPY killed %17 %23:vreg_128 = COPY killed %17
%24:sreg_64 = COPY killed %16 %24:sreg_64 = COPY killed %16
%25:vgpr_32 = V_OR_B32_e32 %22, %11, implicit $exec %25:vgpr_32 = V_OR_B32_e32 %22, %11, implicit $exec
%26:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %25, undef %27:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4) %26:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %25, undef %27:sreg_128, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
%28:vgpr_32 = V_LSHRREV_B32_e32 30, killed %26.sub0, implicit $exec %28:vgpr_32 = V_LSHRREV_B32_e32 30, killed %26.sub0, implicit $exec
%29:vreg_128 = COPY killed %21 %29:vreg_128 = COPY killed %21
%29.sub0:vreg_128 = COPY %1 %29.sub0:vreg_128 = COPY %1
%30:sreg_64 = V_CMP_NE_U32_e64 0, %28, implicit $exec %30:sreg_64 = V_CMP_NE_U32_e64 0, %28, implicit $exec
%31:sreg_64_xexec = V_CMP_EQ_U32_e64 0, %28, implicit $exec %31:sreg_64_xexec = V_CMP_EQ_U32_e64 0, %28, implicit $exec
dead %32:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed %31, implicit $exec dead %32:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed %31, implicit $exec
%33:vreg_128 = COPY %29 %33:vreg_128 = COPY %29
%33.sub1:vreg_128 = COPY undef %32 %33.sub1:vreg_128 = COPY undef %32
▲ Show 20 Lines • Show All 189 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/coalescer-subreg-join.mir

Show All 40 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr2_sgpr3, $vgpr2, $vgpr3 liveins: $sgpr2_sgpr3, $vgpr2, $vgpr3
%0 = COPY $sgpr2_sgpr3 %0 = COPY $sgpr2_sgpr3
%1 = COPY $vgpr2 %1 = COPY $vgpr2
%2 = COPY $vgpr3 %2 = COPY $vgpr3
%3 = S_LOAD_DWORDX8_IMM %0, 0, 0 %3 = S_LOAD_DWORDX8_IMM %0, 0, 0, 0
%4 = S_LOAD_DWORDX4_IMM %0, 12, 0 %4 = S_LOAD_DWORDX4_IMM %0, 12, 0, 0
%5 = S_LOAD_DWORDX8_IMM %0, 16, 0 %5 = S_LOAD_DWORDX8_IMM %0, 16, 0, 0
%6 = S_LOAD_DWORDX4_IMM %0, 28, 0 %6 = S_LOAD_DWORDX4_IMM %0, 28, 0, 0
undef %7.sub0 = S_MOV_B32 212739 undef %7.sub0 = S_MOV_B32 212739
%20 = COPY %7 %20 = COPY %7
%11 = COPY %20 %11 = COPY %20
%11.sub1 = COPY %1 %11.sub1 = COPY %1
%11.sub2 = COPY %1 %11.sub2 = COPY %1
%11.sub3 = COPY %1 %11.sub3 = COPY %1
%11.sub4 = COPY %1 %11.sub4 = COPY %1
%11.sub5 = COPY %1 %11.sub5 = COPY %1
Show All 15 Lines

llvm/trunk/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir

# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s # RUN: llc -march=amdgcn -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
# #
# See bug http://llvm.org/PR33152 for details of the bug this test is checking # See bug http://llvm.org/PR33152 for details of the bug this test is checking
# for. # for.
# This test will provoke a subrange join during simple register # This test will provoke a subrange join during simple register
# coalescing. Withough a fix for PR33152 this causes an unreachable in SubRange # coalescing. Withough a fix for PR33152 this causes an unreachable in SubRange
# Join # Join
# #
# The lines where the problem exhibits are the last 2 copy instructions in the # The lines where the problem exhibits are the last 2 copy instructions in the
# BB (bb.25) # BB (bb.25)
# #
# GCN-LABEL: bb.6: # GCN-LABEL: bb.6:
# GCN: successors: %bb.7(0x{{[0-9]+}}), %bb.18(0x{{[0-9]+}}) # GCN: successors: %bb.7(0x{{[0-9]+}}), %bb.18(0x{{[0-9]+}})
# GCN: %{{[0-9]+}}:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %{{[0-9]+}}, 0, 0, 0, 0, 0, implicit $exec # GCN: %{{[0-9]+}}:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %{{[0-9]+}}, 0, 0, 0, 0, 0, 0, implicit $exec
# #
--- | --- |
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5" target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
target triple = "amdgcn--amdpal" target triple = "amdgcn--amdpal"
define amdgpu_ps void @main() #0 { define amdgpu_ps void @main() #0 {
ret void ret void
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines bb.5:
S_BRANCH %bb.9 S_BRANCH %bb.9
bb.6: bb.6:
successors: %bb.7(0x40000000), %bb.18(0x40000000) successors: %bb.7(0x40000000), %bb.18(0x40000000)
%9:vreg_128 = COPY killed %6 %9:vreg_128 = COPY killed %6
%10:sreg_64 = COPY killed %5 %10:sreg_64 = COPY killed %5
undef %11.sub2:sreg_128 = COPY %4 undef %11.sub2:sreg_128 = COPY %4
%11.sub3:sreg_128 = COPY %3 %11.sub3:sreg_128 = COPY %3
%12:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET killed %11, 0, 0, 0, 0, 0, implicit $exec %12:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET killed %11, 0, 0, 0, 0, 0, 0, implicit $exec
undef %13.sub1:vreg_128 = COPY %9.sub1 undef %13.sub1:vreg_128 = COPY %9.sub1
%13.sub2:vreg_128 = COPY %9.sub2 %13.sub2:vreg_128 = COPY %9.sub2
%14:sreg_64 = V_CMP_GT_F32_e64 0, target-flags(amdgpu-rel32-lo) 0, 0, killed %12.sub3, 0, implicit $exec %14:sreg_64 = V_CMP_GT_F32_e64 0, target-flags(amdgpu-rel32-lo) 0, 0, killed %12.sub3, 0, implicit $exec
%15:vgpr_32 = V_ADD_F32_e32 1065353216, undef %16:vgpr_32, implicit $exec %15:vgpr_32 = V_ADD_F32_e32 1065353216, undef %16:vgpr_32, implicit $exec
%17:sreg_64 = V_CMP_GT_F32_e64 0, 0, 0, killed %15, 0, implicit $exec %17:sreg_64 = V_CMP_GT_F32_e64 0, 0, 0, killed %15, 0, implicit $exec
%18:sreg_64 = S_AND_B64 killed %17, killed %14, implicit-def dead $scc %18:sreg_64 = S_AND_B64 killed %17, killed %14, implicit-def dead $scc
%19:sreg_64 = COPY %10 %19:sreg_64 = COPY %10
%20:vreg_128 = COPY %13 %20:vreg_128 = COPY %13
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines bb.17:
%54:vreg_128 = COPY killed %38 %54:vreg_128 = COPY killed %38
%55:vgpr_32 = V_FMA_F32 0, killed %54.sub1, 0, target-flags(amdgpu-gotprel32-lo) 1056964608, 0, 1056964608, 0, 0, implicit $exec %55:vgpr_32 = V_FMA_F32 0, killed %54.sub1, 0, target-flags(amdgpu-gotprel32-lo) 1056964608, 0, 1056964608, 0, 0, implicit $exec
EXP 1, undef %56:vgpr_32, killed %55, undef %57:vgpr_32, undef %58:vgpr_32, -1, 0, 15, implicit $exec EXP 1, undef %56:vgpr_32, killed %55, undef %57:vgpr_32, undef %58:vgpr_32, -1, 0, 15, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
bb.18: bb.18:
successors: %bb.7(0x80000000) successors: %bb.7(0x80000000)
dead %59:vgpr_32 = V_FMA_F32 0, killed %9.sub2, 0, undef %60:vgpr_32, 0, undef %61:vgpr_32, 0, 0, implicit $exec dead %59:vgpr_32 = V_FMA_F32 0, killed %9.sub2, 0, undef %60:vgpr_32, 0, undef %61:vgpr_32, 0, 0, implicit $exec
dead %62:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %63:vgpr_32, undef %64:sreg_128, undef %65:sreg_32, 0, 0, 0, 0, implicit $exec dead %62:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %63:vgpr_32, undef %64:sreg_128, undef %65:sreg_32, 0, 0, 0, 0, 0, implicit $exec
undef %66.sub1:vreg_128 = COPY %13.sub1 undef %66.sub1:vreg_128 = COPY %13.sub1
%66.sub2:vreg_128 = COPY %13.sub2 %66.sub2:vreg_128 = COPY %13.sub2
%67:sreg_64 = V_CMP_NGT_F32_e64 0, 0, 0, undef %68:vgpr_32, 0, implicit $exec %67:sreg_64 = V_CMP_NGT_F32_e64 0, 0, 0, undef %68:vgpr_32, 0, implicit $exec
%69:vgpr_32 = V_ADD_F32_e32 1065353216, undef %70:vgpr_32, implicit $exec %69:vgpr_32 = V_ADD_F32_e32 1065353216, undef %70:vgpr_32, implicit $exec
%71:vgpr_32 = V_ADD_F32_e32 1065353216, killed %69, implicit $exec %71:vgpr_32 = V_ADD_F32_e32 1065353216, killed %69, implicit $exec
%72:sreg_64 = V_CMP_NGT_F32_e64 0, 0, 0, killed %71, 0, implicit $exec %72:sreg_64 = V_CMP_NGT_F32_e64 0, 0, 0, killed %71, 0, implicit $exec
%73:sreg_64 = S_OR_B64 killed %72, killed %67, implicit-def dead $scc %73:sreg_64 = S_OR_B64 killed %72, killed %67, implicit-def dead $scc
%74:sreg_64 = S_OR_B64 killed %73, killed %10, implicit-def dead $scc %74:sreg_64 = S_OR_B64 killed %73, killed %10, implicit-def dead $scc
%19:sreg_64 = COPY killed %74 %19:sreg_64 = COPY killed %74
%20:vreg_128 = COPY %66 %20:vreg_128 = COPY %66
%21:vreg_128 = COPY killed %66 %21:vreg_128 = COPY killed %66
S_BRANCH %bb.7 S_BRANCH %bb.7
... ...

llvm/trunk/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir

Show First 20 Lines • Show All 139 Lines • ▼ Show 20 Linesbody: |
bb.14: bb.14:
successors: %bb.15(0x40000000), %bb.16(0x40000000) successors: %bb.15(0x40000000), %bb.16(0x40000000)
%38:vgpr_32 = V_MAD_F32 0, killed %36.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $exec %38:vgpr_32 = V_MAD_F32 0, killed %36.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $exec
%39:vgpr_32 = V_MAD_F32 0, killed %38, 0, 0, 0, 0, 0, 0, implicit $exec %39:vgpr_32 = V_MAD_F32 0, killed %38, 0, 0, 0, 0, 0, 0, implicit $exec
%40:vgpr_32 = V_MAD_F32 0, killed %39, 0, -1090519040, 0, 1056964608, 0, 0, implicit $exec %40:vgpr_32 = V_MAD_F32 0, killed %39, 0, -1090519040, 0, 1056964608, 0, 0, implicit $exec
%41:vgpr_32 = V_MAD_F32 0, killed %40, 0, 0, 0, -1090519040, 0, 0, implicit $exec %41:vgpr_32 = V_MAD_F32 0, killed %40, 0, 0, 0, -1090519040, 0, 0, implicit $exec
%42:vgpr_32 = V_CVT_I32_F32_e32 killed %41, implicit $exec %42:vgpr_32 = V_CVT_I32_F32_e32 killed %41, implicit $exec
%43:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %44:sreg_128, 12, 0 :: (dereferenceable invariant load 4) %43:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %44:sreg_128, 12, 0, 0 :: (dereferenceable invariant load 4)
%45:vgpr_32 = V_MUL_LO_I32 killed %42, killed %43, implicit $exec %45:vgpr_32 = V_MUL_LO_I32 killed %42, killed %43, implicit $exec
%46:vgpr_32 = V_LSHLREV_B32_e32 2, killed %45, implicit $exec %46:vgpr_32 = V_LSHLREV_B32_e32 2, killed %45, implicit $exec
%47:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN killed %46, undef %48:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4) %47:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN killed %46, undef %48:sreg_128, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
%49:sreg_64 = V_CMP_NE_U32_e64 0, killed %47, implicit $exec %49:sreg_64 = V_CMP_NE_U32_e64 0, killed %47, implicit $exec
%50:sreg_64 = COPY $exec, implicit-def $exec %50:sreg_64 = COPY $exec, implicit-def $exec
%51:sreg_64 = S_AND_B64 %50, %49, implicit-def dead $scc %51:sreg_64 = S_AND_B64 %50, %49, implicit-def dead $scc
$exec = S_MOV_B64_term killed %51 $exec = S_MOV_B64_term killed %51
SI_MASK_BRANCH %bb.16, implicit $exec SI_MASK_BRANCH %bb.16, implicit $exec
S_BRANCH %bb.15 S_BRANCH %bb.15
bb.15: bb.15:
Show All 25 Lines

llvm/trunk/test/CodeGen/AMDGPU/collapse-endcf.mir

Show All 19 Linesbody: |
; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec ; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN: SI_MASK_BRANCH %bb.4, implicit $exec ; GCN: SI_MASK_BRANCH %bb.4, implicit $exec
; GCN: S_BRANCH %bb.1 ; GCN: S_BRANCH %bb.1
; GCN: bb.1: ; GCN: bb.1:
; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) ; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec ; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec
; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec ; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1 ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1
; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec ; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec ; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec
; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440 ; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440
; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0 ; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0
; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec ; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec
; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN: SI_MASK_BRANCH %bb.3, implicit $exec ; GCN: SI_MASK_BRANCH %bb.3, implicit $exec
; GCN: S_BRANCH %bb.2 ; GCN: S_BRANCH %bb.2
; GCN: bb.2: ; GCN: bb.2:
; GCN: successors: %bb.3(0x80000000) ; GCN: successors: %bb.3(0x80000000)
; GCN: %5.sub0:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub0:sgpr_128 = COPY %5.sub2
; GCN: %5.sub1:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub1:sgpr_128 = COPY %5.sub2
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: bb.3: ; GCN: bb.3:
; GCN: successors: %bb.4(0x80000000) ; GCN: successors: %bb.4(0x80000000)
; GCN: DBG_VALUE ; GCN: DBG_VALUE
; GCN: bb.4: ; GCN: bb.4:
; GCN: DBG_VALUE ; GCN: DBG_VALUE
; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
Show All 11 Lines bb.0:
%4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc %4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc
$exec = S_MOV_B64_term %4 $exec = S_MOV_B64_term %4
SI_MASK_BRANCH %bb.4, implicit $exec SI_MASK_BRANCH %bb.4, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
successors: %bb.2, %bb.3 successors: %bb.2, %bb.3
undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec
%6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
%7:vgpr_32 = COPY %5.sub1 %7:vgpr_32 = COPY %5.sub1
undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
%8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec
%5.sub3:sgpr_128 = S_MOV_B32 61440 %5.sub3:sgpr_128 = S_MOV_B32 61440
%5.sub2:sgpr_128 = S_MOV_B32 0 %5.sub2:sgpr_128 = S_MOV_B32 0
BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
%11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec %11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec
%12:sreg_64 = COPY $exec, implicit-def $exec %12:sreg_64 = COPY $exec, implicit-def $exec
%13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc %13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc
$exec = S_MOV_B64_term %13 $exec = S_MOV_B64_term %13
SI_MASK_BRANCH %bb.3, implicit $exec SI_MASK_BRANCH %bb.3, implicit $exec
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.2: bb.2:
%5.sub0:sgpr_128 = COPY %5.sub2 %5.sub0:sgpr_128 = COPY %5.sub2
%5.sub1:sgpr_128 = COPY %5.sub2 %5.sub1:sgpr_128 = COPY %5.sub2
%14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec %14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
bb.3: bb.3:
$exec = S_OR_B64 $exec, %12, implicit-def $scc $exec = S_OR_B64 $exec, %12, implicit-def $scc
DBG_VALUE DBG_VALUE
bb.4: bb.4:
DBG_VALUE DBG_VALUE
$exec = S_OR_B64 $exec, %3, implicit-def $scc $exec = S_OR_B64 $exec, %3, implicit-def $scc
Show All 24 Linesbody: |
; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec ; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN: SI_MASK_BRANCH %bb.5, implicit $exec ; GCN: SI_MASK_BRANCH %bb.5, implicit $exec
; GCN: S_BRANCH %bb.1 ; GCN: S_BRANCH %bb.1
; GCN: bb.1: ; GCN: bb.1:
; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) ; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec ; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec
; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec ; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1 ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1
; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec ; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec ; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec
; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440 ; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440
; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0 ; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0
; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec ; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec
; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN: SI_MASK_BRANCH %bb.3, implicit $exec ; GCN: SI_MASK_BRANCH %bb.3, implicit $exec
; GCN: S_BRANCH %bb.2 ; GCN: S_BRANCH %bb.2
; GCN: bb.2: ; GCN: bb.2:
; GCN: successors: %bb.3(0x80000000) ; GCN: successors: %bb.3(0x80000000)
; GCN: %5.sub0:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub0:sgpr_128 = COPY %5.sub2
; GCN: %5.sub1:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub1:sgpr_128 = COPY %5.sub2
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: bb.3: ; GCN: bb.3:
; GCN: successors: %bb.4(0x80000000) ; GCN: successors: %bb.4(0x80000000)
; GCN: bb.4: ; GCN: bb.4:
; GCN: successors: %bb.5(0x80000000) ; GCN: successors: %bb.5(0x80000000)
; GCN: bb.5: ; GCN: bb.5:
; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
Show All 11 Lines bb.0:
%4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc %4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc
$exec = S_MOV_B64_term %4 $exec = S_MOV_B64_term %4
SI_MASK_BRANCH %bb.4, implicit $exec SI_MASK_BRANCH %bb.4, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
successors: %bb.2, %bb.3 successors: %bb.2, %bb.3
undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec
%6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
%7:vgpr_32 = COPY %5.sub1 %7:vgpr_32 = COPY %5.sub1
undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
%8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec
%5.sub3:sgpr_128 = S_MOV_B32 61440 %5.sub3:sgpr_128 = S_MOV_B32 61440
%5.sub2:sgpr_128 = S_MOV_B32 0 %5.sub2:sgpr_128 = S_MOV_B32 0
BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
%11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec %11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec
%12:sreg_64 = COPY $exec, implicit-def $exec %12:sreg_64 = COPY $exec, implicit-def $exec
%13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc %13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc
$exec = S_MOV_B64_term %13 $exec = S_MOV_B64_term %13
SI_MASK_BRANCH %bb.3, implicit $exec SI_MASK_BRANCH %bb.3, implicit $exec
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.2: bb.2:
%5.sub0:sgpr_128 = COPY %5.sub2 %5.sub0:sgpr_128 = COPY %5.sub2
%5.sub1:sgpr_128 = COPY %5.sub2 %5.sub1:sgpr_128 = COPY %5.sub2
%14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec %14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
bb.3: bb.3:
$exec = S_OR_B64 $exec, %12, implicit-def $scc $exec = S_OR_B64 $exec, %12, implicit-def $scc
bb.5: bb.5:
bb.4: bb.4:
$exec = S_OR_B64 $exec, %3, implicit-def $scc $exec = S_OR_B64 $exec, %3, implicit-def $scc
Show All 24 Linesbody: |
; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec ; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN: SI_MASK_BRANCH %bb.5, implicit $exec ; GCN: SI_MASK_BRANCH %bb.5, implicit $exec
; GCN: S_BRANCH %bb.1 ; GCN: S_BRANCH %bb.1
; GCN: bb.1: ; GCN: bb.1:
; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) ; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec ; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec
; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec ; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1 ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1
; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec ; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec ; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec
; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440 ; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440
; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0 ; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0
; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec ; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec
; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN: SI_MASK_BRANCH %bb.3, implicit $exec ; GCN: SI_MASK_BRANCH %bb.3, implicit $exec
; GCN: S_BRANCH %bb.2 ; GCN: S_BRANCH %bb.2
; GCN: bb.2: ; GCN: bb.2:
; GCN: successors: %bb.3(0x80000000) ; GCN: successors: %bb.3(0x80000000)
; GCN: %5.sub0:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub0:sgpr_128 = COPY %5.sub2
; GCN: %5.sub1:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub1:sgpr_128 = COPY %5.sub2
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: bb.3: ; GCN: bb.3:
; GCN: successors: %bb.4(0x80000000) ; GCN: successors: %bb.4(0x80000000)
; GCN: bb.4: ; GCN: bb.4:
; GCN: successors: %bb.5(0x80000000) ; GCN: successors: %bb.5(0x80000000)
; GCN: DBG_VALUE ; GCN: DBG_VALUE
; GCN: bb.5: ; GCN: bb.5:
; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
Show All 12 Lines bb.0:
%4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc %4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc
$exec = S_MOV_B64_term %4 $exec = S_MOV_B64_term %4
SI_MASK_BRANCH %bb.4, implicit $exec SI_MASK_BRANCH %bb.4, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
successors: %bb.2, %bb.3 successors: %bb.2, %bb.3
undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec
%6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
%7:vgpr_32 = COPY %5.sub1 %7:vgpr_32 = COPY %5.sub1
undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
%8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec
%5.sub3:sgpr_128 = S_MOV_B32 61440 %5.sub3:sgpr_128 = S_MOV_B32 61440
%5.sub2:sgpr_128 = S_MOV_B32 0 %5.sub2:sgpr_128 = S_MOV_B32 0
BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
%11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec %11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec
%12:sreg_64 = COPY $exec, implicit-def $exec %12:sreg_64 = COPY $exec, implicit-def $exec
%13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc %13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc
$exec = S_MOV_B64_term %13 $exec = S_MOV_B64_term %13
SI_MASK_BRANCH %bb.3, implicit $exec SI_MASK_BRANCH %bb.3, implicit $exec
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.2: bb.2:
%5.sub0:sgpr_128 = COPY %5.sub2 %5.sub0:sgpr_128 = COPY %5.sub2
%5.sub1:sgpr_128 = COPY %5.sub2 %5.sub1:sgpr_128 = COPY %5.sub2
%14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec %14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
bb.3: bb.3:
$exec = S_OR_B64 $exec, %12, implicit-def $scc $exec = S_OR_B64 $exec, %12, implicit-def $scc
bb.5: bb.5:
DBG_VALUE DBG_VALUE
bb.4: bb.4:
Show All 24 Linesbody: |
; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec ; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN: SI_MASK_BRANCH %bb.4, implicit $exec ; GCN: SI_MASK_BRANCH %bb.4, implicit $exec
; GCN: S_BRANCH %bb.1 ; GCN: S_BRANCH %bb.1
; GCN: bb.1: ; GCN: bb.1:
; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) ; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec ; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec
; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec ; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1 ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1
; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec ; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec ; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec
; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440 ; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440
; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0 ; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0
; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec ; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec
; GCN: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN: SI_MASK_BRANCH %bb.3, implicit $exec ; GCN: SI_MASK_BRANCH %bb.3, implicit $exec
; GCN: S_BRANCH %bb.2 ; GCN: S_BRANCH %bb.2
; GCN: bb.2: ; GCN: bb.2:
; GCN: successors: %bb.3(0x80000000) ; GCN: successors: %bb.3(0x80000000)
; GCN: %5.sub0:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub0:sgpr_128 = COPY %5.sub2
; GCN: %5.sub1:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub1:sgpr_128 = COPY %5.sub2
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: bb.3: ; GCN: bb.3:
; GCN: successors: %bb.4(0x80000000) ; GCN: successors: %bb.4(0x80000000)
; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
; GCN: dead %16:sgpr_32 = S_BREV_B32 [[DEF]] ; GCN: dead %16:sgpr_32 = S_BREV_B32 [[DEF]]
; GCN: KILL [[DEF]] ; GCN: KILL [[DEF]]
; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc ; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc
; GCN: bb.4: ; GCN: bb.4:
; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
Show All 13 Lines bb.0:
%4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc %4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc
$exec = S_MOV_B64_term %4 $exec = S_MOV_B64_term %4
SI_MASK_BRANCH %bb.4, implicit $exec SI_MASK_BRANCH %bb.4, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
successors: %bb.2, %bb.3 successors: %bb.2, %bb.3
undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec
%6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
%7:vgpr_32 = COPY %5.sub1 %7:vgpr_32 = COPY %5.sub1
undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
%8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec
%5.sub3:sgpr_128 = S_MOV_B32 61440 %5.sub3:sgpr_128 = S_MOV_B32 61440
%5.sub2:sgpr_128 = S_MOV_B32 0 %5.sub2:sgpr_128 = S_MOV_B32 0
BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
%11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec %11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec
%12:sreg_64 = COPY $exec, implicit-def $exec %12:sreg_64 = COPY $exec, implicit-def $exec
%13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc %13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc
$exec = S_MOV_B64_term %13 $exec = S_MOV_B64_term %13
SI_MASK_BRANCH %bb.3, implicit $exec SI_MASK_BRANCH %bb.3, implicit $exec
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.2: bb.2:
%5.sub0:sgpr_128 = COPY %5.sub2 %5.sub0:sgpr_128 = COPY %5.sub2
%5.sub1:sgpr_128 = COPY %5.sub2 %5.sub1:sgpr_128 = COPY %5.sub2
%14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec %14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
bb.3: bb.3:
%15:sgpr_32 = IMPLICIT_DEF %15:sgpr_32 = IMPLICIT_DEF
%16:sgpr_32 = S_BREV_B32 %15 %16:sgpr_32 = S_BREV_B32 %15
KILL %15 KILL %15
$exec = S_OR_B64 $exec, %12, implicit-def $scc $exec = S_OR_B64 $exec, %12, implicit-def $scc
bb.4: bb.4:
Show All 26 Linesbody: |
; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec ; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN: SI_MASK_BRANCH %bb.4, implicit $exec ; GCN: SI_MASK_BRANCH %bb.4, implicit $exec
; GCN: S_BRANCH %bb.1 ; GCN: S_BRANCH %bb.1
; GCN: bb.1: ; GCN: bb.1:
; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) ; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec ; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec
; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec ; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1 ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1
; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec ; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec ; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec
; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440 ; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440
; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0 ; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0
; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec ; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec
; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN: SI_MASK_BRANCH %bb.3, implicit $exec ; GCN: SI_MASK_BRANCH %bb.3, implicit $exec
; GCN: S_BRANCH %bb.2 ; GCN: S_BRANCH %bb.2
; GCN: bb.2: ; GCN: bb.2:
; GCN: successors: %bb.3(0x80000000) ; GCN: successors: %bb.3(0x80000000)
; GCN: %5.sub0:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub0:sgpr_128 = COPY %5.sub2
; GCN: %5.sub1:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub1:sgpr_128 = COPY %5.sub2
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: bb.3: ; GCN: bb.3:
; GCN: successors: %bb.4(0x80000000) ; GCN: successors: %bb.4(0x80000000)
; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
; GCN: [[S_BREV_B32_:%[0-9]+]]:sgpr_32 = S_BREV_B32 [[DEF]] ; GCN: [[S_BREV_B32_:%[0-9]+]]:sgpr_32 = S_BREV_B32 [[DEF]]
; GCN: KILL [[DEF]] ; GCN: KILL [[DEF]]
; GCN: dead %17:sgpr_32 = COPY [[S_BREV_B32_]] ; GCN: dead %17:sgpr_32 = COPY [[S_BREV_B32_]]
; GCN: bb.4: ; GCN: bb.4:
; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
Show All 13 Lines bb.0:
%4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc %4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc
$exec = S_MOV_B64_term %4 $exec = S_MOV_B64_term %4
SI_MASK_BRANCH %bb.4, implicit $exec SI_MASK_BRANCH %bb.4, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
successors: %bb.2, %bb.3 successors: %bb.2, %bb.3
undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec
%6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
%7:vgpr_32 = COPY %5.sub1 %7:vgpr_32 = COPY %5.sub1
undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
%8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec
%5.sub3:sgpr_128 = S_MOV_B32 61440 %5.sub3:sgpr_128 = S_MOV_B32 61440
%5.sub2:sgpr_128 = S_MOV_B32 0 %5.sub2:sgpr_128 = S_MOV_B32 0
BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
%11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec %11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec
%12:sreg_64 = COPY $exec, implicit-def $exec %12:sreg_64 = COPY $exec, implicit-def $exec
%13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc %13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc
$exec = S_MOV_B64_term %13 $exec = S_MOV_B64_term %13
SI_MASK_BRANCH %bb.3, implicit $exec SI_MASK_BRANCH %bb.3, implicit $exec
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.2: bb.2:
%5.sub0:sgpr_128 = COPY %5.sub2 %5.sub0:sgpr_128 = COPY %5.sub2
%5.sub1:sgpr_128 = COPY %5.sub2 %5.sub1:sgpr_128 = COPY %5.sub2
%14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec %14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
bb.3: bb.3:
$exec = S_OR_B64 $exec, %12, implicit-def $scc $exec = S_OR_B64 $exec, %12, implicit-def $scc
%15:sgpr_32 = IMPLICIT_DEF %15:sgpr_32 = IMPLICIT_DEF
%16:sgpr_32 = S_BREV_B32 %15 %16:sgpr_32 = S_BREV_B32 %15
KILL %15 KILL %15
%19:sgpr_32 = COPY %16 %19:sgpr_32 = COPY %16
Show All 26 Linesbody: |
; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec ; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN: SI_MASK_BRANCH %bb.4, implicit $exec ; GCN: SI_MASK_BRANCH %bb.4, implicit $exec
; GCN: S_BRANCH %bb.1 ; GCN: S_BRANCH %bb.1
; GCN: bb.1: ; GCN: bb.1:
; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) ; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec ; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec
; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec ; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1 ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1
; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec ; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec ; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec
; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440 ; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440
; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0 ; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0
; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec ; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec
; GCN: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN: SI_MASK_BRANCH %bb.3, implicit $exec ; GCN: SI_MASK_BRANCH %bb.3, implicit $exec
; GCN: S_BRANCH %bb.2 ; GCN: S_BRANCH %bb.2
; GCN: bb.2: ; GCN: bb.2:
; GCN: successors: %bb.3(0x80000000) ; GCN: successors: %bb.3(0x80000000)
; GCN: %5.sub0:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub0:sgpr_128 = COPY %5.sub2
; GCN: %5.sub1:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub1:sgpr_128 = COPY %5.sub2
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: bb.3: ; GCN: bb.3:
; GCN: successors: %bb.4(0x80000000) ; GCN: successors: %bb.4(0x80000000)
; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc ; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc
; GCN: dead %15:sreg_64 = S_BREV_B64 $exec ; GCN: dead %15:sreg_64 = S_BREV_B64 $exec
; GCN: bb.4: ; GCN: bb.4:
; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
Show All 11 Lines bb.0:
%4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc %4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc
$exec = S_MOV_B64_term %4 $exec = S_MOV_B64_term %4
SI_MASK_BRANCH %bb.4, implicit $exec SI_MASK_BRANCH %bb.4, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
successors: %bb.2, %bb.3 successors: %bb.2, %bb.3
undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec
%6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
%7:vgpr_32 = COPY %5.sub1 %7:vgpr_32 = COPY %5.sub1
undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
%8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec
%5.sub3:sgpr_128 = S_MOV_B32 61440 %5.sub3:sgpr_128 = S_MOV_B32 61440
%5.sub2:sgpr_128 = S_MOV_B32 0 %5.sub2:sgpr_128 = S_MOV_B32 0
BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
%11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec %11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec
%12:sreg_64 = COPY $exec, implicit-def $exec %12:sreg_64 = COPY $exec, implicit-def $exec
%13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc %13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc
$exec = S_MOV_B64_term %13 $exec = S_MOV_B64_term %13
SI_MASK_BRANCH %bb.3, implicit $exec SI_MASK_BRANCH %bb.3, implicit $exec
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.2: bb.2:
%5.sub0:sgpr_128 = COPY %5.sub2 %5.sub0:sgpr_128 = COPY %5.sub2
%5.sub1:sgpr_128 = COPY %5.sub2 %5.sub1:sgpr_128 = COPY %5.sub2
%14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec %14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
bb.3: bb.3:
$exec = S_OR_B64 $exec, %12, implicit-def $scc $exec = S_OR_B64 $exec, %12, implicit-def $scc
%15:sreg_64 = S_BREV_B64 $exec %15:sreg_64 = S_BREV_B64 $exec
bb.4: bb.4:
$exec = S_OR_B64 $exec, %3, implicit-def $scc $exec = S_OR_B64 $exec, %3, implicit-def $scc
%17:vgpr_32 = V_MOV_B32_e32 3, implicit $exec %17:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
Show All 23 Linesbody: |
; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec ; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN: SI_MASK_BRANCH %bb.4, implicit $exec ; GCN: SI_MASK_BRANCH %bb.4, implicit $exec
; GCN: S_BRANCH %bb.1 ; GCN: S_BRANCH %bb.1
; GCN: bb.1: ; GCN: bb.1:
; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) ; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec ; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec
; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec ; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1 ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1
; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec ; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec ; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec
; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440 ; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440
; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0 ; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0
; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec ; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec
; GCN: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN: SI_MASK_BRANCH %bb.3, implicit $exec ; GCN: SI_MASK_BRANCH %bb.3, implicit $exec
; GCN: S_BRANCH %bb.2 ; GCN: S_BRANCH %bb.2
; GCN: bb.2: ; GCN: bb.2:
; GCN: successors: %bb.3(0x80000000) ; GCN: successors: %bb.3(0x80000000)
; GCN: %5.sub0:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub0:sgpr_128 = COPY %5.sub2
; GCN: %5.sub1:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub1:sgpr_128 = COPY %5.sub2
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: bb.3: ; GCN: bb.3:
; GCN: successors: %bb.4(0x80000000) ; GCN: successors: %bb.4(0x80000000)
; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc ; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc
; GCN: dead %15:vgpr_32 = COPY %5.sub2 ; GCN: dead %15:vgpr_32 = COPY %5.sub2
; GCN: bb.4: ; GCN: bb.4:
; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
Show All 11 Lines bb.0:
%4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc %4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc
$exec = S_MOV_B64_term %4 $exec = S_MOV_B64_term %4
SI_MASK_BRANCH %bb.4, implicit $exec SI_MASK_BRANCH %bb.4, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
successors: %bb.2, %bb.3 successors: %bb.2, %bb.3
undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec
%6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
%7:vgpr_32 = COPY %5.sub1 %7:vgpr_32 = COPY %5.sub1
undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
%8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec
%5.sub3:sgpr_128 = S_MOV_B32 61440 %5.sub3:sgpr_128 = S_MOV_B32 61440
%5.sub2:sgpr_128 = S_MOV_B32 0 %5.sub2:sgpr_128 = S_MOV_B32 0
BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
%11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec %11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec
%12:sreg_64 = COPY $exec, implicit-def $exec %12:sreg_64 = COPY $exec, implicit-def $exec
%13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc %13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc
$exec = S_MOV_B64_term %13 $exec = S_MOV_B64_term %13
SI_MASK_BRANCH %bb.3, implicit $exec SI_MASK_BRANCH %bb.3, implicit $exec
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.2: bb.2:
%5.sub0:sgpr_128 = COPY %5.sub2 %5.sub0:sgpr_128 = COPY %5.sub2
%5.sub1:sgpr_128 = COPY %5.sub2 %5.sub1:sgpr_128 = COPY %5.sub2
%14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec %14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
bb.3: bb.3:
$exec = S_OR_B64 $exec, %12, implicit-def $scc $exec = S_OR_B64 $exec, %12, implicit-def $scc
%15:vgpr_32 = COPY %5.sub2 %15:vgpr_32 = COPY %5.sub2
bb.4: bb.4:
$exec = S_OR_B64 $exec, %3, implicit-def $scc $exec = S_OR_B64 $exec, %3, implicit-def $scc
%17:vgpr_32 = V_MOV_B32_e32 3, implicit $exec %17:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
Show All 23 Linesbody: |
; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec ; GCN: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN: SI_MASK_BRANCH %bb.4, implicit $exec ; GCN: SI_MASK_BRANCH %bb.4, implicit $exec
; GCN: S_BRANCH %bb.1 ; GCN: S_BRANCH %bb.1
; GCN: bb.1: ; GCN: bb.1:
; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) ; GCN: undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec ; GCN: undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec
; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec ; GCN: %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1 ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1
; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec ; GCN: undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec ; GCN: %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec
; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440 ; GCN: %5.sub3:sgpr_128 = S_MOV_B32 61440
; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0 ; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0
; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec ; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec
; GCN: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc ; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]] ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN: SI_MASK_BRANCH %bb.3, implicit $exec ; GCN: SI_MASK_BRANCH %bb.3, implicit $exec
; GCN: S_BRANCH %bb.2 ; GCN: S_BRANCH %bb.2
; GCN: bb.2: ; GCN: bb.2:
; GCN: successors: %bb.3(0x80000000) ; GCN: successors: %bb.3(0x80000000)
; GCN: %5.sub0:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub0:sgpr_128 = COPY %5.sub2
; GCN: %5.sub1:sgpr_128 = COPY %5.sub2 ; GCN: %5.sub1:sgpr_128 = COPY %5.sub2
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; GCN: bb.3: ; GCN: bb.3:
; GCN: successors: %bb.5(0x80000000) ; GCN: successors: %bb.5(0x80000000)
; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc ; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc
; GCN: S_BRANCH %bb.5 ; GCN: S_BRANCH %bb.5
; GCN: bb.4: ; GCN: bb.4:
; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
Show All 14 Lines bb.0:
%4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc %4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc
$exec = S_MOV_B64_term %4 $exec = S_MOV_B64_term %4
SI_MASK_BRANCH %bb.4, implicit $exec SI_MASK_BRANCH %bb.4, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
successors: %bb.2, %bb.3 successors: %bb.2, %bb.3
undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4) undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec
%6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
%7:vgpr_32 = COPY %5.sub1 %7:vgpr_32 = COPY %5.sub1
undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_I32_e64 %5.sub0, %6.sub0, 0, implicit $exec
%8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec
%5.sub3:sgpr_128 = S_MOV_B32 61440 %5.sub3:sgpr_128 = S_MOV_B32 61440
%5.sub2:sgpr_128 = S_MOV_B32 0 %5.sub2:sgpr_128 = S_MOV_B32 0
BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
%11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec %11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec
%12:sreg_64 = COPY $exec, implicit-def $exec %12:sreg_64 = COPY $exec, implicit-def $exec
%13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc %13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc
$exec = S_MOV_B64_term %13 $exec = S_MOV_B64_term %13
SI_MASK_BRANCH %bb.3, implicit $exec SI_MASK_BRANCH %bb.3, implicit $exec
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.2: bb.2:
%5.sub0:sgpr_128 = COPY %5.sub2 %5.sub0:sgpr_128 = COPY %5.sub2
%5.sub1:sgpr_128 = COPY %5.sub2 %5.sub1:sgpr_128 = COPY %5.sub2
%14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec %14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
bb.3: bb.3:
$exec = S_OR_B64 $exec, %12, implicit-def $scc $exec = S_OR_B64 $exec, %12, implicit-def $scc
S_BRANCH %bb.5 S_BRANCH %bb.5
bb.4: bb.4:
$exec = S_OR_B64 $exec, %3, implicit-def $scc $exec = S_OR_B64 $exec, %3, implicit-def $scc
%15:vgpr_32 = V_MOV_B32_e32 3, implicit $exec %15:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
Show All 9 Lines

llvm/trunk/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir

Show All 38 LinesframeInfo:
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%1 = S_LOAD_DWORDX2_IMM %0, 36, 0 %1 = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
%2 = COPY %1.sub1 %2 = COPY %1.sub1
%3 = COPY %1.sub0 %3 = COPY %1.sub0
%4 = S_MOV_B32 61440 %4 = S_MOV_B32 61440
%5 = S_MOV_B32 -1 %5 = S_MOV_B32 -1
%6 = REG_SEQUENCE killed %2, 1, killed %3, 2, killed %4, 3, killed %5, 4 %6 = REG_SEQUENCE killed %2, 1, killed %3, 2, killed %4, 3, killed %5, 4
%7 = S_MOV_B32 1234567 %7 = S_MOV_B32 1234567
%8 = S_MOV_B32 9999 %8 = S_MOV_B32 9999
%9 = S_AND_B32 killed %7, killed %8, implicit-def dead $scc %9 = S_AND_B32 killed %7, killed %8, implicit-def dead $scc
%10 = COPY %9 %10 = COPY %9
BUFFER_STORE_DWORD_OFFSET killed %10, killed %6, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed %10, killed %6, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: v_fold_and_imm_regimm_32{{$}} # GCN-LABEL: name: v_fold_and_imm_regimm_32{{$}}
# GCN: %9:vgpr_32 = V_MOV_B32_e32 646, implicit $exec # GCN: %9:vgpr_32 = V_MOV_B32_e32 646, implicit $exec
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 36, 0 %4 = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
%31 = V_ASHRREV_I32_e64 31, %3, implicit $exec %31 = V_ASHRREV_I32_e64 31, %3, implicit $exec
%32 = REG_SEQUENCE %3, 1, %31, 2 %32 = REG_SEQUENCE %3, 1, %31, 2
%33 = V_LSHLREV_B64 2, killed %32, implicit $exec %33 = V_LSHLREV_B64 2, killed %32, implicit $exec
%20 = COPY %4.sub1 %20 = COPY %4.sub1
%44 = V_ADD_I32_e32 %4.sub0, %33.sub0, implicit-def $vcc, implicit $exec %44 = V_ADD_I32_e32 %4.sub0, %33.sub0, implicit-def $vcc, implicit $exec
%36 = COPY killed %20 %36 = COPY killed %20
%35 = V_ADDC_U32_e32 %33.sub1, %36, implicit-def $vcc, implicit $vcc, implicit $exec %35 = V_ADDC_U32_e32 %33.sub1, %36, implicit-def $vcc, implicit $vcc, implicit $exec
%37 = REG_SEQUENCE %44, 1, killed %35, 2 %37 = REG_SEQUENCE %44, 1, killed %35, 2
%24 = V_MOV_B32_e32 982, implicit $exec %24 = V_MOV_B32_e32 982, implicit $exec
%26 = S_MOV_B32 1234567 %26 = S_MOV_B32 1234567
%34 = V_MOV_B32_e32 63, implicit $exec %34 = V_MOV_B32_e32 63, implicit $exec
%27 = V_AND_B32_e64 %26, %24, implicit $exec %27 = V_AND_B32_e64 %26, %24, implicit $exec
FLAT_STORE_DWORD %37, %27, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %37, %27, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%28 = V_AND_B32_e64 %24, %26, implicit $exec %28 = V_AND_B32_e64 %24, %26, implicit $exec
FLAT_STORE_DWORD %37, %28, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %37, %28, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%29 = V_AND_B32_e32 %26, %24, implicit $exec %29 = V_AND_B32_e32 %26, %24, implicit $exec
FLAT_STORE_DWORD %37, %29, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %37, %29, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%30 = V_AND_B32_e64 %26, %26, implicit $exec %30 = V_AND_B32_e64 %26, %26, implicit $exec
FLAT_STORE_DWORD %37, %30, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %37, %30, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%31 = V_AND_B32_e64 %34, %34, implicit $exec %31 = V_AND_B32_e64 %34, %34, implicit $exec
FLAT_STORE_DWORD %37, %31, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %37, %31, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: s_fold_shl_imm_regimm_32{{$}} # GCN-LABEL: name: s_fold_shl_imm_regimm_32{{$}}
# GC1: %13 = V_MOV_B32_e32 4096, implicit $exec # GC1: %13 = V_MOV_B32_e32 4096, implicit $exec
Show All 37 LinesframeInfo:
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 36, 0 %4 = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
%5 = S_MOV_B32 1 %5 = S_MOV_B32 1
%6 = COPY %4.sub1 %6 = COPY %4.sub1
%7 = COPY %4.sub0 %7 = COPY %4.sub0
%8 = S_MOV_B32 61440 %8 = S_MOV_B32 61440
%9 = S_MOV_B32 -1 %9 = S_MOV_B32 -1
%10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4 %10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4
%12 = S_LSHL_B32 killed %5, 12, implicit-def dead $scc %12 = S_LSHL_B32 killed %5, 12, implicit-def dead $scc
%13 = COPY %12 %13 = COPY %12
BUFFER_STORE_DWORD_OFFSET killed %13, killed %10, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed %13, killed %10, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: v_fold_shl_imm_regimm_32{{$}} # GCN-LABEL: name: v_fold_shl_imm_regimm_32{{$}}
# GCN: %11:vgpr_32 = V_MOV_B32_e32 40955904, implicit $exec # GCN: %11:vgpr_32 = V_MOV_B32_e32 40955904, implicit $exec
# GCN: FLAT_STORE_DWORD %20, %11, # GCN: FLAT_STORE_DWORD %20, %11,
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%2 = COPY $vgpr0 %2 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%3 = S_LOAD_DWORDX2_IMM %0, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %3 = S_LOAD_DWORDX2_IMM %0, 36, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%15 = V_ASHRREV_I32_e64 31, %2, implicit $exec %15 = V_ASHRREV_I32_e64 31, %2, implicit $exec
%16 = REG_SEQUENCE %2, 1, %15, 2 %16 = REG_SEQUENCE %2, 1, %15, 2
%17 = V_LSHLREV_B64 2, killed %16, implicit $exec %17 = V_LSHLREV_B64 2, killed %16, implicit $exec
%9 = COPY %3.sub1 %9 = COPY %3.sub1
%21 = V_ADD_I32_e32 %3.sub0, %17.sub0, implicit-def $vcc, implicit $exec %21 = V_ADD_I32_e32 %3.sub0, %17.sub0, implicit-def $vcc, implicit $exec
%19 = COPY killed %9 %19 = COPY killed %9
%18 = V_ADDC_U32_e32 %17.sub1, %19, implicit-def $vcc, implicit $vcc, implicit $exec %18 = V_ADDC_U32_e32 %17.sub1, %19, implicit-def $vcc, implicit $vcc, implicit $exec
%20 = REG_SEQUENCE %21, 1, killed %18, 2 %20 = REG_SEQUENCE %21, 1, killed %18, 2
%10 = V_MOV_B32_e32 9999, implicit $exec %10 = V_MOV_B32_e32 9999, implicit $exec
%24 = V_MOV_B32_e32 3871, implicit $exec %24 = V_MOV_B32_e32 3871, implicit $exec
%6 = V_MOV_B32_e32 1, implicit $exec %6 = V_MOV_B32_e32 1, implicit $exec
%7 = S_MOV_B32 1 %7 = S_MOV_B32 1
%27 = S_MOV_B32 -4 %27 = S_MOV_B32 -4
%11 = V_LSHLREV_B32_e64 12, %10, implicit $exec %11 = V_LSHLREV_B32_e64 12, %10, implicit $exec
FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%12 = V_LSHLREV_B32_e64 %7, 12, implicit $exec %12 = V_LSHLREV_B32_e64 %7, 12, implicit $exec
FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %12, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%13 = V_LSHL_B32_e64 %7, 12, implicit $exec %13 = V_LSHL_B32_e64 %7, 12, implicit $exec
FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %13, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%14 = V_LSHL_B32_e64 12, %7, implicit $exec %14 = V_LSHL_B32_e64 12, %7, implicit $exec
FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %14, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%15 = V_LSHL_B32_e64 12, %24, implicit $exec %15 = V_LSHL_B32_e64 12, %24, implicit $exec
FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %15, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%22 = V_LSHL_B32_e64 %6, 12, implicit $exec %22 = V_LSHL_B32_e64 %6, 12, implicit $exec
FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %22, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%23 = V_LSHL_B32_e64 %6, 32, implicit $exec %23 = V_LSHL_B32_e64 %6, 32, implicit $exec
FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %23, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%25 = V_LSHL_B32_e32 %6, %6, implicit $exec %25 = V_LSHL_B32_e32 %6, %6, implicit $exec
FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %25, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%26 = V_LSHLREV_B32_e32 11, %24, implicit $exec %26 = V_LSHLREV_B32_e32 11, %24, implicit $exec
FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %26, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%28 = V_LSHL_B32_e32 %27, %6, implicit $exec %28 = V_LSHL_B32_e32 %27, %6, implicit $exec
FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %28, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: s_fold_ashr_imm_regimm_32{{$}} # GCN-LABEL: name: s_fold_ashr_imm_regimm_32{{$}}
# GCN: %11:vgpr_32 = V_MOV_B32_e32 243, implicit $exec # GCN: %11:vgpr_32 = V_MOV_B32_e32 243, implicit $exec
Show All 34 LinesframeInfo:
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 36, 0 %4 = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
%5 = S_MOV_B32 999123 %5 = S_MOV_B32 999123
%6 = COPY %4.sub1 %6 = COPY %4.sub1
%7 = COPY %4.sub0 %7 = COPY %4.sub0
%8 = S_MOV_B32 61440 %8 = S_MOV_B32 61440
%9 = S_MOV_B32 -1 %9 = S_MOV_B32 -1
%10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4 %10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4
%12 = S_ASHR_I32 killed %5, 12, implicit-def dead $scc %12 = S_ASHR_I32 killed %5, 12, implicit-def dead $scc
%13 = COPY %12 %13 = COPY %12
BUFFER_STORE_DWORD_OFFSET killed %13, killed %10, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed %13, killed %10, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN-LABEL: name: v_fold_ashr_imm_regimm_32{{$}} # GCN-LABEL: name: v_fold_ashr_imm_regimm_32{{$}}
# GCN: %11:vgpr_32 = V_MOV_B32_e32 3903258, implicit $exec # GCN: %11:vgpr_32 = V_MOV_B32_e32 3903258, implicit $exec
# GCN: FLAT_STORE_DWORD %20, %11, # GCN: FLAT_STORE_DWORD %20, %11,
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%2 = COPY $vgpr0 %2 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%3 = S_LOAD_DWORDX2_IMM %0, 36, 0 %3 = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
%15 = V_ASHRREV_I32_e64 31, %2, implicit $exec %15 = V_ASHRREV_I32_e64 31, %2, implicit $exec
%16 = REG_SEQUENCE %2, 1, %15, 2 %16 = REG_SEQUENCE %2, 1, %15, 2
%17 = V_LSHLREV_B64 2, killed %16, implicit $exec %17 = V_LSHLREV_B64 2, killed %16, implicit $exec
%9 = COPY %3.sub1 %9 = COPY %3.sub1
%21 = V_ADD_I32_e32 %3.sub0, %17.sub0, implicit-def $vcc, implicit $exec %21 = V_ADD_I32_e32 %3.sub0, %17.sub0, implicit-def $vcc, implicit $exec
%19 = COPY killed %9 %19 = COPY killed %9
%18 = V_ADDC_U32_e32 %17.sub1, %19, implicit-def $vcc, implicit $vcc, implicit $exec %18 = V_ADDC_U32_e32 %17.sub1, %19, implicit-def $vcc, implicit $vcc, implicit $exec
%20 = REG_SEQUENCE %21, 1, killed %18, 2 %20 = REG_SEQUENCE %21, 1, killed %18, 2
%10 = V_MOV_B32_e32 999234234, implicit $exec %10 = V_MOV_B32_e32 999234234, implicit $exec
%24 = V_MOV_B32_e32 3871, implicit $exec %24 = V_MOV_B32_e32 3871, implicit $exec
%6 = V_MOV_B32_e32 1000000, implicit $exec %6 = V_MOV_B32_e32 1000000, implicit $exec
%7 = S_MOV_B32 13424252 %7 = S_MOV_B32 13424252
%8 = S_MOV_B32 4 %8 = S_MOV_B32 4
%27 = S_MOV_B32 -4 %27 = S_MOV_B32 -4
%32 = S_MOV_B32 1 %32 = S_MOV_B32 1
%33 = S_MOV_B32 3841 %33 = S_MOV_B32 3841
%34 = V_MOV_B32_e32 3841, implicit $exec %34 = V_MOV_B32_e32 3841, implicit $exec
%35 = V_MOV_B32_e32 2, implicit $exec %35 = V_MOV_B32_e32 2, implicit $exec
%11 = V_ASHRREV_I32_e64 8, %10, implicit $exec %11 = V_ASHRREV_I32_e64 8, %10, implicit $exec
FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%12 = V_ASHRREV_I32_e64 %8, %10, implicit $exec %12 = V_ASHRREV_I32_e64 %8, %10, implicit $exec
FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %12, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%13 = V_ASHR_I32_e64 %7, 3, implicit $exec %13 = V_ASHR_I32_e64 %7, 3, implicit $exec
FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %13, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%14 = V_ASHR_I32_e64 7, %32, implicit $exec %14 = V_ASHR_I32_e64 7, %32, implicit $exec
FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %14, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%15 = V_ASHR_I32_e64 %27, %24, implicit $exec %15 = V_ASHR_I32_e64 %27, %24, implicit $exec
FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %15, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%22 = V_ASHR_I32_e64 %6, 4, implicit $exec %22 = V_ASHR_I32_e64 %6, 4, implicit $exec
FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %22, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%23 = V_ASHR_I32_e64 %6, %33, implicit $exec %23 = V_ASHR_I32_e64 %6, %33, implicit $exec
FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %23, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%25 = V_ASHR_I32_e32 %34, %34, implicit $exec %25 = V_ASHR_I32_e32 %34, %34, implicit $exec
FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %25, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%26 = V_ASHRREV_I32_e32 11, %10, implicit $exec %26 = V_ASHRREV_I32_e32 11, %10, implicit $exec
FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %26, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%28 = V_ASHR_I32_e32 %27, %35, implicit $exec %28 = V_ASHR_I32_e32 %27, %35, implicit $exec
FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %28, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: s_fold_lshr_imm_regimm_32{{$}} # GCN-LABEL: name: s_fold_lshr_imm_regimm_32{{$}}
# GCN: %11:vgpr_32 = V_MOV_B32_e32 1048332, implicit $exec # GCN: %11:vgpr_32 = V_MOV_B32_e32 1048332, implicit $exec
Show All 34 LinesframeInfo:
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 36, 0 %4 = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
%5 = S_MOV_B32 -999123 %5 = S_MOV_B32 -999123
%6 = COPY %4.sub1 %6 = COPY %4.sub1
%7 = COPY %4.sub0 %7 = COPY %4.sub0
%8 = S_MOV_B32 61440 %8 = S_MOV_B32 61440
%9 = S_MOV_B32 -1 %9 = S_MOV_B32 -1
%10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4 %10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4
%12 = S_LSHR_B32 killed %5, 12, implicit-def dead $scc %12 = S_LSHR_B32 killed %5, 12, implicit-def dead $scc
%13 = COPY %12 %13 = COPY %12
BUFFER_STORE_DWORD_OFFSET killed %13, killed %10, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed %13, killed %10, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: v_fold_lshr_imm_regimm_32{{$}} # GCN-LABEL: name: v_fold_lshr_imm_regimm_32{{$}}
# GCN: %11:vgpr_32 = V_MOV_B32_e32 3903258, implicit $exec # GCN: %11:vgpr_32 = V_MOV_B32_e32 3903258, implicit $exec
# GCN: FLAT_STORE_DWORD %20, %11, # GCN: FLAT_STORE_DWORD %20, %11,
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%2 = COPY $vgpr0 %2 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%3 = S_LOAD_DWORDX2_IMM %0, 36, 0 %3 = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
%15 = V_ASHRREV_I32_e64 31, %2, implicit $exec %15 = V_ASHRREV_I32_e64 31, %2, implicit $exec
%16 = REG_SEQUENCE %2, 1, %15, 2 %16 = REG_SEQUENCE %2, 1, %15, 2
%17 = V_LSHLREV_B64 2, killed %16, implicit $exec %17 = V_LSHLREV_B64 2, killed %16, implicit $exec
%9 = COPY %3.sub1 %9 = COPY %3.sub1
%21 = V_ADD_I32_e32 %3.sub0, %17.sub0, implicit-def $vcc, implicit $exec %21 = V_ADD_I32_e32 %3.sub0, %17.sub0, implicit-def $vcc, implicit $exec
%19 = COPY killed %9 %19 = COPY killed %9
%18 = V_ADDC_U32_e32 %17.sub1, %19, implicit-def $vcc, implicit $vcc, implicit $exec %18 = V_ADDC_U32_e32 %17.sub1, %19, implicit-def $vcc, implicit $vcc, implicit $exec
%20 = REG_SEQUENCE %21, 1, killed %18, 2 %20 = REG_SEQUENCE %21, 1, killed %18, 2
%10 = V_MOV_B32_e32 999234234, implicit $exec %10 = V_MOV_B32_e32 999234234, implicit $exec
%24 = V_MOV_B32_e32 3871, implicit $exec %24 = V_MOV_B32_e32 3871, implicit $exec
%6 = V_MOV_B32_e32 1000000, implicit $exec %6 = V_MOV_B32_e32 1000000, implicit $exec
%7 = S_MOV_B32 13424252 %7 = S_MOV_B32 13424252
%8 = S_MOV_B32 4 %8 = S_MOV_B32 4
%27 = S_MOV_B32 -4 %27 = S_MOV_B32 -4
%32 = S_MOV_B32 1 %32 = S_MOV_B32 1
%33 = S_MOV_B32 3841 %33 = S_MOV_B32 3841
%34 = V_MOV_B32_e32 3841, implicit $exec %34 = V_MOV_B32_e32 3841, implicit $exec
%35 = V_MOV_B32_e32 2, implicit $exec %35 = V_MOV_B32_e32 2, implicit $exec
%11 = V_LSHRREV_B32_e64 8, %10, implicit $exec %11 = V_LSHRREV_B32_e64 8, %10, implicit $exec
FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%12 = V_LSHRREV_B32_e64 %8, %10, implicit $exec %12 = V_LSHRREV_B32_e64 %8, %10, implicit $exec
FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %12, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%13 = V_LSHR_B32_e64 %7, 3, implicit $exec %13 = V_LSHR_B32_e64 %7, 3, implicit $exec
FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %13, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%14 = V_LSHR_B32_e64 7, %32, implicit $exec %14 = V_LSHR_B32_e64 7, %32, implicit $exec
FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %14, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%15 = V_LSHR_B32_e64 %27, %24, implicit $exec %15 = V_LSHR_B32_e64 %27, %24, implicit $exec
FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %15, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%22 = V_LSHR_B32_e64 %6, 4, implicit $exec %22 = V_LSHR_B32_e64 %6, 4, implicit $exec
FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %22, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%23 = V_LSHR_B32_e64 %6, %33, implicit $exec %23 = V_LSHR_B32_e64 %6, %33, implicit $exec
FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %23, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%25 = V_LSHR_B32_e32 %34, %34, implicit $exec %25 = V_LSHR_B32_e32 %34, %34, implicit $exec
FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %25, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%26 = V_LSHRREV_B32_e32 11, %10, implicit $exec %26 = V_LSHRREV_B32_e32 11, %10, implicit $exec
FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %26, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%28 = V_LSHR_B32_e32 %27, %35, implicit $exec %28 = V_LSHR_B32_e32 %27, %35, implicit $exec
FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD %20, %28, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# There is only an undef use operand for %1, so there is no # There is only an undef use operand for %1, so there is no
# corresponding defining instruction # corresponding defining instruction
# GCN-LABEL: name: undefined_vreg_operand{{$}} # GCN-LABEL: name: undefined_vreg_operand{{$}}
# GCN: bb.0 # GCN: bb.0
# GCN-NEXT: FLAT_STORE_DWORD undef %3:vreg_64, undef %1:vgpr_32, # GCN-NEXT: FLAT_STORE_DWORD undef %3:vreg_64, undef %1:vgpr_32,
# GCN-NEXT: S_ENDPGM 0 # GCN-NEXT: S_ENDPGM 0
name: undefined_vreg_operand name: undefined_vreg_operand
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vgpr_32, preferred-register: '' } - { id: 0, class: vgpr_32, preferred-register: '' }
- { id: 1, class: vgpr_32, preferred-register: '' } - { id: 1, class: vgpr_32, preferred-register: '' }
- { id: 2, class: vgpr_32, preferred-register: '' } - { id: 2, class: vgpr_32, preferred-register: '' }
- { id: 3, class: vreg_64, preferred-register: '' } - { id: 3, class: vreg_64, preferred-register: '' }
body: | body: |
bb.0: bb.0:
%0 = V_MOV_B32_e32 0, implicit $exec %0 = V_MOV_B32_e32 0, implicit $exec
%2 = V_XOR_B32_e64 killed %0, undef %1, implicit $exec %2 = V_XOR_B32_e64 killed %0, undef %1, implicit $exec
FLAT_STORE_DWORD undef %3, %2, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD undef %3, %2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Make sure there is no crash if one of the operands is a physical register # Make sure there is no crash if one of the operands is a physical register
# GCN-LABEL: name: constant_fold_physreg_op{{$}} # GCN-LABEL: name: constant_fold_physreg_op{{$}}
# GCN: %3:sreg_64 = S_AND_B64 $exec, 0, implicit-def dead $scc # GCN: %3:sreg_64 = S_AND_B64 $exec, 0, implicit-def dead $scc
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir

Show First 20 Lines • Show All 285 Lines • ▼ Show 20 Lines bb.2.._crit_edge3575:
successors: %bb.5(0x40000000), %bb.3(0x40000000) successors: %bb.5(0x40000000), %bb.3(0x40000000)
S_CBRANCH_SCC1 %bb.5, implicit undef $scc S_CBRANCH_SCC1 %bb.5, implicit undef $scc
S_BRANCH %bb.3 S_BRANCH %bb.3
bb.3..lr.ph3410.preheader: bb.3..lr.ph3410.preheader:
successors: %bb.4(0x80000000) successors: %bb.4(0x80000000)
dead %22:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %53.sub3, undef %24:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4) dead %22:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %53.sub3, undef %24:sreg_128, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
dead %60:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec dead %60:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
%36:sreg_64 = S_AND_B64 $exec, -1, implicit-def dead $scc %36:sreg_64 = S_AND_B64 $exec, -1, implicit-def dead $scc
dead %67:vgpr_32 = V_MOV_B32_e32 0, implicit $exec dead %67:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
bb.4..lr.ph3410: bb.4..lr.ph3410:
successors: %bb.4(0x7c000000), %bb.6(0x04000000) successors: %bb.4(0x7c000000), %bb.6(0x04000000)
$vcc = COPY %36 $vcc = COPY %36
Show All 17 Lines

llvm/trunk/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir

# RUN: llc -mtriple=amdgcn-- -run-pass=liveintervals,dead-mi-elimination,simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s # RUN: llc -mtriple=amdgcn-- -run-pass=liveintervals,dead-mi-elimination,simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# This is used to fail verififcation if MachineDCE tracks LIS. # This is used to fail verififcation if MachineDCE tracks LIS.
# GCN-LABEL: name: foo # GCN-LABEL: name: foo
# GCN: S_ENDPGM # GCN: S_ENDPGM
--- ---
name: foo name: foo
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
%10:sreg_128 = S_LOAD_DWORDX4_IMM killed $noreg, 9, 0 %10:sreg_128 = S_LOAD_DWORDX4_IMM killed $noreg, 9, 0, 0
S_NOP 0, implicit-def %4:sreg_128, implicit %10.sub1:sreg_128 S_NOP 0, implicit-def %4:sreg_128, implicit %10.sub1:sreg_128
S_CBRANCH_SCC0 %bb.3, implicit undef $scc S_CBRANCH_SCC0 %bb.3, implicit undef $scc
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
S_CBRANCH_SCC0 %bb.2, implicit undef $scc S_CBRANCH_SCC0 %bb.2, implicit undef $scc
S_BRANCH %bb.3 S_BRANCH %bb.3
bb.2: bb.2:
%8:sreg_32_xm0 = COPY %4.sub1:sreg_128 %8:sreg_32_xm0 = COPY %4.sub1:sreg_128
%7:sreg_32_xm0 = COPY %10.sub1:sreg_128 %7:sreg_32_xm0 = COPY %10.sub1:sreg_128
S_BRANCH %bb.4 S_BRANCH %bb.4
bb.3: bb.3:
%10:sreg_128 = S_LOAD_DWORDX4_IMM killed $noreg, 10, 0 %10:sreg_128 = S_LOAD_DWORDX4_IMM killed $noreg, 10, 0, 0
%7:sreg_32_xm0 = COPY %10.sub1:sreg_128 %7:sreg_32_xm0 = COPY %10.sub1:sreg_128
%8:sreg_32_xm0 = COPY %10.sub2:sreg_128 %8:sreg_32_xm0 = COPY %10.sub2:sreg_128
bb.4: bb.4:
S_NOP 0, implicit %10 S_NOP 0, implicit %10
$sgpr0 = COPY %8:sreg_32_xm0 $sgpr0 = COPY %8:sreg_32_xm0
$sgpr1 = COPY %7:sreg_32_xm0 $sgpr1 = COPY %7:sreg_32_xm0
S_ENDPGM 0, implicit $sgpr0, implicit $sgpr1 S_ENDPGM 0, implicit $sgpr0, implicit $sgpr1
... ...

llvm/trunk/test/CodeGen/AMDGPU/dead-lane.mir

# RUN: llc -march=amdgcn -mcpu=tonga %s -start-before detect-dead-lanes -stop-before machine-scheduler -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=tonga %s -start-before detect-dead-lanes -stop-before machine-scheduler -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: dead_lane # GCN-LABEL: name: dead_lane
# GCN: bb.0: # GCN: bb.0:
# GCN-NEXT: undef %3.sub0:vreg_64 = V_MAC_F32_e32 undef %1:vgpr_32, undef %1:vgpr_32, undef %3.sub0, implicit $exec # GCN-NEXT: undef %3.sub0:vreg_64 = V_MAC_F32_e32 undef %1:vgpr_32, undef %1:vgpr_32, undef %3.sub0, implicit $exec
# GCN-NEXT: FLAT_STORE_DWORD undef %4:vreg_64, %3.sub0, # GCN-NEXT: FLAT_STORE_DWORD undef %4:vreg_64, %3.sub0,
--- ---
name: dead_lane name: dead_lane
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
%1:vgpr_32 = V_MAC_F32_e32 undef %0:vgpr_32, undef %0:vgpr_32, undef %0:vgpr_32, implicit $exec %1:vgpr_32 = V_MAC_F32_e32 undef %0:vgpr_32, undef %0:vgpr_32, undef %0:vgpr_32, implicit $exec
%2:vgpr_32 = V_MAC_F32_e32 undef %0:vgpr_32, undef %0:vgpr_32, undef %0:vgpr_32, implicit $exec %2:vgpr_32 = V_MAC_F32_e32 undef %0:vgpr_32, undef %0:vgpr_32, undef %0:vgpr_32, implicit $exec
%3:vreg_64 = REG_SEQUENCE %1:vgpr_32, %subreg.sub0, %2:vgpr_32, %subreg.sub1 %3:vreg_64 = REG_SEQUENCE %1:vgpr_32, %subreg.sub0, %2:vgpr_32, %subreg.sub1
FLAT_STORE_DWORD undef %4:vreg_64, %3.sub0, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD undef %4:vreg_64, %3.sub0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/dead-mi-use-same-intr.mir

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Linesregisters:
- { id: 0, class: vgpr_32 } - { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 } - { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 } - { id: 2, class: vgpr_32 }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1 = IMPLICIT_DEF %1 = IMPLICIT_DEF
%2 = IMPLICIT_DEF %2 = IMPLICIT_DEF
GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %2, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %2, 0, 0, 0, 0, implicit $exec
dead %2:vgpr_32 = V_MAC_F32_e32 %0:vgpr_32, %1:vgpr_32, %2:vgpr_32, implicit $exec dead %2:vgpr_32 = V_MAC_F32_e32 %0:vgpr_32, %1:vgpr_32, %2:vgpr_32, implicit $exec
S_ENDPGM 0 S_ENDPGM 0

llvm/trunk/test/CodeGen/AMDGPU/dead_copy.mir

Show All 17 Lines bb.0:
$vgpr5 = COPY $vgpr11, implicit $exec $vgpr5 = COPY $vgpr11, implicit $exec
$sgpr14 = S_ADD_U32 $sgpr0, target-flags(amdgpu-gotprel) 1136, implicit-def $scc $sgpr14 = S_ADD_U32 $sgpr0, target-flags(amdgpu-gotprel) 1136, implicit-def $scc
$sgpr15 = S_ADDC_U32 $sgpr1, target-flags(amdgpu-gotprel32-lo) 0, implicit-def dead $scc, implicit $scc $sgpr15 = S_ADDC_U32 $sgpr1, target-flags(amdgpu-gotprel32-lo) 0, implicit-def dead $scc, implicit $scc
$vgpr10 = COPY killed $sgpr14, implicit $exec $vgpr10 = COPY killed $sgpr14, implicit $exec
$vgpr11 = COPY killed $sgpr15, implicit $exec $vgpr11 = COPY killed $sgpr15, implicit $exec
FLAT_STORE_DWORDX4 $vgpr10_vgpr11, $vgpr4_vgpr5_vgpr6_vgpr7, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORDX4 $vgpr10_vgpr11, $vgpr4_vgpr5_vgpr6_vgpr7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
... ...

llvm/trunk/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Linesbody: |
; CHECK: $vgpr1 = COPY [[V_MUL_F32_e32_2]] ; CHECK: $vgpr1 = COPY [[V_MUL_F32_e32_2]]
; CHECK: $vgpr2 = COPY [[V_MUL_F32_e32_3]] ; CHECK: $vgpr2 = COPY [[V_MUL_F32_e32_3]]
; CHECK: dead $sgpr30_sgpr31 = SI_CALL [[DEF14]], @foo, csr_amdgpu_highregs, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit-def $vgpr0 ; CHECK: dead $sgpr30_sgpr31 = SI_CALL [[DEF14]], @foo, csr_amdgpu_highregs, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit-def $vgpr0
; CHECK: [[V_ADD_F32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_F32_e32 [[V_MUL_F32_e32_]], [[DEF8]], implicit $exec ; CHECK: [[V_ADD_F32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_F32_e32 [[V_MUL_F32_e32_]], [[DEF8]], implicit $exec
; CHECK: [[V_MAC_F32_e32_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e32 [[DEF12]], [[DEF9]], [[V_MAC_F32_e32_]], implicit $exec ; CHECK: [[V_MAC_F32_e32_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e32 [[DEF12]], [[DEF9]], [[V_MAC_F32_e32_]], implicit $exec
; CHECK: dead %26:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF4]], 0, [[DEF1]], 0, 0, implicit $exec ; CHECK: dead %26:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF4]], 0, [[DEF1]], 0, 0, implicit $exec
; CHECK: dead %27:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF5]], 0, [[DEF2]], 0, 0, implicit $exec ; CHECK: dead %27:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF5]], 0, [[DEF2]], 0, 0, implicit $exec
; CHECK: dead %28:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF6]], 0, [[DEF3]], 0, 0, implicit $exec ; CHECK: dead %28:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF6]], 0, [[DEF3]], 0, 0, implicit $exec
; CHECK: GLOBAL_STORE_DWORD [[DEF]], [[DEF10]], 0, 0, 0, implicit $exec ; CHECK: GLOBAL_STORE_DWORD [[DEF]], [[DEF10]], 0, 0, 0, 0, implicit $exec
; CHECK: S_ENDPGM 0 ; CHECK: S_ENDPGM 0
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
%0:vreg_64 = IMPLICIT_DEF %0:vreg_64 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF %1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF %2:vgpr_32 = IMPLICIT_DEF
%3:vgpr_32 = IMPLICIT_DEF %3:vgpr_32 = IMPLICIT_DEF
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines bb.3:
$vgpr2 = COPY %18 $vgpr2 = COPY %18
$sgpr4 = IMPLICIT_DEF $sgpr4 = IMPLICIT_DEF
dead $sgpr30_sgpr31 = SI_CALL %24, @foo, csr_amdgpu_highregs, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit killed $vgpr0, implicit killed $vgpr1, implicit killed $vgpr2, implicit-def $vgpr0 dead $sgpr30_sgpr31 = SI_CALL %24, @foo, csr_amdgpu_highregs, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit killed $vgpr0, implicit killed $vgpr1, implicit killed $vgpr2, implicit-def $vgpr0
%25:vgpr_32 = V_ADD_F32_e32 %9, %8, implicit $exec %25:vgpr_32 = V_ADD_F32_e32 %9, %8, implicit $exec
%25:vgpr_32 = V_MAC_F32_e32 %15, %10, %25, implicit $exec %25:vgpr_32 = V_MAC_F32_e32 %15, %10, %25, implicit $exec
%26:vgpr_32 = V_MAD_F32 0, %25, 0, %4, 0, %1, 0, 0, implicit $exec %26:vgpr_32 = V_MAD_F32 0, %25, 0, %4, 0, %1, 0, 0, implicit $exec
%27:vgpr_32 = V_MAD_F32 0, %25, 0, %5, 0, %2, 0, 0, implicit $exec %27:vgpr_32 = V_MAD_F32 0, %25, 0, %5, 0, %2, 0, 0, implicit $exec
%28:vgpr_32 = V_MAD_F32 0, %25, 0, %6, 0, %3, 0, 0, implicit $exec %28:vgpr_32 = V_MAD_F32 0, %25, 0, %6, 0, %3, 0, 0, implicit $exec
GLOBAL_STORE_DWORD %0, %11, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORD %0, %11, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/endpgm-dce.mir

Show All 11 Linesregisters:
- { id: 3, class: sgpr_32 } - { id: 3, class: sgpr_32 }
- { id: 4, class: sgpr_32 } - { id: 4, class: sgpr_32 }
body: | body: |
bb.0: bb.0:
$vcc = IMPLICIT_DEF $vcc = IMPLICIT_DEF
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%3 = IMPLICIT_DEF %3 = IMPLICIT_DEF
$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
%1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
%2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec
%4 = S_ADD_U32 %3, 1, implicit-def $scc %4 = S_ADD_U32 %3, 1, implicit-def $scc
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_without_memoperand # GCN-LABEL: name: load_without_memoperand
# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
# GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr # GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
# GCN-NEXT: S_ENDPGM 0 # GCN-NEXT: S_ENDPGM 0
name: load_without_memoperand name: load_without_memoperand
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_64 } - { id: 0, class: vreg_64 }
- { id: 1, class: vgpr_32 } - { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 } - { id: 2, class: vgpr_32 }
- { id: 3, class: sgpr_32 } - { id: 3, class: sgpr_32 }
- { id: 4, class: sgpr_32 } - { id: 4, class: sgpr_32 }
body: | body: |
bb.0: bb.0:
$vcc = IMPLICIT_DEF $vcc = IMPLICIT_DEF
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%3 = IMPLICIT_DEF %3 = IMPLICIT_DEF
$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
%1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec
%4 = S_ADD_U32 %3, 1, implicit-def $scc %4 = S_ADD_U32 %3, 1, implicit-def $scc
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_volatile # GCN-LABEL: name: load_volatile
# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
# GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4) # GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4)
# GCN-NEXT: S_ENDPGM 0 # GCN-NEXT: S_ENDPGM 0
name: load_volatile name: load_volatile
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_64 } - { id: 0, class: vreg_64 }
- { id: 1, class: vgpr_32 } - { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 } - { id: 2, class: vgpr_32 }
- { id: 3, class: sgpr_32 } - { id: 3, class: sgpr_32 }
- { id: 4, class: sgpr_32 } - { id: 4, class: sgpr_32 }
body: | body: |
bb.0: bb.0:
$vcc = IMPLICIT_DEF $vcc = IMPLICIT_DEF
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%3 = IMPLICIT_DEF %3 = IMPLICIT_DEF
$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
%1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4) %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4)
%2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec
%4 = S_ADD_U32 %3, 1, implicit-def $scc %4 = S_ADD_U32 %3, 1, implicit-def $scc
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store # GCN-LABEL: name: store
# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
# GCN-NEXT: FLAT_STORE_DWORD %0, %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) # GCN-NEXT: FLAT_STORE_DWORD %0, %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
# GCN-NEXT: S_ENDPGM 0 # GCN-NEXT: S_ENDPGM 0
name: store name: store
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_64 } - { id: 0, class: vreg_64 }
- { id: 1, class: vgpr_32 } - { id: 1, class: vgpr_32 }
body: | body: |
bb.0: bb.0:
$vcc = IMPLICIT_DEF $vcc = IMPLICIT_DEF
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1 = IMPLICIT_DEF %1 = IMPLICIT_DEF
$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
FLAT_STORE_DWORD %0, %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) FLAT_STORE_DWORD %0, %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: barrier # GCN-LABEL: name: barrier
# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
# GCN-NEXT: S_BARRIER # GCN-NEXT: S_BARRIER
# GCN-NEXT: S_ENDPGM 0 # GCN-NEXT: S_ENDPGM 0
name: barrier name: barrier
▲ Show 20 Lines • Show All 194 Lines • ▼ Show 20 Lines bb.1:
$vcc = IMPLICIT_DEF $vcc = IMPLICIT_DEF
$sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...
# GCN-LABEL: name: implicit_use_on_s_endpgm # GCN-LABEL: name: implicit_use_on_S_ENDPGM 0
# GCN: V_ADD_I32 # GCN: V_ADD_I32
# GCN: COPY # GCN: COPY
# GCN: V_ADDC_U32 # GCN: V_ADDC_U32
# GCN: S_ENDPGM 0, implicit %3 # GCN: S_ENDPGM 0, implicit %3
name: implicit_use_on_s_endpgm name: implicit_use_on_S_ENDPGM 0
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
dead %0:vgpr_32 = V_ADD_I32_e32 12345, undef %1:vgpr_32, implicit-def $vcc, implicit $exec dead %0:vgpr_32 = V_ADD_I32_e32 12345, undef %1:vgpr_32, implicit-def $vcc, implicit $exec
%2:sreg_64_xexec = COPY $vcc %2:sreg_64_xexec = COPY $vcc
%3:vgpr_32, dead %4:sreg_64_xexec = V_ADDC_U32_e64 undef %5:vgpr_32, undef %6:vgpr_32, %2, 0, implicit $exec %3:vgpr_32, dead %4:sreg_64_xexec = V_ADDC_U32_e64 undef %5:vgpr_32, undef %6:vgpr_32, %2, 0, implicit $exec
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...

llvm/trunk/test/CodeGen/AMDGPU/flat-load-clustering.mir

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linesliveins:
- { reg: '$vgpr0', virtual-reg: '%0' } - { reg: '$vgpr0', virtual-reg: '%0' }
- { reg: '$sgpr4_sgpr5', virtual-reg: '%1' } - { reg: '$sgpr4_sgpr5', virtual-reg: '%1' }
body: | body: |
bb.0.bb: bb.0.bb:
liveins: $vgpr0, $sgpr4_sgpr5 liveins: $vgpr0, $sgpr4_sgpr5
%1 = COPY $sgpr4_sgpr5 %1 = COPY $sgpr4_sgpr5
%0 = COPY $vgpr0 %0 = COPY $vgpr0
%3 = S_LOAD_DWORDX2_IMM %1, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %3 = S_LOAD_DWORDX2_IMM %1, 0, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%4 = S_LOAD_DWORDX2_IMM %1, 8, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %4 = S_LOAD_DWORDX2_IMM %1, 8, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%7 = V_LSHLREV_B32_e32 2, %0, implicit $exec %7 = V_LSHLREV_B32_e32 2, %0, implicit $exec
%2 = V_MOV_B32_e32 0, implicit $exec %2 = V_MOV_B32_e32 0, implicit $exec
undef %12.sub0 = V_ADD_I32_e32 %4.sub0, %7, implicit-def $vcc, implicit $exec undef %12.sub0 = V_ADD_I32_e32 %4.sub0, %7, implicit-def $vcc, implicit $exec
%11 = COPY %4.sub1 %11 = COPY %4.sub1
%12.sub1 = V_ADDC_U32_e32 %11, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec %12.sub1 = V_ADDC_U32_e32 %11, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
%5 = FLAT_LOAD_DWORD %12, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.gep1) %5 = FLAT_LOAD_DWORD %12, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.gep1)
undef %9.sub0 = V_ADD_I32_e32 %3.sub0, %7, implicit-def $vcc, implicit $exec undef %9.sub0 = V_ADD_I32_e32 %3.sub0, %7, implicit-def $vcc, implicit $exec
%8 = COPY %3.sub1 %8 = COPY %3.sub1
%9.sub1 = V_ADDC_U32_e32 %8, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec %9.sub1 = V_ADDC_U32_e32 %8, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
undef %13.sub0 = V_ADD_I32_e32 16, %12.sub0, implicit-def $vcc, implicit $exec undef %13.sub0 = V_ADD_I32_e32 16, %12.sub0, implicit-def $vcc, implicit $exec
%13.sub1 = V_ADDC_U32_e32 %12.sub1, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec %13.sub1 = V_ADDC_U32_e32 %12.sub1, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
%6 = FLAT_LOAD_DWORD %13, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.gep34) %6 = FLAT_LOAD_DWORD %13, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.gep34)
undef %10.sub0 = V_ADD_I32_e32 16, %9.sub0, implicit-def $vcc, implicit $exec undef %10.sub0 = V_ADD_I32_e32 16, %9.sub0, implicit-def $vcc, implicit $exec
%10.sub1 = V_ADDC_U32_e32 %9.sub1, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec %10.sub1 = V_ADDC_U32_e32 %9.sub1, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
FLAT_STORE_DWORD %9, %5, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.gep2) FLAT_STORE_DWORD %9, %5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.gep2)
FLAT_STORE_DWORD %10, %6, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.gep4) FLAT_STORE_DWORD %10, %6, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.gep4)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/flat-offset-bug.ll

; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
; GCN-LABEL: flat_inst_offset:
; GFX9: flat_load_dword v{{[0-9]+}}, v[{{[0-9:]+}}] offset:4
; GFX9: flat_store_dword v[{{[0-9:]+}}], v{{[0-9]+}} offset:4
; GFX10: flat_load_dword v{{[0-9]+}}, v[{{[0-9:]+}}]{{$}}
; GFX10: flat_store_dword v[{{[0-9:]+}}], v{{[0-9]+}}{{$}}
define void @flat_inst_offset(i32* nocapture %p) {
%gep = getelementptr inbounds i32, i32* %p, i64 1
%load = load i32, i32* %gep, align 4
%inc = add nsw i32 %load, 1
store i32 %inc, i32* %gep, align 4
ret void
}
; GCN-LABEL: global_inst_offset:
; GCN: global_load_dword v{{[0-9]+}}, v[{{[0-9:]+}}], off offset:4
; GCN: global_store_dword v[{{[0-9:]+}}], v{{[0-9]+}}, off offset:4
define void @global_inst_offset(i32 addrspace(1)* nocapture %p) {
%gep = getelementptr inbounds i32, i32 addrspace(1)* %p, i64 1
%load = load i32, i32 addrspace(1)* %gep, align 4
%inc = add nsw i32 %load, 1
store i32 %inc, i32 addrspace(1)* %gep, align 4
ret void
}
; GCN-LABEL: load_i16_lo:
; GFX9 : flat_load_short_d16 v{{[0-9]+}}, v[{{[0-9:]+}}] offset:8{{$}}
; GFX10: flat_load_short_d16 v{{[0-9]+}}, v[{{[0-9:]+}}]{{$}}
define amdgpu_kernel void @load_i16_lo(i16* %arg, <2 x i16>* %out) {
%gep = getelementptr inbounds i16, i16* %arg, i32 4
%ld = load i16, i16* %gep, align 2
%vec = insertelement <2 x i16> <i16 undef, i16 0>, i16 %ld, i32 0
%v = add <2 x i16> %vec, %vec
store <2 x i16> %v, <2 x i16>* %out, align 4
ret void
}
; GCN-LABEL: load_i16_hi:
; GFX9: flat_load_short_d16_hi v{{[0-9]+}}, v[{{[0-9:]+}}] offset:8{{$}}
; GFX10: flat_load_short_d16_hi v{{[0-9]+}}, v[{{[0-9:]+}}]{{$}}
define amdgpu_kernel void @load_i16_hi(i16* %arg, <2 x i16>* %out) {
%gep = getelementptr inbounds i16, i16* %arg, i32 4
%ld = load i16, i16* %gep, align 2
%vec = insertelement <2 x i16> <i16 0, i16 undef>, i16 %ld, i32 1
%v = add <2 x i16> %vec, %vec
store <2 x i16> %v, <2 x i16>* %out, align 4
ret void
}
; GCN-LABEL: load_half_lo:
; GFX9: flat_load_short_d16 v{{[0-9]+}}, v[{{[0-9:]+}}] offset:8{{$}}
; GFX10: flat_load_short_d16 v{{[0-9]+}}, v[{{[0-9:]+}}]{{$}}
define amdgpu_kernel void @load_half_lo(half* %arg, <2 x half>* %out) {
%gep = getelementptr inbounds half, half* %arg, i32 4
%ld = load half, half* %gep, align 2
%vec = insertelement <2 x half> <half undef, half 0xH0000>, half %ld, i32 0
%v = fadd <2 x half> %vec, %vec
store <2 x half> %v, <2 x half>* %out, align 4
ret void
}
; GCN-LABEL: load_half_hi:
; GFX9: flat_load_short_d16_hi v{{[0-9]+}}, v[{{[0-9:]+}}] offset:8{{$}}
; GFX10: flat_load_short_d16_hi v{{[0-9]+}}, v[{{[0-9:]+}}]{{$}}
define amdgpu_kernel void @load_half_hi(half* %arg, <2 x half>* %out) {
%gep = getelementptr inbounds half, half* %arg, i32 4
%ld = load half, half* %gep, align 2
%vec = insertelement <2 x half> <half 0xH0000, half undef>, half %ld, i32 1
%v = fadd <2 x half> %vec, %vec
store <2 x half> %v, <2 x half>* %out, align 4
ret void
}
; GCN-LABEL: load_float_lo:
; GFX9: flat_load_dword v{{[0-9]+}}, v[{{[0-9:]+}}] offset:16{{$}}
; GFX10: flat_load_dword v{{[0-9]+}}, v[{{[0-9:]+}}]{{$}}
define amdgpu_kernel void @load_float_lo(float* %arg, float* %out) {
%gep = getelementptr inbounds float, float* %arg, i32 4
%ld = load float, float* %gep, align 4
%v = fadd float %ld, %ld
store float %v, float* %out, align 4
ret void
}

llvm/trunk/test/CodeGen/AMDGPU/fold-imm-copy.mir

# RUN: llc -march=amdgcn -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: fold-imm-copy # GCN-LABEL: name: fold-imm-copy
# GCN: [[SREG:%[0-9+]]]:sreg_32_xm0 = S_MOV_B32 65535 # GCN: [[SREG:%[0-9+]]]:sreg_32_xm0 = S_MOV_B32 65535
# GCN: V_AND_B32_e32 [[SREG]] # GCN: V_AND_B32_e32 [[SREG]]
name: fold-imm-copy name: fold-imm-copy
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%1:sgpr_64 = COPY $sgpr0_sgpr1 %1:sgpr_64 = COPY $sgpr0_sgpr1
%2:sreg_128 = S_LOAD_DWORDX4_IMM %1, 9, 0 %2:sreg_128 = S_LOAD_DWORDX4_IMM %1, 9, 0, 0
%3:sreg_32_xm0 = S_MOV_B32 2 %3:sreg_32_xm0 = S_MOV_B32 2
%4:vgpr_32 = V_LSHLREV_B32_e64 killed %3, %0, implicit $exec %4:vgpr_32 = V_LSHLREV_B32_e64 killed %3, %0, implicit $exec
%5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%6:vreg_64 = REG_SEQUENCE killed %4, %subreg.sub0, killed %5, %subreg.sub1 %6:vreg_64 = REG_SEQUENCE killed %4, %subreg.sub0, killed %5, %subreg.sub1
%7:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 %6, %2, 0, 4, 0, 0, 0, implicit $exec %7:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 %6, %2, 0, 4, 0, 0, 0, 0, implicit $exec
%8:sreg_32_xm0 = S_MOV_B32 65535 %8:sreg_32_xm0 = S_MOV_B32 65535
%9:vgpr_32 = COPY %8 %9:vgpr_32 = COPY %8
%10:vgpr_32 = V_AND_B32_e32 %7, %9, implicit $exec %10:vgpr_32 = V_AND_B32_e32 %7, %9, implicit $exec
... ...

llvm/trunk/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir

Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Linesbody: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
%4 = IMPLICIT_DEF %4 = IMPLICIT_DEF
%5 = COPY %4.sub1 %5 = COPY %4.sub1
%6 = IMPLICIT_DEF %6 = IMPLICIT_DEF
%7 = COPY %6.sub0 %7 = COPY %6.sub0
%8 = S_MOV_B32 61440 %8 = S_MOV_B32 61440
%9 = S_MOV_B32 -1 %9 = S_MOV_B32 -1
%10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
%11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`) %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
%12 = V_MOV_B32_e32 1065353216, implicit $exec %12 = V_MOV_B32_e32 1065353216, implicit $exec
%13 = V_ADD_F16_e64 0, killed %11, 0, %12, 0, 0, implicit $exec %13 = V_ADD_F16_e64 0, killed %11, 0, %12, 0, 0, implicit $exec
BUFFER_STORE_SHORT_OFFSET killed %13, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`) BUFFER_STORE_SHORT_OFFSET killed %13, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Materialized f32 inline immediate should not be folded into the f16 # Materialized f32 inline immediate should not be folded into the f16
# operands # operands
# CHECK-LABEL: name: add_f32_1.0_multi_f16_use # CHECK-LABEL: name: add_f32_1.0_multi_f16_use
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Linesbody: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
%4 = IMPLICIT_DEF %4 = IMPLICIT_DEF
%5 = COPY %4.sub1 %5 = COPY %4.sub1
%6 = IMPLICIT_DEF %6 = IMPLICIT_DEF
%7 = COPY %6.sub0 %7 = COPY %6.sub0
%8 = S_MOV_B32 61440 %8 = S_MOV_B32 61440
%9 = S_MOV_B32 -1 %9 = S_MOV_B32 -1
%10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
%11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`) %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
%12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`) %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
%13 = V_MOV_B32_e32 1065353216, implicit $exec %13 = V_MOV_B32_e32 1065353216, implicit $exec
%14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit $exec %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit $exec
%15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit $exec %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit $exec
BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`) BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`) BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# f32 1.0 should be folded into the single f32 use as an inline # f32 1.0 should be folded into the single f32 use as an inline
# immediate, and folded into the single f16 use as a literal constant # immediate, and folded into the single f16 use as a literal constant
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Linesbody: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
%4 = IMPLICIT_DEF %4 = IMPLICIT_DEF
%5 = COPY %4.sub1 %5 = COPY %4.sub1
%6 = IMPLICIT_DEF %6 = IMPLICIT_DEF
%7 = COPY %6.sub0 %7 = COPY %6.sub0
%8 = S_MOV_B32 61440 %8 = S_MOV_B32 61440
%9 = S_MOV_B32 -1 %9 = S_MOV_B32 -1
%10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
%11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`) %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
%12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`) %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
%13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`) %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
%14 = V_MOV_B32_e32 1065353216, implicit $exec %14 = V_MOV_B32_e32 1065353216, implicit $exec
%15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $exec %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $exec
%16 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $exec %16 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $exec
BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`) BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
BUFFER_STORE_DWORD_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`) BUFFER_STORE_DWORD_OFFSET killed %16, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# f32 1.0 should be folded for the single f32 use as an inline # f32 1.0 should be folded for the single f32 use as an inline
# constant, and not folded as a multi-use literal for the f16 cases # constant, and not folded as a multi-use literal for the f16 cases
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Linesbody: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
%4 = IMPLICIT_DEF %4 = IMPLICIT_DEF
%5 = COPY %4.sub1 %5 = COPY %4.sub1
%6 = IMPLICIT_DEF %6 = IMPLICIT_DEF
%7 = COPY %6.sub0 %7 = COPY %6.sub0
%8 = S_MOV_B32 61440 %8 = S_MOV_B32 61440
%9 = S_MOV_B32 -1 %9 = S_MOV_B32 -1
%10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
%11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`) %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
%12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`) %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
%13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`) %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
%14 = V_MOV_B32_e32 1065353216, implicit $exec %14 = V_MOV_B32_e32 1065353216, implicit $exec
%15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $exec %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $exec
%16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit $exec %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit $exec
%17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $exec %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $exec
BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`) BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`) BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`) BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# CHECK-LABEL: name: add_i32_1_multi_f16_use # CHECK-LABEL: name: add_i32_1_multi_f16_use
# CHECK: %13:vgpr_32 = V_MOV_B32_e32 1, implicit $exec # CHECK: %13:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
# CHECK: %14:vgpr_32 = V_ADD_F16_e32 1, killed %11, implicit $exec # CHECK: %14:vgpr_32 = V_ADD_F16_e32 1, killed %11, implicit $exec
# CHECK: %15:vgpr_32 = V_ADD_F16_e32 1, killed %12, implicit $exec # CHECK: %15:vgpr_32 = V_ADD_F16_e32 1, killed %12, implicit $exec
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesbody: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
%4 = IMPLICIT_DEF %4 = IMPLICIT_DEF
%5 = COPY %4.sub1 %5 = COPY %4.sub1
%6 = IMPLICIT_DEF %6 = IMPLICIT_DEF
%7 = COPY %6.sub0 %7 = COPY %6.sub0
%8 = S_MOV_B32 61440 %8 = S_MOV_B32 61440
%9 = S_MOV_B32 -1 %9 = S_MOV_B32 -1
%10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
%11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`) %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
%12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`) %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
%13 = V_MOV_B32_e32 1, implicit $exec %13 = V_MOV_B32_e32 1, implicit $exec
%14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit $exec %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit $exec
%15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit $exec %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit $exec
BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`) BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`) BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# CHECK-LABEL: name: add_i32_m2_one_f32_use_multi_f16_use # CHECK-LABEL: name: add_i32_m2_one_f32_use_multi_f16_use
# CHECK: %14:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec # CHECK: %14:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec
# CHECK: %15:vgpr_32 = V_ADD_F16_e32 -2, %11, implicit $exec # CHECK: %15:vgpr_32 = V_ADD_F16_e32 -2, %11, implicit $exec
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Linesbody: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
%4 = IMPLICIT_DEF %4 = IMPLICIT_DEF
%5 = COPY %4.sub1 %5 = COPY %4.sub1
%6 = IMPLICIT_DEF %6 = IMPLICIT_DEF
%7 = COPY %6.sub0 %7 = COPY %6.sub0
%8 = S_MOV_B32 61440 %8 = S_MOV_B32 61440
%9 = S_MOV_B32 -1 %9 = S_MOV_B32 -1
%10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
%11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`) %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
%12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`) %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
%13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`) %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
%14 = V_MOV_B32_e32 -2, implicit $exec %14 = V_MOV_B32_e32 -2, implicit $exec
%15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $exec %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $exec
%16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit $exec %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit $exec
%17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $exec %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $exec
BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`) BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`) BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`) BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# f32 1.0 should be folded for the single f32 use as an inline # f32 1.0 should be folded for the single f32 use as an inline
# constant, and not folded as a multi-use literal for the f16 cases # constant, and not folded as a multi-use literal for the f16 cases
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Linesbody: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
%4 = IMPLICIT_DEF %4 = IMPLICIT_DEF
%5 = COPY %4.sub1 %5 = COPY %4.sub1
%6 = IMPLICIT_DEF %6 = IMPLICIT_DEF
%7 = COPY %6.sub0 %7 = COPY %6.sub0
%8 = S_MOV_B32 61440 %8 = S_MOV_B32 61440
%9 = S_MOV_B32 -1 %9 = S_MOV_B32 -1
%10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
%11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`) %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
%12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`) %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
%13 = V_MOV_B32_e32 15360, implicit $exec %13 = V_MOV_B32_e32 15360, implicit $exec
%14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit $exec %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit $exec
%15 = V_ADD_F32_e64 0, %12, 0, %13, 0, 0, implicit $exec %15 = V_ADD_F32_e64 0, %12, 0, %13, 0, 0, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`) BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
BUFFER_STORE_DWORD_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`) BUFFER_STORE_DWORD_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# The low 16-bits are an inline immediate, but the high bits are junk # The low 16-bits are an inline immediate, but the high bits are junk
# FIXME: Should be able to fold this # FIXME: Should be able to fold this
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Linesbody: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
%4 = IMPLICIT_DEF %4 = IMPLICIT_DEF
%5 = COPY %4.sub1 %5 = COPY %4.sub1
%6 = IMPLICIT_DEF %6 = IMPLICIT_DEF
%7 = COPY %6.sub0 %7 = COPY %6.sub0
%8 = S_MOV_B32 61440 %8 = S_MOV_B32 61440
%9 = S_MOV_B32 -1 %9 = S_MOV_B32 -1
%10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
%11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`) %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
%12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`) %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
%13 = V_MOV_B32_e32 80886784, implicit $exec %13 = V_MOV_B32_e32 80886784, implicit $exec
%14 = V_ADD_F16_e64 0, %11, 0, %13, 0, 0, implicit $exec %14 = V_ADD_F16_e64 0, %11, 0, %13, 0, 0, implicit $exec
%15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit $exec %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit $exec
BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`) BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`) BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# FIXME: Should fold inline immediate into f16 and literal use into # FIXME: Should fold inline immediate into f16 and literal use into
# f32 instruction. # f32 instruction.
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesbody: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
%4 = IMPLICIT_DEF %4 = IMPLICIT_DEF
%5 = COPY %4.sub1 %5 = COPY %4.sub1
%6 = IMPLICIT_DEF %6 = IMPLICIT_DEF
%7 = COPY %6.sub0 %7 = COPY %6.sub0
%8 = S_MOV_B32 61440 %8 = S_MOV_B32 61440
%9 = S_MOV_B32 -1 %9 = S_MOV_B32 -1
%10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
%11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`) %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
%12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`) %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
%13 = V_MOV_B32_e32 305413120, implicit $exec %13 = V_MOV_B32_e32 305413120, implicit $exec
%14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit $exec %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit $exec
%15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit $exec %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`) BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`) BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir

Show All 40 Linesliveins:
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
- { reg: '$vgpr0', virtual-reg: '%3' } - { reg: '$vgpr0', virtual-reg: '%3' }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
%6 = S_LOAD_DWORDX2_IMM %0, 13, 0 %6 = S_LOAD_DWORDX2_IMM %0, 13, 0, 0
%27 = V_ASHRREV_I32_e32 31, %3, implicit $exec %27 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%28 = REG_SEQUENCE %3, 1, %27, 2 %28 = REG_SEQUENCE %3, 1, %27, 2
%11 = S_MOV_B32 61440 %11 = S_MOV_B32 61440
%12 = S_MOV_B32 0 %12 = S_MOV_B32 0
%13 = REG_SEQUENCE killed %12, 1, killed %11, 2 %13 = REG_SEQUENCE killed %12, 1, killed %11, 2
%14 = REG_SEQUENCE killed %5, 17, %13, 18 %14 = REG_SEQUENCE killed %5, 17, %13, 18
%15 = S_MOV_B32 2 %15 = S_MOV_B32 2
%29 = V_LSHL_B64 killed %28, killed %15, implicit $exec %29 = V_LSHL_B64 killed %28, killed %15, implicit $exec
%17 = REG_SEQUENCE killed %6, 17, %13, 18 %17 = REG_SEQUENCE killed %6, 17, %13, 18
%18 = REG_SEQUENCE killed %4, 17, %13, 18 %18 = REG_SEQUENCE killed %4, 17, %13, 18
%20 = COPY %29 %20 = COPY %29
%19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, implicit $exec %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, 0, implicit $exec
%22 = COPY %29 %22 = COPY %29
%21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, implicit $exec %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, 0, implicit $exec
%23 = V_MOV_B32_e32 1090519040, implicit $exec %23 = V_MOV_B32_e32 1090519040, implicit $exec
%24 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $exec %24 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $exec
%26 = COPY %29 %26 = COPY %29
BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: no_fold_imm_madak_mac_omod_f32 # GCN-LABEL: name: no_fold_imm_madak_mac_omod_f32
# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec # GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec
# GCN: %24:vgpr_32 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 0, 2, implicit $exec # GCN: %24:vgpr_32 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 0, 2, implicit $exec
Show All 34 Linesliveins:
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
- { reg: '$vgpr0', virtual-reg: '%3' } - { reg: '$vgpr0', virtual-reg: '%3' }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
%6 = S_LOAD_DWORDX2_IMM %0, 13, 0 %6 = S_LOAD_DWORDX2_IMM %0, 13, 0, 0
%27 = V_ASHRREV_I32_e32 31, %3, implicit $exec %27 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%28 = REG_SEQUENCE %3, 1, %27, 2 %28 = REG_SEQUENCE %3, 1, %27, 2
%11 = S_MOV_B32 61440 %11 = S_MOV_B32 61440
%12 = S_MOV_B32 0 %12 = S_MOV_B32 0
%13 = REG_SEQUENCE killed %12, 1, killed %11, 2 %13 = REG_SEQUENCE killed %12, 1, killed %11, 2
%14 = REG_SEQUENCE killed %5, 17, %13, 18 %14 = REG_SEQUENCE killed %5, 17, %13, 18
%15 = S_MOV_B32 2 %15 = S_MOV_B32 2
%29 = V_LSHL_B64 killed %28, killed %15, implicit $exec %29 = V_LSHL_B64 killed %28, killed %15, implicit $exec
%17 = REG_SEQUENCE killed %6, 17, %13, 18 %17 = REG_SEQUENCE killed %6, 17, %13, 18
%18 = REG_SEQUENCE killed %4, 17, %13, 18 %18 = REG_SEQUENCE killed %4, 17, %13, 18
%20 = COPY %29 %20 = COPY %29
%19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, implicit $exec %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, 0, implicit $exec
%22 = COPY %29 %22 = COPY %29
%21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, implicit $exec %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, 0, implicit $exec
%23 = V_MOV_B32_e32 1090519040, implicit $exec %23 = V_MOV_B32_e32 1090519040, implicit $exec
%24 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 0, 2, implicit $exec %24 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 0, 2, implicit $exec
%26 = COPY %29 %26 = COPY %29
BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN: name: no_fold_imm_madak_mad_clamp_f32 # GCN: name: no_fold_imm_madak_mad_clamp_f32
# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec # GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec
# GCN: %24:vgpr_32 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $exec # GCN: %24:vgpr_32 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $exec
Show All 34 Linesliveins:
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
- { reg: '$vgpr0', virtual-reg: '%3' } - { reg: '$vgpr0', virtual-reg: '%3' }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
%6 = S_LOAD_DWORDX2_IMM %0, 13, 0 %6 = S_LOAD_DWORDX2_IMM %0, 13, 0, 0
%27 = V_ASHRREV_I32_e32 31, %3, implicit $exec %27 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%28 = REG_SEQUENCE %3, 1, %27, 2 %28 = REG_SEQUENCE %3, 1, %27, 2
%11 = S_MOV_B32 61440 %11 = S_MOV_B32 61440
%12 = S_MOV_B32 0 %12 = S_MOV_B32 0
%13 = REG_SEQUENCE killed %12, 1, killed %11, 2 %13 = REG_SEQUENCE killed %12, 1, killed %11, 2
%14 = REG_SEQUENCE killed %5, 17, %13, 18 %14 = REG_SEQUENCE killed %5, 17, %13, 18
%15 = S_MOV_B32 2 %15 = S_MOV_B32 2
%29 = V_LSHL_B64 killed %28, killed %15, implicit $exec %29 = V_LSHL_B64 killed %28, killed %15, implicit $exec
%17 = REG_SEQUENCE killed %6, 17, %13, 18 %17 = REG_SEQUENCE killed %6, 17, %13, 18
%18 = REG_SEQUENCE killed %4, 17, %13, 18 %18 = REG_SEQUENCE killed %4, 17, %13, 18
%20 = COPY %29 %20 = COPY %29
%19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, implicit $exec %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, 0, implicit $exec
%22 = COPY %29 %22 = COPY %29
%21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, implicit $exec %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, 0, implicit $exec
%23 = V_MOV_B32_e32 1090519040, implicit $exec %23 = V_MOV_B32_e32 1090519040, implicit $exec
%24 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $exec %24 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $exec
%26 = COPY %29 %26 = COPY %29
BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN: name: no_fold_imm_madak_mad_omod_f32 # GCN: name: no_fold_imm_madak_mad_omod_f32
# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec # GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec
# GCN: %24:vgpr_32 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 0, 1, implicit $exec # GCN: %24:vgpr_32 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 0, 1, implicit $exec
Show All 34 Linesliveins:
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
- { reg: '$vgpr0', virtual-reg: '%3' } - { reg: '$vgpr0', virtual-reg: '%3' }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
%6 = S_LOAD_DWORDX2_IMM %0, 13, 0 %6 = S_LOAD_DWORDX2_IMM %0, 13, 0, 0
%27 = V_ASHRREV_I32_e32 31, %3, implicit $exec %27 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%28 = REG_SEQUENCE %3, 1, %27, 2 %28 = REG_SEQUENCE %3, 1, %27, 2
%11 = S_MOV_B32 61440 %11 = S_MOV_B32 61440
%12 = S_MOV_B32 0 %12 = S_MOV_B32 0
%13 = REG_SEQUENCE killed %12, 1, killed %11, 2 %13 = REG_SEQUENCE killed %12, 1, killed %11, 2
%14 = REG_SEQUENCE killed %5, 17, %13, 18 %14 = REG_SEQUENCE killed %5, 17, %13, 18
%15 = S_MOV_B32 2 %15 = S_MOV_B32 2
%29 = V_LSHL_B64 killed %28, killed %15, implicit $exec %29 = V_LSHL_B64 killed %28, killed %15, implicit $exec
%17 = REG_SEQUENCE killed %6, 17, %13, 18 %17 = REG_SEQUENCE killed %6, 17, %13, 18
%18 = REG_SEQUENCE killed %4, 17, %13, 18 %18 = REG_SEQUENCE killed %4, 17, %13, 18
%20 = COPY %29 %20 = COPY %29
%19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, implicit $exec %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, 0, implicit $exec
%22 = COPY %29 %22 = COPY %29
%21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, implicit $exec %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, 0, implicit $exec
%23 = V_MOV_B32_e32 1090519040, implicit $exec %23 = V_MOV_B32_e32 1090519040, implicit $exec
%24 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 0, 1, implicit $exec %24 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 0, 1, implicit $exec
%26 = COPY %29 %26 = COPY %29
BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/fold-multiple.mir

Show All 28 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1 = S_MOV_B32 2 %1 = S_MOV_B32 2
%2 = V_LSHLREV_B32_e64 %1, killed %0, implicit $exec %2 = V_LSHLREV_B32_e64 %1, killed %0, implicit $exec
%3 = S_LSHL_B32 %1, killed %1, implicit-def dead $scc %3 = S_LSHL_B32 %1, killed %1, implicit-def dead $scc
%4 = V_AND_B32_e64 killed %2, killed %3, implicit $exec %4 = V_AND_B32_e64 killed %2, killed %3, implicit $exec
%5 = IMPLICIT_DEF %5 = IMPLICIT_DEF
BUFFER_STORE_DWORD_OFFSET killed %4, killed %5, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed %4, killed %5, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/global-load-store-atomics.mir

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name: global_load_store_atomics name: global_load_store_atomics
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
%1:sgpr_64 = COPY $sgpr0_sgpr1 %1:sgpr_64 = COPY $sgpr0_sgpr1
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%4:sreg_64_xexec = S_LOAD_DWORDX2_IMM %1, 36, 0 :: (dereferenceable invariant load 8 ) %4:sreg_64_xexec = S_LOAD_DWORDX2_IMM %1, 36, 0, 0 :: (dereferenceable invariant load 8 )
%5:sreg_32_xm0 = S_MOV_B32 2 %5:sreg_32_xm0 = S_MOV_B32 2
%6:vgpr_32 = V_LSHLREV_B32_e64 killed %5, %0, implicit $exec %6:vgpr_32 = V_LSHLREV_B32_e64 killed %5, %0, implicit $exec
%7:sreg_32_xm0 = S_MOV_B32 0 %7:sreg_32_xm0 = S_MOV_B32 0
%15:vgpr_32 = V_MOV_B32_e32 0, implicit $exec %15:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%14:vreg_64 = REG_SEQUENCE killed %6, %subreg.sub0, killed %15, %subreg.sub1 %14:vreg_64 = REG_SEQUENCE killed %6, %subreg.sub0, killed %15, %subreg.sub1
%21:sgpr_32 = COPY %4.sub0 %21:sgpr_32 = COPY %4.sub0
%22:vgpr_32 = COPY %14.sub0 %22:vgpr_32 = COPY %14.sub0
%23:sgpr_32 = COPY %4.sub1 %23:sgpr_32 = COPY %4.sub1
%24:vgpr_32 = COPY %14.sub1 %24:vgpr_32 = COPY %14.sub1
%17:vgpr_32, %19:sreg_64_xexec = V_ADD_I32_e64 %21, %22, 0, implicit $exec %17:vgpr_32, %19:sreg_64_xexec = V_ADD_I32_e64 %21, %22, 0, implicit $exec
%25:vgpr_32 = COPY %23 %25:vgpr_32 = COPY %23
%18:vgpr_32, dead %20:sreg_64_xexec = V_ADDC_U32_e64 %25, %24, killed %19, 0, implicit $exec %18:vgpr_32, dead %20:sreg_64_xexec = V_ADDC_U32_e64 %25, %24, killed %19, 0, implicit $exec
%16:vreg_64 = REG_SEQUENCE %17, %subreg.sub0, %18, %subreg.sub1 %16:vreg_64 = REG_SEQUENCE %17, %subreg.sub0, %18, %subreg.sub1
%11:vreg_64 = COPY %16 %11:vreg_64 = COPY %16
%10:vgpr_32 = GLOBAL_LOAD_DWORD %11, 16, 0, 0, implicit $exec :: (load 4) %10:vgpr_32 = GLOBAL_LOAD_DWORD %11, 16, 0, 0, 0, implicit $exec :: (load 4)
GLOBAL_STORE_DWORD %11, %10, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %11, %10, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
%40:vreg_64 = GLOBAL_LOAD_DWORDX2 %11, 16, 0, 0, implicit $exec :: (load 4) %40:vreg_64 = GLOBAL_LOAD_DWORDX2 %11, 16, 0, 0, 0, implicit $exec :: (load 4)
GLOBAL_STORE_DWORDX2 %11, %40, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %11, %40, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
%41:vreg_96 = GLOBAL_LOAD_DWORDX3 %11, 16, 0, 0, implicit $exec :: (load 4) %41:vreg_96 = GLOBAL_LOAD_DWORDX3 %11, 16, 0, 0, 0, implicit $exec :: (load 4)
GLOBAL_STORE_DWORDX3 %11, %41, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX3 %11, %41, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
%42:vreg_128 = GLOBAL_LOAD_DWORDX4 %11, 16, 0, 0, implicit $exec :: (load 4) %42:vreg_128 = GLOBAL_LOAD_DWORDX4 %11, 16, 0, 0, 0, implicit $exec :: (load 4)
GLOBAL_STORE_DWORDX4 %11, %42, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX4 %11, %42, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
%43:vgpr_32 = GLOBAL_LOAD_SSHORT %11, 16, 0, 0, implicit $exec :: (load 4) %43:vgpr_32 = GLOBAL_LOAD_SSHORT %11, 16, 0, 0, 0, implicit $exec :: (load 4)
GLOBAL_STORE_SHORT %11, %43, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_SHORT %11, %43, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
%44:vgpr_32 = GLOBAL_LOAD_USHORT %11, 16, 0, 0, implicit $exec :: (load 4) %44:vgpr_32 = GLOBAL_LOAD_USHORT %11, 16, 0, 0, 0, implicit $exec :: (load 4)
GLOBAL_STORE_SHORT %11, %44, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_SHORT %11, %44, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
%45:vgpr_32 = GLOBAL_LOAD_UBYTE %11, 16, 0, 0, implicit $exec :: (load 4) %45:vgpr_32 = GLOBAL_LOAD_UBYTE %11, 16, 0, 0, 0, implicit $exec :: (load 4)
GLOBAL_STORE_BYTE %11, %45, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_BYTE %11, %45, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
%46:vgpr_32 = GLOBAL_LOAD_SBYTE %11, 16, 0, 0, implicit $exec :: (load 4) %46:vgpr_32 = GLOBAL_LOAD_SBYTE %11, 16, 0, 0, 0, implicit $exec :: (load 4)
GLOBAL_STORE_BYTE %11, %46, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_BYTE %11, %46, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
%47:vgpr_32 = GLOBAL_LOAD_SBYTE_D16 %11, 16, 0, 0, %46, implicit $exec :: (load 4) %47:vgpr_32 = GLOBAL_LOAD_SBYTE_D16 %11, 16, 0, 0, 0, %46, implicit $exec :: (load 4)
GLOBAL_STORE_BYTE_D16_HI %11, %47, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_BYTE_D16_HI %11, %47, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
%48:vgpr_32 = GLOBAL_LOAD_UBYTE_D16 %11, 16, 0, 0, %46, implicit $exec :: (load 4) %48:vgpr_32 = GLOBAL_LOAD_UBYTE_D16 %11, 16, 0, 0, 0, %46, implicit $exec :: (load 4)
GLOBAL_STORE_BYTE_D16_HI %11, %48, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_BYTE_D16_HI %11, %48, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
%49:vgpr_32 = GLOBAL_LOAD_SBYTE_D16_HI %11, 16, 0, 0, %46, implicit $exec :: (load 4) %49:vgpr_32 = GLOBAL_LOAD_SBYTE_D16_HI %11, 16, 0, 0, 0, %46, implicit $exec :: (load 4)
GLOBAL_STORE_BYTE_D16_HI %11, %49, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_BYTE_D16_HI %11, %49, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
%50:vgpr_32 = GLOBAL_LOAD_UBYTE_D16_HI %11, 16, 0, 0, %46, implicit $exec :: (load 4) %50:vgpr_32 = GLOBAL_LOAD_UBYTE_D16_HI %11, 16, 0, 0, 0, %46, implicit $exec :: (load 4)
GLOBAL_STORE_BYTE_D16_HI %11, %50, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_BYTE_D16_HI %11, %50, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
%51:vgpr_32 = GLOBAL_LOAD_SHORT_D16_HI %11, 16, 0, 0, %46, implicit $exec :: (load 4) %51:vgpr_32 = GLOBAL_LOAD_SHORT_D16_HI %11, 16, 0, 0, 0, %46, implicit $exec :: (load 4)
GLOBAL_STORE_SHORT_D16_HI %11, %51, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_SHORT_D16_HI %11, %51, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
%52:vgpr_32 = GLOBAL_LOAD_SHORT_D16 %11, 16, 0, 0, %46, implicit $exec :: (load 4) %52:vgpr_32 = GLOBAL_LOAD_SHORT_D16 %11, 16, 0, 0, 0, %46, implicit $exec :: (load 4)
GLOBAL_STORE_SHORT_D16_HI %11, %52, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_SHORT_D16_HI %11, %52, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
%53:vgpr_32 = GLOBAL_ATOMIC_XOR_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %53:vgpr_32 = GLOBAL_ATOMIC_XOR_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORD %11, %53, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %11, %53, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_XOR %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_XOR %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%54:vgpr_32 = GLOBAL_ATOMIC_SMIN_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %54:vgpr_32 = GLOBAL_ATOMIC_SMIN_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORD %11, %54, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %11, %54, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_SMIN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_SMIN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%55:vgpr_32 = GLOBAL_ATOMIC_AND_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %55:vgpr_32 = GLOBAL_ATOMIC_AND_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORD %11, %55, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %11, %55, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_AND %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_AND %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%56:vgpr_32 = GLOBAL_ATOMIC_SWAP_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %56:vgpr_32 = GLOBAL_ATOMIC_SWAP_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORD %11, %56, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %11, %56, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_SWAP %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_SWAP %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%57:vgpr_32 = GLOBAL_ATOMIC_SMAX_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %57:vgpr_32 = GLOBAL_ATOMIC_SMAX_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORD %11, %57, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %11, %57, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_SMAX %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_SMAX %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%58:vgpr_32 = GLOBAL_ATOMIC_UMIN_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %58:vgpr_32 = GLOBAL_ATOMIC_UMIN_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORD %11, %58, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %11, %58, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_UMIN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_UMIN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%59:vgpr_32 = GLOBAL_ATOMIC_UMAX_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %59:vgpr_32 = GLOBAL_ATOMIC_UMAX_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORD %11, %59, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %11, %59, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_UMAX %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_UMAX %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%60:vgpr_32 = GLOBAL_ATOMIC_OR_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %60:vgpr_32 = GLOBAL_ATOMIC_OR_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORD %11, %60, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %11, %60, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_OR %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_OR %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%61:vgpr_32 = GLOBAL_ATOMIC_ADD_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %61:vgpr_32 = GLOBAL_ATOMIC_ADD_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORD %11, %61, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %11, %61, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_ADD %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_ADD %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%62:vgpr_32 = GLOBAL_ATOMIC_SUB_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %62:vgpr_32 = GLOBAL_ATOMIC_SUB_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORD %11, %62, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %11, %62, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_SUB %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_SUB %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%63:vgpr_32 = GLOBAL_ATOMIC_CMPSWAP_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %63:vgpr_32 = GLOBAL_ATOMIC_CMPSWAP_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORD %11, %63, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %11, %63, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_CMPSWAP %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_CMPSWAP %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%64:vgpr_32 = GLOBAL_ATOMIC_INC_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %64:vgpr_32 = GLOBAL_ATOMIC_INC_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORD %11, %64, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %11, %64, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_INC %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_INC %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%65:vgpr_32 = GLOBAL_ATOMIC_DEC_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %65:vgpr_32 = GLOBAL_ATOMIC_DEC_RTN %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORD %11, %65, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORD %11, %65, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_DEC %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_DEC %11, %15, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%66:vreg_64 = GLOBAL_ATOMIC_OR_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %66:vreg_64 = GLOBAL_ATOMIC_OR_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORDX2 %11, %66, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %11, %66, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_OR_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_OR_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%67:vreg_64 = GLOBAL_ATOMIC_XOR_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %67:vreg_64 = GLOBAL_ATOMIC_XOR_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORDX2 %11, %67, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %11, %67, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_XOR_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_XOR_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%68:vreg_64 = GLOBAL_ATOMIC_AND_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %68:vreg_64 = GLOBAL_ATOMIC_AND_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORDX2 %11, %68, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %11, %68, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_AND_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_AND_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%69:vreg_64 = GLOBAL_ATOMIC_ADD_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %69:vreg_64 = GLOBAL_ATOMIC_ADD_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORDX2 %11, %69, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %11, %69, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_ADD_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_ADD_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%70:vreg_64 = GLOBAL_ATOMIC_SUB_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %70:vreg_64 = GLOBAL_ATOMIC_SUB_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORDX2 %11, %70, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %11, %70, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_SUB_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_SUB_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%71:vreg_64 = GLOBAL_ATOMIC_DEC_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %71:vreg_64 = GLOBAL_ATOMIC_DEC_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORDX2 %11, %71, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %11, %71, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_DEC_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_DEC_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%72:vreg_64 = GLOBAL_ATOMIC_INC_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %72:vreg_64 = GLOBAL_ATOMIC_INC_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORDX2 %11, %72, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %11, %72, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_INC_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_INC_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%73:vreg_64 = GLOBAL_ATOMIC_SMIN_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %73:vreg_64 = GLOBAL_ATOMIC_SMIN_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORDX2 %11, %73, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %11, %73, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_SMIN_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_SMIN_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%74:vreg_64 = GLOBAL_ATOMIC_SWAP_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %74:vreg_64 = GLOBAL_ATOMIC_SWAP_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORDX2 %11, %74, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %11, %74, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_SWAP_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_SWAP_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%75:vreg_64 = GLOBAL_ATOMIC_SMAX_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %75:vreg_64 = GLOBAL_ATOMIC_SMAX_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORDX2 %11, %75, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %11, %75, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_SMAX_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_SMAX_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%76:vreg_64 = GLOBAL_ATOMIC_UMIN_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %76:vreg_64 = GLOBAL_ATOMIC_UMIN_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORDX2 %11, %76, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %11, %76, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_UMIN_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_UMIN_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%77:vreg_64 = GLOBAL_ATOMIC_UMAX_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %77:vreg_64 = GLOBAL_ATOMIC_UMAX_X2_RTN %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORDX2 %11, %77, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %11, %77, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_UMAX_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_UMAX_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
%79:sreg_128 = REG_SEQUENCE %4, %subreg.sub0, %4, %subreg.sub1, %4, %subreg.sub2, %4, %subreg.sub3 %79:sreg_128 = REG_SEQUENCE %4, %subreg.sub0, %4, %subreg.sub1, %4, %subreg.sub2, %4, %subreg.sub3
%80:vreg_128 = COPY %79 %80:vreg_128 = COPY %79
%78:vreg_64 = GLOBAL_ATOMIC_CMPSWAP_X2_RTN %11, %80, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) %78:vreg_64 = GLOBAL_ATOMIC_CMPSWAP_X2_RTN %11, %80, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
GLOBAL_STORE_DWORDX2 %11, %78, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) GLOBAL_STORE_DWORDX2 %11, %78, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
GLOBAL_ATOMIC_CMPSWAP_X2 %11, %80, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1) GLOBAL_ATOMIC_CMPSWAP_X2 %11, %80, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir

# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s # RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
# GCN-LABEL: name: hazard_buffer_store_v_interp # GCN-LABEL: name: hazard_buffer_store_v_interp
# GCN: bb.0.entry: # GCN: bb.0.entry:
# GCN-NEXT: BUFFER_STORE_DWORDX4_OFFSET_exact # GCN-NEXT: BUFFER_STORE_DWORDX4_OFFSET_exact
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: V_INTERP_P1_F32 # GCN-NEXT: V_INTERP_P1_F32
name: hazard_buffer_store_v_interp name: hazard_buffer_store_v_interp
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr7, $vgpr8, $vgpr9, $vgpr10 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr7, $vgpr8, $vgpr9, $vgpr10
BUFFER_STORE_DWORDX4_OFFSET_exact killed $vgpr7_vgpr8_vgpr9_vgpr10, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 96, 0, 0, 0, implicit $exec BUFFER_STORE_DWORDX4_OFFSET_exact killed $vgpr7_vgpr8_vgpr9_vgpr10, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 96, 0, 0, 0, 0, implicit $exec
$vgpr7 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $m0, implicit $exec $vgpr7 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $m0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/hazard-inlineasm.mir

Show All 10 Lines
# CHECK-NEXT: S_NOP 0 # CHECK-NEXT: S_NOP 0
# CHECK-NEXT: INLINEASM # CHECK-NEXT: INLINEASM
--- ---
name: hazard-inlineasm name: hazard-inlineasm
body: | body: |
bb.0: bb.0:
FLAT_STORE_DWORDX4 $vgpr49_vgpr50, $vgpr26_vgpr27_vgpr28_vgpr29, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORDX4 $vgpr49_vgpr50, $vgpr26_vgpr27_vgpr28_vgpr29, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
INLINEASM &"v_mad_u64_u32 $0, $1, $2, $3, $4", 0, 2621450, def $vgpr26_vgpr27, 2818058, def dead $sgpr14_sgpr15, 589833, $sgpr12, 327689, killed $vgpr51, 2621449, $vgpr46_vgpr47 INLINEASM &"v_mad_u64_u32 $0, $1, $2, $3, $4", 0, 2621450, def $vgpr26_vgpr27, 2818058, def dead $sgpr14_sgpr15, 589833, $sgpr12, 327689, killed $vgpr51, 2621449, $vgpr46_vgpr47
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/hazard-kill.mir

Show All 15 Lines
# GFX90-NEXT: V_INTERP_MOV_F32 # GFX90-NEXT: V_INTERP_MOV_F32
name: _amdgpu_ps_main name: _amdgpu_ps_main
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr2, $sgpr3, $sgpr4 liveins: $sgpr2, $sgpr3, $sgpr4
$sgpr6 = S_MOV_B32 killed $sgpr3 $sgpr6 = S_MOV_B32 killed $sgpr3
renamable $sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX4_IMM renamable $sgpr6_sgpr7, 16, 0 renamable $sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX4_IMM renamable $sgpr6_sgpr7, 16, 0, 0
$m0 = S_MOV_B32 killed renamable $sgpr4 $m0 = S_MOV_B32 killed renamable $sgpr4
dead renamable $sgpr0 = KILL undef renamable $sgpr2 dead renamable $sgpr0 = KILL undef renamable $sgpr2
renamable $vgpr0 = V_INTERP_MOV_F32 2, 0, 0, implicit $m0, implicit $exec renamable $vgpr0 = V_INTERP_MOV_F32 2, 0, 0, implicit $m0, implicit $exec
renamable $sgpr0 = S_MOV_B32 0 renamable $sgpr0 = S_MOV_B32 0
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-term.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -O0 -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs -stop-after=regallocfast < %s | FileCheck -check-prefixes=GCN %s ; RUN: llc -O0 -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs -stop-after=regallocfast < %s | FileCheck -check-prefixes=GCN %s
; Verify that we consider the xor at the end of the waterfall loop emitted for ; Verify that we consider the xor at the end of the waterfall loop emitted for
; divergent indirect addressing as a terminator. ; divergent indirect addressing as a terminator.
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
; There should be no spill code inserted between the xor and the real terminator ; There should be no spill code inserted between the xor and the real terminator
define amdgpu_kernel void @extract_w_offset_vgpr(i32 addrspace(1)* %out) { define amdgpu_kernel void @extract_w_offset_vgpr(i32 addrspace(1)* %out) {
; GCN-LABEL: name: extract_w_offset_vgpr ; GCN-LABEL: name: extract_w_offset_vgpr
; GCN: bb.0.entry: ; GCN: bb.0.entry:
; GCN: successors: %bb.1(0x80000000) ; GCN: successors: %bb.1(0x80000000)
; GCN: liveins: $vgpr0, $sgpr0_sgpr1 ; GCN: liveins: $vgpr0, $sgpr0_sgpr1
; GCN: renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed renamable $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 8 from %ir.out.kernarg.offset.cast, align 4, addrspace 4) ; GCN: renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed renamable $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 8 from %ir.out.kernarg.offset.cast, align 4, addrspace 4)
; GCN: renamable $sgpr2 = COPY renamable $sgpr1 ; GCN: renamable $sgpr2 = COPY renamable $sgpr1
; GCN: renamable $sgpr4 = COPY renamable $sgpr0, implicit killed $sgpr0_sgpr1 ; GCN: renamable $sgpr4 = COPY renamable $sgpr0, implicit killed $sgpr0_sgpr1
; GCN: renamable $sgpr5 = S_MOV_B32 61440 ; GCN: renamable $sgpr5 = S_MOV_B32 61440
; GCN: renamable $sgpr6 = S_MOV_B32 -1 ; GCN: renamable $sgpr6 = S_MOV_B32 -1
; GCN: undef renamable $sgpr8 = COPY killed renamable $sgpr4, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 ; GCN: undef renamable $sgpr8 = COPY killed renamable $sgpr4, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
; GCN: renamable $sgpr9 = COPY killed renamable $sgpr2 ; GCN: renamable $sgpr9 = COPY killed renamable $sgpr2
; GCN: renamable $sgpr10 = COPY killed renamable $sgpr6 ; GCN: renamable $sgpr10 = COPY killed renamable $sgpr6
; GCN: renamable $sgpr11 = COPY killed renamable $sgpr5 ; GCN: renamable $sgpr11 = COPY killed renamable $sgpr5
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @extract_w_offset_vgpr(i32 addrspace(1)* %out) {
; GCN: SI_SPILL_V32_SAVE killed $vgpr18, %stack.8, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr3, 0, implicit $exec :: (store 4 into %stack.8, addrspace 5) ; GCN: SI_SPILL_V32_SAVE killed $vgpr18, %stack.8, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr3, 0, implicit $exec :: (store 4 into %stack.8, addrspace 5)
; GCN: $exec = S_XOR_B64_term $exec, killed renamable $sgpr4_sgpr5, implicit-def $scc ; GCN: $exec = S_XOR_B64_term $exec, killed renamable $sgpr4_sgpr5, implicit-def $scc
; GCN: S_CBRANCH_EXECNZ %bb.1, implicit $exec ; GCN: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; GCN: bb.2: ; GCN: bb.2:
; GCN: $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.3, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr3, implicit-def dead $m0 :: (load 8 from %stack.3, align 4, addrspace 5) ; GCN: $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.3, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr3, implicit-def dead $m0 :: (load 8 from %stack.3, align 4, addrspace 5)
; GCN: $exec = S_MOV_B64 killed renamable $sgpr0_sgpr1 ; GCN: $exec = S_MOV_B64 killed renamable $sgpr0_sgpr1
; GCN: $vgpr0 = SI_SPILL_V32_RESTORE %stack.8, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr3, 0, implicit $exec :: (load 4 from %stack.8, addrspace 5) ; GCN: $vgpr0 = SI_SPILL_V32_RESTORE %stack.8, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr3, 0, implicit $exec :: (load 4 from %stack.8, addrspace 5)
; GCN: $sgpr4_sgpr5_sgpr6_sgpr7 = SI_SPILL_S128_RESTORE %stack.1, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr3, implicit-def dead $m0 :: (load 16 from %stack.1, align 4, addrspace 5) ; GCN: $sgpr4_sgpr5_sgpr6_sgpr7 = SI_SPILL_S128_RESTORE %stack.1, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr3, implicit-def dead $m0 :: (load 16 from %stack.1, align 4, addrspace 5)
; GCN: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr0, killed renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out.load, addrspace 1) ; GCN: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr0, killed renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out.load, addrspace 1)
; GCN: S_ENDPGM ; GCN: S_ENDPGM
entry: entry:
%id = call i32 @llvm.amdgcn.workitem.id.x() #1 %id = call i32 @llvm.amdgcn.workitem.id.x() #1
%index = add i32 %id, 1 %index = add i32 %id, 1
%value = extractelement <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>, i32 %index %value = extractelement <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>, i32 %index
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }

llvm/trunk/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 LinesframeInfo:
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.2): bb.0 (%ir-block.2):
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`) $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
$vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`) $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
$vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`) $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
$vgpr3 = BUFFER_LOAD_DWORD_OFFSET killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`) $vgpr3 = BUFFER_LOAD_DWORD_OFFSET killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
EXP_DONE 0, killed $vgpr0, killed $vgpr1, killed $vgpr2, killed $vgpr3, -1, -1, 15, implicit $exec EXP_DONE 0, killed $vgpr0, killed $vgpr1, killed $vgpr2, killed $vgpr3, -1, -1, 15, implicit $exec
$vgpr0 = V_MOV_B32_e32 1056964608, implicit $exec $vgpr0 = V_MOV_B32_e32 1056964608, implicit $exec
$vgpr1 = V_MOV_B32_e32 1065353216, implicit $exec $vgpr1 = V_MOV_B32_e32 1065353216, implicit $exec
$vgpr2 = V_MOV_B32_e32 1073741824, implicit $exec $vgpr2 = V_MOV_B32_e32 1073741824, implicit $exec
$vgpr3 = V_MOV_B32_e32 1082130432, implicit $exec $vgpr3 = V_MOV_B32_e32 1082130432, implicit $exec
SI_RETURN_TO_EPILOG killed $vgpr0, killed $vgpr1, killed $vgpr2, killed $vgpr3 SI_RETURN_TO_EPILOG killed $vgpr0, killed $vgpr1, killed $vgpr2, killed $vgpr3
... ...

llvm/trunk/test/CodeGen/AMDGPU/inserted-wait-states.mir

Show First 20 Lines • Show All 224 Lines • ▼ Show 20 Lines
# GCN: FLAT_ATOMIC_FCMPSWAP_X2 # GCN: FLAT_ATOMIC_FCMPSWAP_X2
# CIVI: S_NOP # CIVI: S_NOP
# GCN: V_MOV_B32 # GCN: V_MOV_B32
name: vmem_gt_8dw_store name: vmem_gt_8dw_store
body: | body: |
bb.0: bb.0:
BUFFER_STORE_DWORD_OFFSET $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
$vgpr3 = V_MOV_B32_e32 0, implicit $exec $vgpr3 = V_MOV_B32_e32 0, implicit $exec
BUFFER_STORE_DWORDX3_OFFSET $vgpr2_vgpr3_vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORDX3_OFFSET $vgpr2_vgpr3_vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
$vgpr3 = V_MOV_B32_e32 0, implicit $exec $vgpr3 = V_MOV_B32_e32 0, implicit $exec
BUFFER_STORE_DWORDX4_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORDX4_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
$vgpr3 = V_MOV_B32_e32 0, implicit $exec $vgpr3 = V_MOV_B32_e32 0, implicit $exec
BUFFER_STORE_DWORDX4_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORDX4_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
$vgpr3 = V_MOV_B32_e32 0, implicit $exec $vgpr3 = V_MOV_B32_e32 0, implicit $exec
BUFFER_STORE_FORMAT_XYZ_OFFSET $vgpr2_vgpr3_vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_FORMAT_XYZ_OFFSET $vgpr2_vgpr3_vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
$vgpr3 = V_MOV_B32_e32 0, implicit $exec $vgpr3 = V_MOV_B32_e32 0, implicit $exec
BUFFER_STORE_FORMAT_XYZW_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_FORMAT_XYZW_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
$vgpr3 = V_MOV_B32_e32 0, implicit $exec $vgpr3 = V_MOV_B32_e32 0, implicit $exec
BUFFER_ATOMIC_CMPSWAP_X2_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, implicit $exec BUFFER_ATOMIC_CMPSWAP_X2_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, implicit $exec
$vgpr3 = V_MOV_B32_e32 0, implicit $exec $vgpr3 = V_MOV_B32_e32 0, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
FLAT_STORE_DWORDX2 $vgpr0_vgpr1, $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORDX2 $vgpr0_vgpr1, $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr3 = V_MOV_B32_e32 0, implicit $exec $vgpr3 = V_MOV_B32_e32 0, implicit $exec
FLAT_STORE_DWORDX3 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORDX3 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr3 = V_MOV_B32_e32 0, implicit $exec $vgpr3 = V_MOV_B32_e32 0, implicit $exec
FLAT_STORE_DWORDX4 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORDX4 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr3 = V_MOV_B32_e32 0, implicit $exec $vgpr3 = V_MOV_B32_e32 0, implicit $exec
FLAT_ATOMIC_CMPSWAP_X2 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec, implicit $flat_scr FLAT_ATOMIC_CMPSWAP_X2 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec, implicit $flat_scr
$vgpr3 = V_MOV_B32_e32 0, implicit $exec $vgpr3 = V_MOV_B32_e32 0, implicit $exec
FLAT_ATOMIC_FCMPSWAP_X2 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec, implicit $flat_scr FLAT_ATOMIC_FCMPSWAP_X2 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec, implicit $flat_scr
$vgpr3 = V_MOV_B32_e32 0, implicit $exec $vgpr3 = V_MOV_B32_e32 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
▲ Show 20 Lines • Show All 281 Lines • ▼ Show 20 Linesstack:
- { id: 1, offset: 8, size: 4, alignment: 4 } - { id: 1, offset: 8, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr9, $sgpr0_sgpr1_sgpr2_sgpr3 liveins: $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr9, $sgpr0_sgpr1_sgpr2_sgpr3
$flat_scr_lo = S_ADD_U32 $sgpr6, $sgpr9, implicit-def $scc $flat_scr_lo = S_ADD_U32 $sgpr6, $sgpr9, implicit-def $scc
$flat_scr_hi = S_ADDC_U32 $sgpr7, 0, implicit-def $scc, implicit $scc $flat_scr_hi = S_ADDC_U32 $sgpr7, 0, implicit-def $scc, implicit $scc
DBG_VALUE $noreg, 2, !5, !11, debug-location !12 DBG_VALUE $noreg, 2, !5, !11, debug-location !12
$sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr4_sgpr5, 0, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
dead $sgpr6_sgpr7 = KILL $sgpr4_sgpr5 dead $sgpr6_sgpr7 = KILL $sgpr4_sgpr5
$sgpr8 = S_MOV_B32 $sgpr5 $sgpr8 = S_MOV_B32 $sgpr5
$vgpr0 = V_MOV_B32_e32 killed $sgpr8, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr8, implicit $exec
BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9, 4, 0, 0, 0, implicit $exec :: (store 4 into %ir.A.addr + 4) BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9, 4, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.A.addr + 4)
$sgpr8 = S_MOV_B32 $sgpr4, implicit killed $sgpr4_sgpr5 $sgpr8 = S_MOV_B32 $sgpr4, implicit killed $sgpr4_sgpr5
$vgpr0 = V_MOV_B32_e32 killed $sgpr8, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr8, implicit $exec
BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.A.addr) BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.A.addr)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 LinesframeInfo:
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 11, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc
bb.1.else: bb.1.else:
liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
$vgpr0 = V_MOV_B32_e32 100, implicit $exec $vgpr0 = V_MOV_B32_e32 100, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`) BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
$vgpr0 = V_MOV_B32_e32 1, implicit $exec $vgpr0 = V_MOV_B32_e32 1, implicit $exec
S_BRANCH %bb.3 S_BRANCH %bb.3
bb.2.if: bb.2.if:
liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
$vgpr0 = V_MOV_B32_e32 9, implicit $exec $vgpr0 = V_MOV_B32_e32 9, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`) BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
$vgpr0 = V_MOV_B32_e32 0, implicit $exec $vgpr0 = V_MOV_B32_e32 0, implicit $exec
bb.3.done: bb.3.done:
liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out) BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/limit-coalesce.mir

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $sgpr0, $vgpr0_vgpr1 liveins: $sgpr0, $vgpr0_vgpr1
%3 = IMPLICIT_DEF %3 = IMPLICIT_DEF
undef %4.sub0 = COPY $sgpr0 undef %4.sub0 = COPY $sgpr0
%4.sub1 = COPY %3.sub0 %4.sub1 = COPY %3.sub0
undef %5.sub0 = COPY %4.sub1 undef %5.sub0 = COPY %4.sub1
%5.sub1 = COPY %4.sub0 %5.sub1 = COPY %4.sub0
FLAT_STORE_DWORDX2 $vgpr0_vgpr1, killed %5, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORDX2 $vgpr0_vgpr1, killed %5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%6 = IMPLICIT_DEF %6 = IMPLICIT_DEF
undef %7.sub0_sub1 = COPY %6 undef %7.sub0_sub1 = COPY %6
%7.sub2 = COPY %3.sub0 %7.sub2 = COPY %3.sub0
FLAT_STORE_DWORDX3 $vgpr0_vgpr1, killed %7, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORDX3 $vgpr0_vgpr1, killed %7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%8 = IMPLICIT_DEF %8 = IMPLICIT_DEF
undef %9.sub0_sub1_sub2 = COPY %8 undef %9.sub0_sub1_sub2 = COPY %8
%9.sub3 = COPY %3.sub0 %9.sub3 = COPY %3.sub0
FLAT_STORE_DWORDX4 $vgpr0_vgpr1, killed %9, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORDX4 $vgpr0_vgpr1, killed %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
... ...

llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.get.waveid.in.workgroup.ll

; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
declare i32 @llvm.amdgcn.s.get.waveid.in.workgroup() #0
; GCN-LABEL: {{^}}test_s_get_waveid_in_workgroup:
; GFX10: global_store_dword
; GFX10: s_get_waveid_in_workgroup [[DEST:s[0-9]+]]
; GFX10: s_waitcnt lgkmcnt(0)
; GFX10: v_mov_b32_e32 [[VDEST:v[0-9]+]], [[DEST]]
; GFX10: global_store_dword v[{{[0-9:]+}}], [[VDEST]], off
define amdgpu_kernel void @test_s_get_waveid_in_workgroup(i32 addrspace(1)* %out) {
; Make sure %out is loaded and assiciated wait count already inserted
store i32 0, i32 addrspace(1)* %out
%v = call i32 @llvm.amdgcn.s.get.waveid.in.workgroup()
store i32 %v, i32 addrspace(1)* %out
ret void
}
attributes #0 = { nounwind }

llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 LinesframeInfo:
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
successors: %bb.1.atomic(0x40000000), %bb.2.exit(0x40000000) successors: %bb.1.atomic(0x40000000), %bb.2.exit(0x40000000)
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
$sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM $sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM $sgpr0_sgpr1, 11, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
$vgpr1 = V_ASHRREV_I32_e32 31, $vgpr0, implicit $exec $vgpr1 = V_ASHRREV_I32_e32 31, $vgpr0, implicit $exec
$vgpr1_vgpr2 = V_LSHL_B64 $vgpr0_vgpr1, 3, implicit $exec $vgpr1_vgpr2 = V_LSHL_B64 $vgpr0_vgpr1, 3, implicit $exec
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 0 $sgpr6 = S_MOV_B32 0
S_WAITCNT 127 S_WAITCNT 127
$vgpr1_vgpr2 = BUFFER_LOAD_DWORDX2_ADDR64 killed $vgpr1_vgpr2, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 8 from %ir.tid.gep) $vgpr1_vgpr2 = BUFFER_LOAD_DWORDX2_ADDR64 killed $vgpr1_vgpr2, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 8 from %ir.tid.gep)
$vgpr0 = V_XOR_B32_e32 1, killed $vgpr0, implicit $exec $vgpr0 = V_XOR_B32_e32 1, killed $vgpr0, implicit $exec
V_CMP_NE_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec V_CMP_NE_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec
$sgpr2_sgpr3 = S_AND_SAVEEXEC_B64 killed $vcc, implicit-def $exec, implicit-def $scc, implicit $exec $sgpr2_sgpr3 = S_AND_SAVEEXEC_B64 killed $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
$sgpr2_sgpr3 = S_XOR_B64 $exec, killed $sgpr2_sgpr3, implicit-def dead $scc $sgpr2_sgpr3 = S_XOR_B64 $exec, killed $sgpr2_sgpr3, implicit-def dead $scc
SI_MASK_BRANCH %bb.2.exit, implicit $exec SI_MASK_BRANCH %bb.2.exit, implicit $exec
bb.1.atomic: bb.1.atomic:
successors: %bb.2.exit(0x80000000) successors: %bb.2.exit(0x80000000)
liveins: $sgpr4_sgpr5_sgpr6_sgpr7:0x0000000C, $sgpr0_sgpr1, $sgpr2_sgpr3, $vgpr1_vgpr2_vgpr3_vgpr4:0x00000003 liveins: $sgpr4_sgpr5_sgpr6_sgpr7:0x0000000C, $sgpr0_sgpr1, $sgpr2_sgpr3, $vgpr1_vgpr2_vgpr3_vgpr4:0x00000003
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 15, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 15, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
dead $vgpr0 = V_MOV_B32_e32 -1, implicit $exec dead $vgpr0 = V_MOV_B32_e32 -1, implicit $exec
dead $vgpr0 = V_MOV_B32_e32 61440, implicit $exec dead $vgpr0 = V_MOV_B32_e32 61440, implicit $exec
$sgpr4_sgpr5 = S_MOV_B64 0 $sgpr4_sgpr5 = S_MOV_B64 0
S_WAITCNT 127 S_WAITCNT 127
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
S_WAITCNT 3952 S_WAITCNT 3952
BUFFER_ATOMIC_SMAX_ADDR64 killed $vgpr0, killed $vgpr1_vgpr2, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 400, 0, implicit $exec :: (volatile load syncscope("one-as") seq_cst 4 from %ir.gep) BUFFER_ATOMIC_SMAX_ADDR64 killed $vgpr0, killed $vgpr1_vgpr2, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 400, 0, implicit $exec :: (volatile load syncscope("one-as") seq_cst 4 from %ir.gep)
bb.2.exit: bb.2.exit:
liveins: $sgpr2_sgpr3 liveins: $sgpr2_sgpr3
$exec = S_OR_B64 $exec, killed $sgpr2_sgpr3, implicit-def $scc $exec = S_OR_B64 $exec, killed $sgpr2_sgpr3, implicit-def $scc
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir

# RUN: not llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - 2>&1 | FileCheck -check-prefix=GCN %s # RUN: not llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - 2>&1 | FileCheck -check-prefix=GCN %s
--- ---
# GCN: error: <unknown>:0:0: in function invalid_load void (): Unsupported atomic address space # GCN: error: <unknown>:0:0: in function invalid_load void (): Unsupported atomic address space
name: invalid_load name: invalid_load
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr2_sgpr3 $vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr2_sgpr3
$vgpr1 = V_MOV_B32_e32 killed $sgpr3, implicit $exec, implicit $sgpr2_sgpr3, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr3, implicit $exec, implicit $sgpr2_sgpr3, implicit $exec
renamable $vgpr2 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load syncscope("one-as") seq_cst 4 from `i32 addrspace(42)* undef`) renamable $vgpr2 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load syncscope("one-as") seq_cst 4 from `i32 addrspace(42)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN: error: <unknown>:0:0: in function invalid_store void (): Unsupported atomic address space # GCN: error: <unknown>:0:0: in function invalid_store void (): Unsupported atomic address space
name: invalid_store name: invalid_store
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$vgpr2 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr2 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile store syncscope("agent-one-as") seq_cst 4 into `i32 addrspace(42)* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile store syncscope("agent-one-as") seq_cst 4 into `i32 addrspace(42)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN: error: <unknown>:0:0: in function invalid_cmpxchg void (): Unsupported atomic address space # GCN: error: <unknown>:0:0: in function invalid_cmpxchg void (): Unsupported atomic address space
name: invalid_cmpxchg name: invalid_cmpxchg
Show All 28 Lines

llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-local.mir

# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck -check-prefix=GCN %s
--- ---
# GCN-LABEL: name: load_singlethread_unordered # GCN-LABEL: name: load_singlethread_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_singlethread_unordered name: load_singlethread_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") unordered 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") unordered 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_singlethread_monotonic # GCN-LABEL: name: load_singlethread_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_singlethread_monotonic name: load_singlethread_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") monotonic 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") monotonic 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_singlethread_acquire # GCN-LABEL: name: load_singlethread_acquire
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_singlethread_acquire name: load_singlethread_acquire
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") acquire 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") acquire 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_singlethread_seq_cst # GCN-LABEL: name: load_singlethread_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_singlethread_seq_cst name: load_singlethread_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") seq_cst 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") seq_cst 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_wavefront_unordered # GCN-LABEL: name: load_wavefront_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_wavefront_unordered name: load_wavefront_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") unordered 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") unordered 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_wavefront_monotonic # GCN-LABEL: name: load_wavefront_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_wavefront_monotonic name: load_wavefront_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") monotonic 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") monotonic 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_wavefront_acquire # GCN-LABEL: name: load_wavefront_acquire
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_wavefront_acquire name: load_wavefront_acquire
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") acquire 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") acquire 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_wavefront_seq_cst # GCN-LABEL: name: load_wavefront_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_wavefront_seq_cst name: load_wavefront_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") seq_cst 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") seq_cst 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_workgroup_unordered # GCN-LABEL: name: load_workgroup_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_workgroup_unordered name: load_workgroup_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") unordered 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") unordered 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_workgroup_monotonic # GCN-LABEL: name: load_workgroup_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_workgroup_monotonic name: load_workgroup_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") monotonic 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") monotonic 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_workgroup_acquire # GCN-LABEL: name: load_workgroup_acquire
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_workgroup_acquire name: load_workgroup_acquire
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") acquire 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") acquire 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_workgroup_seq_cst # GCN-LABEL: name: load_workgroup_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_workgroup_seq_cst name: load_workgroup_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") seq_cst 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") seq_cst 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_agent_unordered # GCN-LABEL: name: load_agent_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_agent_unordered name: load_agent_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") unordered 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") unordered 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_agent_monotonic # GCN-LABEL: name: load_agent_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_agent_monotonic name: load_agent_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") monotonic 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") monotonic 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_agent_acquire # GCN-LABEL: name: load_agent_acquire
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_agent_acquire name: load_agent_acquire
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") acquire 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") acquire 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_agent_seq_cst # GCN-LABEL: name: load_agent_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_agent_seq_cst name: load_agent_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") seq_cst 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") seq_cst 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_system_unordered # GCN-LABEL: name: load_system_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_system_unordered name: load_system_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") unordered 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") unordered 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_system_monotonic # GCN-LABEL: name: load_system_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_system_monotonic name: load_system_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") monotonic 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") monotonic 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_system_acquire # GCN-LABEL: name: load_system_acquire
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_system_acquire name: load_system_acquire
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") acquire 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") acquire 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_system_seq_cst # GCN-LABEL: name: load_system_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_system_seq_cst name: load_system_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") seq_cst 4 from `i32 addrspace(3)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 0, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") seq_cst 4 from `i32 addrspace(3)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_singlethread_unordered # GCN-LABEL: name: store_singlethread_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_singlethread_unordered name: store_singlethread_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") unordered 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") unordered 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_singlethread_monotonic # GCN-LABEL: name: store_singlethread_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_singlethread_monotonic name: store_singlethread_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") monotonic 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") monotonic 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_singlethread_release # GCN-LABEL: name: store_singlethread_release
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_singlethread_release name: store_singlethread_release
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") release 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") release 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_singlethread_seq_cst # GCN-LABEL: name: store_singlethread_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_singlethread_seq_cst name: store_singlethread_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") seq_cst 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") seq_cst 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_wavefront_unordered # GCN-LABEL: name: store_wavefront_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_wavefront_unordered name: store_wavefront_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") unordered 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") unordered 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_wavefront_monotonic # GCN-LABEL: name: store_wavefront_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_wavefront_monotonic name: store_wavefront_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") monotonic 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") monotonic 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_wavefront_release # GCN-LABEL: name: store_wavefront_release
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_wavefront_release name: store_wavefront_release
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") release 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") release 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_wavefront_seq_cst # GCN-LABEL: name: store_wavefront_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_wavefront_seq_cst name: store_wavefront_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") seq_cst 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") seq_cst 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_workgroup_unordered # GCN-LABEL: name: store_workgroup_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_workgroup_unordered name: store_workgroup_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") unordered 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") unordered 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_workgroup_monotonic # GCN-LABEL: name: store_workgroup_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_workgroup_monotonic name: store_workgroup_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") monotonic 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") monotonic 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_workgroup_release # GCN-LABEL: name: store_workgroup_release
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_workgroup_release name: store_workgroup_release
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") release 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") release 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_workgroup_seq_cst # GCN-LABEL: name: store_workgroup_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_workgroup_seq_cst name: store_workgroup_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") seq_cst 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") seq_cst 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_agent_unordered # GCN-LABEL: name: store_agent_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_agent_unordered name: store_agent_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") unordered 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") unordered 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_agent_monotonic # GCN-LABEL: name: store_agent_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_agent_monotonic name: store_agent_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") monotonic 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") monotonic 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_agent_release # GCN-LABEL: name: store_agent_release
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_agent_release name: store_agent_release
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") release 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") release 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_agent_seq_cst # GCN-LABEL: name: store_agent_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_agent_seq_cst name: store_agent_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") seq_cst 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") seq_cst 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_system_unordered # GCN-LABEL: name: store_system_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_system_unordered name: store_system_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("one-as") unordered 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("one-as") unordered 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_system_monotonic # GCN-LABEL: name: store_system_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_system_monotonic name: store_system_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("one-as") monotonic 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("one-as") monotonic 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_system_release # GCN-LABEL: name: store_system_release
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_system_release name: store_system_release
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("one-as") release 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("one-as") release 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_system_seq_cst # GCN-LABEL: name: store_system_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_system_seq_cst name: store_system_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("one-as") seq_cst 4 into `i32 addrspace(3)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("one-as") seq_cst 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: atomicrmw_singlethread_unordered # GCN-LABEL: name: atomicrmw_singlethread_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRXCHG_RTN_B32 # GCN: DS_WRXCHG_RTN_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: atomicrmw_singlethread_unordered name: atomicrmw_singlethread_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
$vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") unordered 4 into `i32 addrspace(3)* undef`) $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") unordered 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: atomicrmw_singlethread_monotonic # GCN-LABEL: name: atomicrmw_singlethread_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRXCHG_RTN_B32 # GCN: DS_WRXCHG_RTN_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: atomicrmw_singlethread_monotonic name: atomicrmw_singlethread_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
$vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") monotonic 4 into `i32 addrspace(3)* undef`) $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") monotonic 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: atomicrmw_singlethread_acquire # GCN-LABEL: name: atomicrmw_singlethread_acquire
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRXCHG_RTN_B32 # GCN: DS_WRXCHG_RTN_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: atomicrmw_singlethread_acquire name: atomicrmw_singlethread_acquire
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
$vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") acquire 4 into `i32 addrspace(3)* undef`) $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") acquire 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: atomicrmw_singlethread_release # GCN-LABEL: name: atomicrmw_singlethread_release
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRXCHG_RTN_B32 # GCN: DS_WRXCHG_RTN_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: atomicrmw_singlethread_release name: atomicrmw_singlethread_release
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
$vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") release 4 into `i32 addrspace(3)* undef`) $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") release 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: atomicrmw_singlethread_acq_rel # GCN-LABEL: name: atomicrmw_singlethread_acq_rel
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRXCHG_RTN_B32 # GCN: DS_WRXCHG_RTN_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: atomicrmw_singlethread_acq_rel name: atomicrmw_singlethread_acq_rel
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
$vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") acq_rel 4 into `i32 addrspace(3)* undef`) $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") acq_rel 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: atomicrmw_singlethread_seq_cst # GCN-LABEL: name: atomicrmw_singlethread_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRXCHG_RTN_B32 # GCN: DS_WRXCHG_RTN_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: atomicrmw_singlethread_seq_cst name: atomicrmw_singlethread_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
$vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") seq_cst 4 into `i32 addrspace(3)* undef`) $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 0, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") seq_cst 4 into `i32 addrspace(3)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir

Show All 10 Lines
# GCN-NEXT: BUFFER_WBINVL1_VOL # GCN-NEXT: BUFFER_WBINVL1_VOL
name: multiple_mem_operands name: multiple_mem_operands
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1(0x30000000), %bb.2(0x50000000) successors: %bb.1(0x30000000), %bb.2(0x50000000)
liveins: $sgpr0_sgpr1, $sgpr3 liveins: $sgpr0_sgpr1, $sgpr3
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 44, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 44, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
$sgpr8 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 $sgpr8 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM $sgpr0_sgpr1, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM $sgpr0_sgpr1, 36, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
$sgpr9 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 $sgpr9 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr10 = S_MOV_B32 4294967295, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 $sgpr10 = S_MOV_B32 4294967295, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr11 = S_MOV_B32 15204352, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 $sgpr11 = S_MOV_B32 15204352, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
$vgpr0 = V_MOV_B32_e32 1, implicit $exec $vgpr0 = V_MOV_B32_e32 1, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 4, 0, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(5)* undef`) BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 4, 0, 0, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(5)* undef`)
S_WAITCNT 127 S_WAITCNT 127
S_CMP_LG_U32 killed $sgpr2, 0, implicit-def $scc S_CMP_LG_U32 killed $sgpr2, 0, implicit-def $scc
S_WAITCNT 3855 S_WAITCNT 3855
$vgpr0 = V_MOV_B32_e32 2, implicit $exec $vgpr0 = V_MOV_B32_e32 2, implicit $exec
$vgpr1 = V_MOV_B32_e32 32772, implicit $exec $vgpr1 = V_MOV_B32_e32 32772, implicit $exec
BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(5)* undef`) BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(5)* undef`)
S_CBRANCH_SCC0 %bb.1, implicit killed $scc S_CBRANCH_SCC0 %bb.1, implicit killed $scc
bb.2: bb.2:
successors: %bb.3(0x80000000) successors: %bb.3(0x80000000)
liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11 liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 52, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 52, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
S_WAITCNT 3855 S_WAITCNT 3855
$vgpr0 = V_MOV_B32_e32 32772, implicit $exec $vgpr0 = V_MOV_B32_e32 32772, implicit $exec
S_BRANCH %bb.3 S_BRANCH %bb.3
bb.1: bb.1:
successors: %bb.3(0x80000000) successors: %bb.3(0x80000000)
liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11 liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 48, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 48, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
S_WAITCNT 3855 S_WAITCNT 3855
$vgpr0 = V_MOV_B32_e32 4, implicit $exec $vgpr0 = V_MOV_B32_e32 4, implicit $exec
bb.3: bb.3:
liveins: $sgpr3, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $sgpr0 liveins: $sgpr3, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $sgpr0
S_WAITCNT 127 S_WAITCNT 127
$sgpr0 = S_LSHL_B32 killed $sgpr0, 2, implicit-def dead $scc $sgpr0 = S_LSHL_B32 killed $sgpr0, 2, implicit-def dead $scc
$vgpr0 = V_ADD_I32_e32 killed $sgpr0, killed $vgpr0, implicit-def dead $vcc, implicit $exec $vgpr0 = V_ADD_I32_e32 killed $sgpr0, killed $vgpr0, implicit-def dead $vcc, implicit $exec
$vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, implicit $exec :: (load syncscope("agent-one-as") unordered 4 from `i32 addrspace(1)* undef`), (load syncscope("workgroup-one-as") seq_cst 4 from `[8192 x i32] addrspace(5)* undef`) $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (load syncscope("agent-one-as") unordered 4 from `i32 addrspace(1)* undef`), (load syncscope("workgroup-one-as") seq_cst 4 from `[8192 x i32] addrspace(5)* undef`)
$vgpr1 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr4_sgpr5 $vgpr1 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr4_sgpr5
$vgpr2 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $sgpr4_sgpr5, implicit $exec $vgpr2 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $sgpr4_sgpr5, implicit $exec
S_WAITCNT 3952 S_WAITCNT 3952
FLAT_STORE_DWORD killed $vgpr1_vgpr2, killed $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32 addrspace(1)* undef`) FLAT_STORE_DWORD killed $vgpr1_vgpr2, killed $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32 addrspace(1)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines--- |
!1 = !{i32 1} !1 = !{i32 1}
... ...
--- ---
# CHECK-LABEL: name: multiple_mem_operands # CHECK-LABEL: name: multiple_mem_operands
# CHECK-LABEL: bb.3.done: # CHECK-LABEL: bb.3.done:
# CHECK: BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 1, 1, 0 # CHECK: BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 1, 1, 0, 0
name: multiple_mem_operands name: multiple_mem_operands
alignment: 0 alignment: 0
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
Show All 31 Lines - { id: 1, name: scratch1, type: default, offset: 32772, size: 32768,
debug-info-variable: '', debug-info-expression: '', debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' } debug-info-location: '' }
constants: constants:
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1.if(0x30000000), %bb.2.else(0x50000000) successors: %bb.1.if(0x30000000), %bb.2.else(0x50000000)
liveins: $sgpr0_sgpr1, $sgpr3 liveins: $sgpr0_sgpr1, $sgpr3
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 44, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 44, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
$sgpr8 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 $sgpr8 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM $sgpr0_sgpr1, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM $sgpr0_sgpr1, 36, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
$sgpr9 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 $sgpr9 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr10 = S_MOV_B32 4294967295, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 $sgpr10 = S_MOV_B32 4294967295, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr11 = S_MOV_B32 15204352, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 $sgpr11 = S_MOV_B32 15204352, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
$vgpr0 = V_MOV_B32_e32 1, implicit $exec $vgpr0 = V_MOV_B32_e32 1, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 4, 0, 0, 0, implicit $exec :: (store 4 into %ir.scratchptr01) BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 4, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.scratchptr01)
S_WAITCNT 127 S_WAITCNT 127
S_CMP_LG_U32 killed $sgpr2, 0, implicit-def $scc S_CMP_LG_U32 killed $sgpr2, 0, implicit-def $scc
S_WAITCNT 3855 S_WAITCNT 3855
$vgpr0 = V_MOV_B32_e32 2, implicit $exec $vgpr0 = V_MOV_B32_e32 2, implicit $exec
$vgpr1 = V_MOV_B32_e32 32772, implicit $exec $vgpr1 = V_MOV_B32_e32 32772, implicit $exec
BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.scratchptr12) BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.scratchptr12)
S_CBRANCH_SCC0 %bb.1.if, implicit killed $scc S_CBRANCH_SCC0 %bb.1.if, implicit killed $scc
bb.2.else: bb.2.else:
successors: %bb.3.done(0x80000000) successors: %bb.3.done(0x80000000)
liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11 liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 52, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 52, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
S_WAITCNT 3855 S_WAITCNT 3855
$vgpr0 = V_MOV_B32_e32 32772, implicit $exec $vgpr0 = V_MOV_B32_e32 32772, implicit $exec
S_BRANCH %bb.3.done S_BRANCH %bb.3.done
bb.1.if: bb.1.if:
successors: %bb.3.done(0x80000000) successors: %bb.3.done(0x80000000)
liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11 liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 48, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 48, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
S_WAITCNT 3855 S_WAITCNT 3855
$vgpr0 = V_MOV_B32_e32 4, implicit $exec $vgpr0 = V_MOV_B32_e32 4, implicit $exec
bb.3.done: bb.3.done:
liveins: $sgpr3, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $sgpr0 liveins: $sgpr3, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $sgpr0
S_WAITCNT 127 S_WAITCNT 127
$sgpr0 = S_LSHL_B32 killed $sgpr0, 2, implicit-def dead $scc $sgpr0 = S_LSHL_B32 killed $sgpr0, 2, implicit-def dead $scc
$vgpr0 = V_ADD_I32_e32 killed $sgpr0, killed $vgpr0, implicit-def dead $vcc, implicit $exec $vgpr0 = V_ADD_I32_e32 killed $sgpr0, killed $vgpr0, implicit-def dead $vcc, implicit $exec
$vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, implicit $exec :: (non-temporal load 4 from %ir.else_ptr), (non-temporal load 4 from %ir.if_ptr) $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (non-temporal load 4 from %ir.else_ptr), (non-temporal load 4 from %ir.if_ptr)
$vgpr1 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr4_sgpr5 $vgpr1 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr4_sgpr5
$vgpr2 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $sgpr4_sgpr5, implicit $exec $vgpr2 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $sgpr4_sgpr5, implicit $exec
S_WAITCNT 3952 S_WAITCNT 3952
FLAT_STORE_DWORD killed $vgpr1_vgpr2, killed $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.out) FLAT_STORE_DWORD killed $vgpr1_vgpr2, killed $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.out)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir

Show All 36 Lines--- |
!1 = !{i32 1} !1 = !{i32 1}
... ...
--- ---
# CHECK-LABEL: name: multiple_mem_operands # CHECK-LABEL: name: multiple_mem_operands
# CHECK-LABEL: bb.3.done: # CHECK-LABEL: bb.3.done:
# CHECK: BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0 # CHECK: BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, 0
name: multiple_mem_operands name: multiple_mem_operands
alignment: 0 alignment: 0
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
Show All 31 Lines - { id: 1, name: scratch1, type: default, offset: 32772, size: 32768,
debug-info-variable: '', debug-info-expression: '', debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' } debug-info-location: '' }
constants: constants:
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1.if(0x30000000), %bb.2.else(0x50000000) successors: %bb.1.if(0x30000000), %bb.2.else(0x50000000)
liveins: $sgpr0_sgpr1, $sgpr3 liveins: $sgpr0_sgpr1, $sgpr3
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 44, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 44, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
$sgpr8 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 $sgpr8 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM $sgpr0_sgpr1, 36, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM $sgpr0_sgpr1, 36, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
$sgpr9 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 $sgpr9 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr10 = S_MOV_B32 4294967295, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 $sgpr10 = S_MOV_B32 4294967295, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr11 = S_MOV_B32 15204352, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11 $sgpr11 = S_MOV_B32 15204352, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
$vgpr0 = V_MOV_B32_e32 1, implicit $exec $vgpr0 = V_MOV_B32_e32 1, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 4, 0, 0, 0, implicit $exec :: (store 4 into %ir.scratchptr01) BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 4, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.scratchptr01)
S_WAITCNT 127 S_WAITCNT 127
S_CMP_LG_U32 killed $sgpr2, 0, implicit-def $scc S_CMP_LG_U32 killed $sgpr2, 0, implicit-def $scc
S_WAITCNT 3855 S_WAITCNT 3855
$vgpr0 = V_MOV_B32_e32 2, implicit $exec $vgpr0 = V_MOV_B32_e32 2, implicit $exec
$vgpr1 = V_MOV_B32_e32 32772, implicit $exec $vgpr1 = V_MOV_B32_e32 32772, implicit $exec
BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.scratchptr12) BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.scratchptr12)
S_CBRANCH_SCC0 %bb.1.if, implicit killed $scc S_CBRANCH_SCC0 %bb.1.if, implicit killed $scc
bb.2.else: bb.2.else:
successors: %bb.3.done(0x80000000) successors: %bb.3.done(0x80000000)
liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11 liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 52, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 52, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
S_WAITCNT 3855 S_WAITCNT 3855
$vgpr0 = V_MOV_B32_e32 32772, implicit $exec $vgpr0 = V_MOV_B32_e32 32772, implicit $exec
S_BRANCH %bb.3.done S_BRANCH %bb.3.done
bb.1.if: bb.1.if:
successors: %bb.3.done(0x80000000) successors: %bb.3.done(0x80000000)
liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11 liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 48, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 48, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
S_WAITCNT 3855 S_WAITCNT 3855
$vgpr0 = V_MOV_B32_e32 4, implicit $exec $vgpr0 = V_MOV_B32_e32 4, implicit $exec
bb.3.done: bb.3.done:
liveins: $sgpr3, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $sgpr0 liveins: $sgpr3, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $sgpr0
S_WAITCNT 127 S_WAITCNT 127
$sgpr0 = S_LSHL_B32 killed $sgpr0, 2, implicit-def dead $scc $sgpr0 = S_LSHL_B32 killed $sgpr0, 2, implicit-def dead $scc
$vgpr0 = V_ADD_I32_e32 killed $sgpr0, killed $vgpr0, implicit-def dead $vcc, implicit $exec $vgpr0 = V_ADD_I32_e32 killed $sgpr0, killed $vgpr0, implicit-def dead $vcc, implicit $exec
$vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, implicit $exec :: (load 4 from %ir.else_ptr), (non-temporal load 4 from %ir.if_ptr) $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %ir.else_ptr), (non-temporal load 4 from %ir.if_ptr)
$vgpr1 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr4_sgpr5 $vgpr1 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr4_sgpr5
$vgpr2 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $sgpr4_sgpr5, implicit $exec $vgpr2 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $sgpr4_sgpr5, implicit $exec
S_WAITCNT 3952 S_WAITCNT 3952
FLAT_STORE_DWORD killed $vgpr1_vgpr2, killed $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.out) FLAT_STORE_DWORD killed $vgpr1_vgpr2, killed $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.out)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-region.mir

# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck -check-prefix=GCN %s
--- ---
# GCN-LABEL: name: load_singlethread_unordered # GCN-LABEL: name: load_singlethread_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_singlethread_unordered name: load_singlethread_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 1, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") unordered 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 1, 0, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") unordered 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_singlethread_monotonic # GCN-LABEL: name: load_singlethread_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_singlethread_monotonic name: load_singlethread_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") monotonic 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") monotonic 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_singlethread_acquire # GCN-LABEL: name: load_singlethread_acquire
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_singlethread_acquire name: load_singlethread_acquire
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") acquire 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") acquire 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_singlethread_seq_cst # GCN-LABEL: name: load_singlethread_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_singlethread_seq_cst name: load_singlethread_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") seq_cst 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("singlethread-one-as") seq_cst 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_wavefront_unordered # GCN-LABEL: name: load_wavefront_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_wavefront_unordered name: load_wavefront_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") unordered 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") unordered 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_wavefront_monotonic # GCN-LABEL: name: load_wavefront_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_wavefront_monotonic name: load_wavefront_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") monotonic 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") monotonic 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_wavefront_acquire # GCN-LABEL: name: load_wavefront_acquire
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_wavefront_acquire name: load_wavefront_acquire
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") acquire 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") acquire 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_wavefront_seq_cst # GCN-LABEL: name: load_wavefront_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_wavefront_seq_cst name: load_wavefront_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") seq_cst 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("wavefront-one-as") seq_cst 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_workgroup_unordered # GCN-LABEL: name: load_workgroup_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_workgroup_unordered name: load_workgroup_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") unordered 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") unordered 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_workgroup_monotonic # GCN-LABEL: name: load_workgroup_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_workgroup_monotonic name: load_workgroup_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") monotonic 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") monotonic 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_workgroup_acquire # GCN-LABEL: name: load_workgroup_acquire
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_workgroup_acquire name: load_workgroup_acquire
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") acquire 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") acquire 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_workgroup_seq_cst # GCN-LABEL: name: load_workgroup_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_workgroup_seq_cst name: load_workgroup_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") seq_cst 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("workgroup-one-as") seq_cst 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_agent_unordered # GCN-LABEL: name: load_agent_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_agent_unordered name: load_agent_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") unordered 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") unordered 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_agent_monotonic # GCN-LABEL: name: load_agent_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_agent_monotonic name: load_agent_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") monotonic 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") monotonic 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_agent_acquire # GCN-LABEL: name: load_agent_acquire
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_agent_acquire name: load_agent_acquire
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") acquire 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") acquire 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_agent_seq_cst # GCN-LABEL: name: load_agent_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_agent_seq_cst name: load_agent_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") seq_cst 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("agent-one-as") seq_cst 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_system_unordered # GCN-LABEL: name: load_system_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_system_unordered name: load_system_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") unordered 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") unordered 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_system_monotonic # GCN-LABEL: name: load_system_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_system_monotonic name: load_system_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") monotonic 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") monotonic 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_system_acquire # GCN-LABEL: name: load_system_acquire
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_system_acquire name: load_system_acquire
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") acquire 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") acquire 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: load_system_seq_cst # GCN-LABEL: name: load_system_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_READ_B32 # GCN: DS_READ_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
name: load_system_seq_cst name: load_system_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 44, 0, 0 :: (dereferenceable invariant load 8 from `i64 addrspace(4)* undef`, align 4, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") seq_cst 4 from `i32 addrspace(2)* undef`) renamable $vgpr2 = DS_READ_B32 killed renamable $vgpr0, 0, 1, implicit $m0, implicit $exec :: (volatile load syncscope("one-as") seq_cst 4 from `i32 addrspace(2)* undef`)
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`) FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_singlethread_unordered # GCN-LABEL: name: store_singlethread_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_singlethread_unordered name: store_singlethread_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") unordered 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") unordered 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_singlethread_monotonic # GCN-LABEL: name: store_singlethread_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_singlethread_monotonic name: store_singlethread_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") monotonic 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") monotonic 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_singlethread_release # GCN-LABEL: name: store_singlethread_release
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_singlethread_release name: store_singlethread_release
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") release 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") release 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_singlethread_seq_cst # GCN-LABEL: name: store_singlethread_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_singlethread_seq_cst name: store_singlethread_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") seq_cst 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") seq_cst 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_wavefront_unordered # GCN-LABEL: name: store_wavefront_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_wavefront_unordered name: store_wavefront_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") unordered 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") unordered 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_wavefront_monotonic # GCN-LABEL: name: store_wavefront_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_wavefront_monotonic name: store_wavefront_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") monotonic 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") monotonic 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_wavefront_release # GCN-LABEL: name: store_wavefront_release
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_wavefront_release name: store_wavefront_release
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") release 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") release 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_wavefront_seq_cst # GCN-LABEL: name: store_wavefront_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_wavefront_seq_cst name: store_wavefront_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") seq_cst 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("wavefront-one-as") seq_cst 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_workgroup_unordered # GCN-LABEL: name: store_workgroup_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_workgroup_unordered name: store_workgroup_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") unordered 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") unordered 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_workgroup_monotonic # GCN-LABEL: name: store_workgroup_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_workgroup_monotonic name: store_workgroup_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") monotonic 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") monotonic 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_workgroup_release # GCN-LABEL: name: store_workgroup_release
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_workgroup_release name: store_workgroup_release
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") release 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") release 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_workgroup_seq_cst # GCN-LABEL: name: store_workgroup_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_workgroup_seq_cst name: store_workgroup_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") seq_cst 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("workgroup-one-as") seq_cst 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_agent_unordered # GCN-LABEL: name: store_agent_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_agent_unordered name: store_agent_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") unordered 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") unordered 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_agent_monotonic # GCN-LABEL: name: store_agent_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_agent_monotonic name: store_agent_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") monotonic 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") monotonic 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_agent_release # GCN-LABEL: name: store_agent_release
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_agent_release name: store_agent_release
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") release 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") release 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_agent_seq_cst # GCN-LABEL: name: store_agent_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_agent_seq_cst name: store_agent_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") seq_cst 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("agent-one-as") seq_cst 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_system_unordered # GCN-LABEL: name: store_system_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_system_unordered name: store_system_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store unordered 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store unordered 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_system_monotonic # GCN-LABEL: name: store_system_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_system_monotonic name: store_system_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store monotonic 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store monotonic 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_system_release # GCN-LABEL: name: store_system_release
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_system_release name: store_system_release
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("one-as") release 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("one-as") release 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: store_system_seq_cst # GCN-LABEL: name: store_system_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRITE_B32 # GCN: DS_WRITE_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: store_system_seq_cst name: store_system_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("one-as") seq_cst 4 into `i32 addrspace(2)* undef`) DS_WRITE_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("one-as") seq_cst 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: atomicrmw_singlethread_unordered # GCN-LABEL: name: atomicrmw_singlethread_unordered
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRXCHG_RTN_B32 # GCN: DS_WRXCHG_RTN_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: atomicrmw_singlethread_unordered name: atomicrmw_singlethread_unordered
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
$vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") unordered 4 into `i32 addrspace(2)* undef`) $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") unordered 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: atomicrmw_singlethread_monotonic # GCN-LABEL: name: atomicrmw_singlethread_monotonic
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRXCHG_RTN_B32 # GCN: DS_WRXCHG_RTN_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: atomicrmw_singlethread_monotonic name: atomicrmw_singlethread_monotonic
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
$vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") monotonic 4 into `i32 addrspace(2)* undef`) $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") monotonic 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: atomicrmw_singlethread_acquire # GCN-LABEL: name: atomicrmw_singlethread_acquire
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRXCHG_RTN_B32 # GCN: DS_WRXCHG_RTN_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: atomicrmw_singlethread_acquire name: atomicrmw_singlethread_acquire
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
$vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") acquire 4 into `i32 addrspace(2)* undef`) $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") acquire 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: atomicrmw_singlethread_release # GCN-LABEL: name: atomicrmw_singlethread_release
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRXCHG_RTN_B32 # GCN: DS_WRXCHG_RTN_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: atomicrmw_singlethread_release name: atomicrmw_singlethread_release
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
$vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") release 4 into `i32 addrspace(2)* undef`) $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") release 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: atomicrmw_singlethread_acq_rel # GCN-LABEL: name: atomicrmw_singlethread_acq_rel
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRXCHG_RTN_B32 # GCN: DS_WRXCHG_RTN_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: atomicrmw_singlethread_acq_rel name: atomicrmw_singlethread_acq_rel
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
$vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") acq_rel 4 into `i32 addrspace(2)* undef`) $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") acq_rel 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: atomicrmw_singlethread_seq_cst # GCN-LABEL: name: atomicrmw_singlethread_seq_cst
# GCN-LABEL: bb.0: # GCN-LABEL: bb.0:
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: DS_WRXCHG_RTN_B32 # GCN: DS_WRXCHG_RTN_B32
# GCN-NOT: S_WAITCNT # GCN-NOT: S_WAITCNT
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: atomicrmw_singlethread_seq_cst name: atomicrmw_singlethread_seq_cst
body: | body: |
bb.0: bb.0:
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4) $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, addrspace 4)
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 40, 0, 0 :: (dereferenceable invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
$vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
$vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") seq_cst 4 into `i32 addrspace(2)* undef`) $vgpr2 = DS_WRXCHG_RTN_B32 killed renamable $vgpr0, killed renamable $vgpr1, 0, 1, implicit $m0, implicit $exec :: (volatile store syncscope("singlethread-one-as") seq_cst 4 into `i32 addrspace(2)* undef`)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/memory_clause.mir

# RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs -run-pass=phi-node-elimination,si-form-memory-clauses %s -o - | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs -run-pass=phi-node-elimination,si-form-memory-clauses %s -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: {{^}}name: vector_clause{{$}} # GCN-LABEL: {{^}}name: vector_clause{{$}}
# GCN: early-clobber %2:vreg_128, early-clobber %4:vreg_128, early-clobber %1:vreg_128, early-clobber %3:vreg_128 = BUNDLE %0, implicit $exec { # GCN: early-clobber %2:vreg_128, early-clobber %4:vreg_128, early-clobber %1:vreg_128, early-clobber %3:vreg_128 = BUNDLE %0, implicit $exec {
# GCN-NEXT: %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec # GCN-NEXT: %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, implicit $exec # GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, 0, implicit $exec
# GCN-NEXT: %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, implicit $exec # GCN-NEXT: %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, 0, implicit $exec
# GCN-NEXT: %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, implicit $exec # GCN-NEXT: %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, 0, implicit $exec
# GCN-NEXT: } # GCN-NEXT: }
# GCN-NEXT: GLOBAL_STORE_DWORDX4 %0, %1, 0, 0, 0, implicit $exec # GCN-NEXT: GLOBAL_STORE_DWORDX4 %0, %1, 0, 0, 0, 0, implicit $exec
--- ---
name: vector_clause name: vector_clause
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_64 } - { id: 0, class: vreg_64 }
- { id: 1, class: vreg_128 } - { id: 1, class: vreg_128 }
- { id: 2, class: vreg_128 } - { id: 2, class: vreg_128 }
- { id: 3, class: vreg_128 } - { id: 3, class: vreg_128 }
- { id: 4, class: vreg_128 } - { id: 4, class: vreg_128 }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, 0, implicit $exec
%2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, implicit $exec %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, 0, implicit $exec
%3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, implicit $exec %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, 0, implicit $exec
%4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, implicit $exec %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, 0, implicit $exec
GLOBAL_STORE_DWORDX4 %0, %1, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORDX4 %0, %1, 0, 0, 0, 0, implicit $exec
GLOBAL_STORE_DWORDX4 %0, %2, 16, 0, 0, implicit $exec GLOBAL_STORE_DWORDX4 %0, %2, 16, 0, 0, 0, implicit $exec
GLOBAL_STORE_DWORDX4 %0, %3, 32, 0, 0, implicit $exec GLOBAL_STORE_DWORDX4 %0, %3, 32, 0, 0, 0, implicit $exec
GLOBAL_STORE_DWORDX4 %0, %4, 48, 0, 0, implicit $exec GLOBAL_STORE_DWORDX4 %0, %4, 48, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: {{^}}name: subreg_full{{$}} # GCN-LABEL: {{^}}name: subreg_full{{$}}
# GCN: early-clobber %1:vreg_128 = BUNDLE %0, implicit $exec { # GCN: early-clobber %1:vreg_128 = BUNDLE %0, implicit $exec {
# GCN-NEXT: undef %1.sub0:vreg_128 = GLOBAL_LOAD_DWORD %0.sub0_sub1, 0, 0, 0, implicit $exec # GCN-NEXT: undef %1.sub0:vreg_128 = GLOBAL_LOAD_DWORD %0.sub0_sub1, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: internal %1.sub1:vreg_128 = GLOBAL_LOAD_DWORD %0.sub1_sub2, 16, 0, 0, implicit $exec # GCN-NEXT: internal %1.sub1:vreg_128 = GLOBAL_LOAD_DWORD %0.sub1_sub2, 16, 0, 0, 0, implicit $exec
# GCN-NEXT: internal %1.sub2:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, implicit $exec # GCN-NEXT: internal %1.sub2:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, 0, implicit $exec
# GCN-NEXT: internal %1.sub3:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, implicit $exec # GCN-NEXT: internal %1.sub3:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, 0, implicit $exec
# GCN-NEXT: } # GCN-NEXT: }
# GCN-NEXT: GLOBAL_STORE_DWORDX4 %0.sub0_sub1, %1, 0, 0, 0, implicit $exec # GCN-NEXT: GLOBAL_STORE_DWORDX4 %0.sub0_sub1, %1, 0, 0, 0, 0, implicit $exec
--- ---
name: subreg_full name: subreg_full
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_128 } - { id: 0, class: vreg_128 }
- { id: 1, class: vreg_128 } - { id: 1, class: vreg_128 }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
undef %1.sub0:vreg_128 = GLOBAL_LOAD_DWORD %0.sub0_sub1, 0, 0, 0, implicit $exec undef %1.sub0:vreg_128 = GLOBAL_LOAD_DWORD %0.sub0_sub1, 0, 0, 0, 0, implicit $exec
%1.sub1:vreg_128 = GLOBAL_LOAD_DWORD %0.sub1_sub2, 16, 0, 0, implicit $exec %1.sub1:vreg_128 = GLOBAL_LOAD_DWORD %0.sub1_sub2, 16, 0, 0, 0, implicit $exec
%1.sub2:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, implicit $exec %1.sub2:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, 0, implicit $exec
%1.sub3:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, implicit $exec %1.sub3:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, 0, implicit $exec
GLOBAL_STORE_DWORDX4 %0.sub0_sub1, %1, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORDX4 %0.sub0_sub1, %1, 0, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: {{^}}name: subreg_part{{$}} # GCN-LABEL: {{^}}name: subreg_part{{$}}
# GCN: undef early-clobber %1.sub0_sub1:vreg_128, undef early-clobber %1.sub3:vreg_128 = BUNDLE %0, implicit $exec { # GCN: undef early-clobber %1.sub0_sub1:vreg_128, undef early-clobber %1.sub3:vreg_128 = BUNDLE %0, implicit $exec {
# GCN-NEXT: undef %1.sub0:vreg_128 = GLOBAL_LOAD_DWORD %0.sub0_sub1, 0, 0, 0, implicit $exec # GCN-NEXT: undef %1.sub0:vreg_128 = GLOBAL_LOAD_DWORD %0.sub0_sub1, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: internal %1.sub1:vreg_128 = GLOBAL_LOAD_DWORD %0.sub1_sub2, 16, 0, 0, implicit $exec # GCN-NEXT: internal %1.sub1:vreg_128 = GLOBAL_LOAD_DWORD %0.sub1_sub2, 16, 0, 0, 0, implicit $exec
# GCN-NEXT: internal %1.sub3:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, implicit $exec # GCN-NEXT: internal %1.sub3:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, 0, implicit $exec
# GCN-NEXT: } # GCN-NEXT: }
# GCN-NEXT: GLOBAL_STORE_DWORDX4 %0.sub0_sub1, %1, 0, 0, 0, implicit $exec # GCN-NEXT: GLOBAL_STORE_DWORDX4 %0.sub0_sub1, %1, 0, 0, 0, 0, implicit $exec
--- ---
name: subreg_part name: subreg_part
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_128 } - { id: 0, class: vreg_128 }
- { id: 1, class: vreg_128 } - { id: 1, class: vreg_128 }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
undef %1.sub0:vreg_128 = GLOBAL_LOAD_DWORD %0.sub0_sub1, 0, 0, 0, implicit $exec undef %1.sub0:vreg_128 = GLOBAL_LOAD_DWORD %0.sub0_sub1, 0, 0, 0, 0, implicit $exec
%1.sub1:vreg_128 = GLOBAL_LOAD_DWORD %0.sub1_sub2, 16, 0, 0, implicit $exec %1.sub1:vreg_128 = GLOBAL_LOAD_DWORD %0.sub1_sub2, 16, 0, 0, 0, implicit $exec
%1.sub3:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, implicit $exec %1.sub3:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, 0, implicit $exec
GLOBAL_STORE_DWORDX4 %0.sub0_sub1, %1, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORDX4 %0.sub0_sub1, %1, 0, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: {{^}}name: dead{{$}} # GCN-LABEL: {{^}}name: dead{{$}}
# GCN: dead early-clobber %2:vreg_128, dead early-clobber %4:vreg_128, dead early-clobber %1:vreg_128, dead early-clobber %3:vreg_128 = BUNDLE %0, implicit $exec { # GCN: dead early-clobber %2:vreg_128, dead early-clobber %4:vreg_128, dead early-clobber %1:vreg_128, dead early-clobber %3:vreg_128 = BUNDLE %0, implicit $exec {
# GCN-NEXT: dead %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec # GCN-NEXT: dead %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, implicit $exec # GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, implicit $exec # GCN-NEXT: dead %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, implicit $exec # GCN-NEXT: dead %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, 0, implicit $exec
# GCN-NEXT: } # GCN-NEXT: }
--- ---
name: dead name: dead
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_64 } - { id: 0, class: vreg_64 }
- { id: 1, class: vreg_128 } - { id: 1, class: vreg_128 }
- { id: 2, class: vreg_128 } - { id: 2, class: vreg_128 }
- { id: 3, class: vreg_128 } - { id: 3, class: vreg_128 }
- { id: 4, class: vreg_128 } - { id: 4, class: vreg_128 }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
dead %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec dead %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, 0, implicit $exec
dead %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, implicit $exec dead %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, 0, implicit $exec
dead %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, implicit $exec dead %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, 0, implicit $exec
dead %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, implicit $exec dead %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: {{^}}name: subreg_dead{{$}} # GCN-LABEL: {{^}}name: subreg_dead{{$}}
# GCN: early-clobber %1:vreg_64 = BUNDLE %0, implicit $exec { # GCN: early-clobber %1:vreg_64 = BUNDLE %0, implicit $exec {
# GCN-NEXT: %1.sub0:vreg_64 = GLOBAL_LOAD_DWORD %0, 16, 0, 0, implicit $exec # GCN-NEXT: %1.sub0:vreg_64 = GLOBAL_LOAD_DWORD %0, 16, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %1.sub1:vreg_64 = GLOBAL_LOAD_DWORD %0, 32, 0, 0, implicit $exec # GCN-NEXT: dead %1.sub1:vreg_64 = GLOBAL_LOAD_DWORD %0, 32, 0, 0, 0, implicit $exec
# GCN-NEXT: } # GCN-NEXT: }
# GCN-NEXT: GLOBAL_STORE_DWORD %0, %1.sub0, 0, 0, 0, implicit $exec # GCN-NEXT: GLOBAL_STORE_DWORD %0, %1.sub0, 0, 0, 0, 0, implicit $exec
--- ---
name: subreg_dead name: subreg_dead
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_64 } - { id: 0, class: vreg_64 }
- { id: 1, class: vreg_64 } - { id: 1, class: vreg_64 }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
undef %1.sub0:vreg_64 = GLOBAL_LOAD_DWORD %0, 16, 0, 0, implicit $exec undef %1.sub0:vreg_64 = GLOBAL_LOAD_DWORD %0, 16, 0, 0, 0, implicit $exec
dead %1.sub1:vreg_64 = GLOBAL_LOAD_DWORD %0, 32, 0, 0, implicit $exec dead %1.sub1:vreg_64 = GLOBAL_LOAD_DWORD %0, 32, 0, 0, 0, implicit $exec
GLOBAL_STORE_DWORD %0, %1.sub0, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORD %0, %1.sub0, 0, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: {{^}}name: kill{{$}} # GCN-LABEL: {{^}}name: kill{{$}}
# GCN: early-clobber %2:vreg_128, early-clobber %3:vreg_128 = BUNDLE %0, %1, implicit $exec { # GCN: early-clobber %2:vreg_128, early-clobber %3:vreg_128 = BUNDLE %0, %1, implicit $exec {
# GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec # GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 16, 0, 0, implicit $exec # GCN-NEXT: %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 16, 0, 0, 0, implicit $exec
# GCN-NEXT: } # GCN-NEXT: }
--- ---
name: kill name: kill
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_64 } - { id: 0, class: vreg_64 }
- { id: 1, class: vreg_64 } - { id: 1, class: vreg_64 }
- { id: 2, class: vreg_128 } - { id: 2, class: vreg_128 }
- { id: 3, class: vreg_128 } - { id: 3, class: vreg_128 }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1 = IMPLICIT_DEF %1 = IMPLICIT_DEF
%2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, 0, implicit $exec
%3:vreg_128 = GLOBAL_LOAD_DWORDX4 killed %1, 16, 0, 0, implicit $exec %3:vreg_128 = GLOBAL_LOAD_DWORDX4 killed %1, 16, 0, 0, 0, implicit $exec
GLOBAL_STORE_DWORDX4 %0, %2, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORDX4 %0, %2, 0, 0, 0, 0, implicit $exec
GLOBAL_STORE_DWORDX4 %0, %3, 16, 0, 0, implicit $exec GLOBAL_STORE_DWORDX4 %0, %3, 16, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: {{^}}name: indirect{{$}} # GCN-LABEL: {{^}}name: indirect{{$}}
# GCN: %1:vreg_64 = GLOBAL_LOAD_DWORDX2 %0, 0, 0, 0, implicit $exec # GCN: %1:vreg_64 = GLOBAL_LOAD_DWORDX2 %0, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: early-clobber %2:vreg_128, early-clobber %3:vreg_128 = BUNDLE %1, implicit $exec { # GCN-NEXT: early-clobber %2:vreg_128, early-clobber %3:vreg_128 = BUNDLE %1, implicit $exec {
# GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 0, 0, 0, implicit $exec # GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 16, 0, 0, implicit $exec # GCN-NEXT: %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 16, 0, 0, 0, implicit $exec
# GCN-NEXT: } # GCN-NEXT: }
--- ---
name: indirect name: indirect
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_64 } - { id: 0, class: vreg_64 }
- { id: 1, class: vreg_64 } - { id: 1, class: vreg_64 }
- { id: 2, class: vreg_128 } - { id: 2, class: vreg_128 }
- { id: 3, class: vreg_128 } - { id: 3, class: vreg_128 }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1:vreg_64 = GLOBAL_LOAD_DWORDX2 %0, 0, 0, 0, implicit $exec %1:vreg_64 = GLOBAL_LOAD_DWORDX2 %0, 0, 0, 0, 0, implicit $exec
%2:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 0, 0, 0, implicit $exec %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 0, 0, 0, 0, implicit $exec
%3:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 16, 0, 0, implicit $exec %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 16, 0, 0, 0, implicit $exec
GLOBAL_STORE_DWORDX4 %0, %2, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORDX4 %0, %2, 0, 0, 0, 0, implicit $exec
GLOBAL_STORE_DWORDX4 %0, %3, 16, 0, 0, implicit $exec GLOBAL_STORE_DWORDX4 %0, %3, 16, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: {{^}}name: stack{{$}} # GCN-LABEL: {{^}}name: stack{{$}}
# GCN: %0:vreg_64 = IMPLICIT_DEF # GCN: %0:vreg_64 = IMPLICIT_DEF
# GCN-NEXT: %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %stack.0, 0, 0, 0, implicit $exec # GCN-NEXT: %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %stack.0, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %stack.0, 16, 0, 0, implicit $exec # GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %stack.0, 16, 0, 0, 0, implicit $exec
# GCN-NEXT: GLOBAL_STORE_DWORDX4 %0, %1, 0, 0, 0, implicit $exec # GCN-NEXT: GLOBAL_STORE_DWORDX4 %0, %1, 0, 0, 0, 0, implicit $exec
--- ---
name: stack name: stack
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_64 } - { id: 0, class: vreg_64 }
- { id: 1, class: vreg_128 } - { id: 1, class: vreg_128 }
- { id: 2, class: vreg_128 } - { id: 2, class: vreg_128 }
stack: stack:
- { id: 0, type: default, offset: 0, size: 64, alignment: 8 } - { id: 0, type: default, offset: 0, size: 64, alignment: 8 }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1:vreg_128 = GLOBAL_LOAD_DWORDX4 %stack.0, 0, 0, 0, implicit $exec %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %stack.0, 0, 0, 0, 0, implicit $exec
%2:vreg_128 = GLOBAL_LOAD_DWORDX4 %stack.0, 16, 0, 0, implicit $exec %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %stack.0, 16, 0, 0, 0, implicit $exec
GLOBAL_STORE_DWORDX4 %0, %1, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORDX4 %0, %1, 0, 0, 0, 0, implicit $exec
GLOBAL_STORE_DWORDX4 %0, %2, 16, 0, 0, implicit $exec GLOBAL_STORE_DWORDX4 %0, %2, 16, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: {{^}}name: overflow_counter{{$}} # GCN-LABEL: {{^}}name: overflow_counter{{$}}
# GCN: dead early-clobber %7:vgpr_32, dead early-clobber %14:vgpr_32, dead early-clobber %2:vgpr_32, dead early-clobber %9:vgpr_32, dead early-clobber %4:vgpr_32, dead early-clobber %11:vgpr_32, dead early-clobber %6:vgpr_32, dead early-clobber %13:vgpr_32, dead early-clobber %1:vgpr_32, dead early-clobber %8:vgpr_32, dead early-clobber %15:vgpr_32, dead early-clobber %3:vgpr_32, dead early-clobber %10:vgpr_32, dead early-clobber %5:vgpr_32, dead early-clobber %12:vgpr_32 = BUNDLE %0, implicit $exec { # GCN: dead early-clobber %7:vgpr_32, dead early-clobber %14:vgpr_32, dead early-clobber %2:vgpr_32, dead early-clobber %9:vgpr_32, dead early-clobber %4:vgpr_32, dead early-clobber %11:vgpr_32, dead early-clobber %6:vgpr_32, dead early-clobber %13:vgpr_32, dead early-clobber %1:vgpr_32, dead early-clobber %8:vgpr_32, dead early-clobber %15:vgpr_32, dead early-clobber %3:vgpr_32, dead early-clobber %10:vgpr_32, dead early-clobber %5:vgpr_32, dead early-clobber %12:vgpr_32 = BUNDLE %0, implicit $exec {
# GCN-NEXT: dead %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, 0, implicit $exec # GCN-NEXT: dead %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, 0, implicit $exec # GCN-NEXT: dead %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, 0, implicit $exec # GCN-NEXT: dead %3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %4:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 0, 0, implicit $exec # GCN-NEXT: dead %4:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %5:vgpr_32 = GLOBAL_LOAD_DWORD %0, 16, 0, 0, implicit $exec # GCN-NEXT: dead %5:vgpr_32 = GLOBAL_LOAD_DWORD %0, 16, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %6:vgpr_32 = GLOBAL_LOAD_DWORD %0, 20, 0, 0, implicit $exec # GCN-NEXT: dead %6:vgpr_32 = GLOBAL_LOAD_DWORD %0, 20, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %7:vgpr_32 = GLOBAL_LOAD_DWORD %0, 24, 0, 0, implicit $exec # GCN-NEXT: dead %7:vgpr_32 = GLOBAL_LOAD_DWORD %0, 24, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %8:vgpr_32 = GLOBAL_LOAD_DWORD %0, 28, 0, 0, implicit $exec # GCN-NEXT: dead %8:vgpr_32 = GLOBAL_LOAD_DWORD %0, 28, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %9:vgpr_32 = GLOBAL_LOAD_DWORD %0, 32, 0, 0, implicit $exec # GCN-NEXT: dead %9:vgpr_32 = GLOBAL_LOAD_DWORD %0, 32, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %10:vgpr_32 = GLOBAL_LOAD_DWORD %0, 36, 0, 0, implicit $exec # GCN-NEXT: dead %10:vgpr_32 = GLOBAL_LOAD_DWORD %0, 36, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %11:vgpr_32 = GLOBAL_LOAD_DWORD %0, 40, 0, 0, implicit $exec # GCN-NEXT: dead %11:vgpr_32 = GLOBAL_LOAD_DWORD %0, 40, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %12:vgpr_32 = GLOBAL_LOAD_DWORD %0, 44, 0, 0, implicit $exec # GCN-NEXT: dead %12:vgpr_32 = GLOBAL_LOAD_DWORD %0, 44, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %13:vgpr_32 = GLOBAL_LOAD_DWORD %0, 48, 0, 0, implicit $exec # GCN-NEXT: dead %13:vgpr_32 = GLOBAL_LOAD_DWORD %0, 48, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %14:vgpr_32 = GLOBAL_LOAD_DWORD %0, 52, 0, 0, implicit $exec # GCN-NEXT: dead %14:vgpr_32 = GLOBAL_LOAD_DWORD %0, 52, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %15:vgpr_32 = GLOBAL_LOAD_DWORD %0, 56, 0, 0, implicit $exec # GCN-NEXT: dead %15:vgpr_32 = GLOBAL_LOAD_DWORD %0, 56, 0, 0, 0, implicit $exec
# GCN-NEXT: } # GCN-NEXT: }
# GCN-NEXT: dead early-clobber %16:vgpr_32, dead early-clobber %17:vgpr_32 = BUNDLE %0, implicit $exec { # GCN-NEXT: dead early-clobber %16:vgpr_32, dead early-clobber %17:vgpr_32 = BUNDLE %0, implicit $exec {
# GCN-NEXT: dead %16:vgpr_32 = GLOBAL_LOAD_DWORD %0, 60, 0, 0, implicit $exec # GCN-NEXT: dead %16:vgpr_32 = GLOBAL_LOAD_DWORD %0, 60, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %17:vgpr_32 = GLOBAL_LOAD_DWORD %0, 64, 0, 0, implicit $exec # GCN-NEXT: dead %17:vgpr_32 = GLOBAL_LOAD_DWORD %0, 64, 0, 0, 0, implicit $exec
# GCN-NEXT: } # GCN-NEXT: }
--- ---
name: overflow_counter name: overflow_counter
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_64 } - { id: 0, class: vreg_64 }
- { id: 1, class: vgpr_32 } - { id: 1, class: vgpr_32 }
Show All 11 Linesregisters:
- { id: 13, class: vgpr_32 } - { id: 13, class: vgpr_32 }
- { id: 14, class: vgpr_32 } - { id: 14, class: vgpr_32 }
- { id: 15, class: vgpr_32 } - { id: 15, class: vgpr_32 }
- { id: 16, class: vgpr_32 } - { id: 16, class: vgpr_32 }
- { id: 17, class: vgpr_32 } - { id: 17, class: vgpr_32 }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, 0, implicit $exec %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, 0, implicit $exec %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, 0, 0, implicit $exec
%3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, 0, implicit $exec %3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, 0, 0, implicit $exec
%4:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 0, 0, implicit $exec %4:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 0, 0, 0, implicit $exec
%5:vgpr_32 = GLOBAL_LOAD_DWORD %0, 16, 0, 0, implicit $exec %5:vgpr_32 = GLOBAL_LOAD_DWORD %0, 16, 0, 0, 0, implicit $exec
%6:vgpr_32 = GLOBAL_LOAD_DWORD %0, 20, 0, 0, implicit $exec %6:vgpr_32 = GLOBAL_LOAD_DWORD %0, 20, 0, 0, 0, implicit $exec
%7:vgpr_32 = GLOBAL_LOAD_DWORD %0, 24, 0, 0, implicit $exec %7:vgpr_32 = GLOBAL_LOAD_DWORD %0, 24, 0, 0, 0, implicit $exec
%8:vgpr_32 = GLOBAL_LOAD_DWORD %0, 28, 0, 0, implicit $exec %8:vgpr_32 = GLOBAL_LOAD_DWORD %0, 28, 0, 0, 0, implicit $exec
%9:vgpr_32 = GLOBAL_LOAD_DWORD %0, 32, 0, 0, implicit $exec %9:vgpr_32 = GLOBAL_LOAD_DWORD %0, 32, 0, 0, 0, implicit $exec
%10:vgpr_32 = GLOBAL_LOAD_DWORD %0, 36, 0, 0, implicit $exec %10:vgpr_32 = GLOBAL_LOAD_DWORD %0, 36, 0, 0, 0, implicit $exec
%11:vgpr_32 = GLOBAL_LOAD_DWORD %0, 40, 0, 0, implicit $exec %11:vgpr_32 = GLOBAL_LOAD_DWORD %0, 40, 0, 0, 0, implicit $exec
%12:vgpr_32 = GLOBAL_LOAD_DWORD %0, 44, 0, 0, implicit $exec %12:vgpr_32 = GLOBAL_LOAD_DWORD %0, 44, 0, 0, 0, implicit $exec
%13:vgpr_32 = GLOBAL_LOAD_DWORD %0, 48, 0, 0, implicit $exec %13:vgpr_32 = GLOBAL_LOAD_DWORD %0, 48, 0, 0, 0, implicit $exec
%14:vgpr_32 = GLOBAL_LOAD_DWORD %0, 52, 0, 0, implicit $exec %14:vgpr_32 = GLOBAL_LOAD_DWORD %0, 52, 0, 0, 0, implicit $exec
%15:vgpr_32 = GLOBAL_LOAD_DWORD %0, 56, 0, 0, implicit $exec %15:vgpr_32 = GLOBAL_LOAD_DWORD %0, 56, 0, 0, 0, implicit $exec
%16:vgpr_32 = GLOBAL_LOAD_DWORD %0, 60, 0, 0, implicit $exec %16:vgpr_32 = GLOBAL_LOAD_DWORD %0, 60, 0, 0, 0, implicit $exec
%17:vgpr_32 = GLOBAL_LOAD_DWORD %0, 64, 0, 0, implicit $exec %17:vgpr_32 = GLOBAL_LOAD_DWORD %0, 64, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: {{^}}name: reg_pressure{{$}} # GCN-LABEL: {{^}}name: reg_pressure{{$}}
# GCN: dead early-clobber %2:vreg_128, dead early-clobber %4:vreg_128, dead early-clobber %1:vreg_128, dead early-clobber %3:vreg_128, dead early-clobber %5:vreg_128 = BUNDLE %0, implicit $exec { # GCN: dead early-clobber %2:vreg_128, dead early-clobber %4:vreg_128, dead early-clobber %1:vreg_128, dead early-clobber %3:vreg_128, dead early-clobber %5:vreg_128 = BUNDLE %0, implicit $exec {
# GCN-NEXT: dead %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec # GCN-NEXT: dead %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, implicit $exec # GCN-NEXT: dead %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, implicit $exec # GCN-NEXT: dead %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, implicit $exec # GCN-NEXT: dead %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %5:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 64, 0, 0, implicit $exec # GCN-NEXT: dead %5:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 64, 0, 0, 0, implicit $exec
# GCN-NEXT: } # GCN-NEXT: }
# GCN-NEXT: dead early-clobber %7:vreg_128, dead early-clobber %6:vreg_128 = BUNDLE %0, implicit $exec { # GCN-NEXT: dead early-clobber %7:vreg_128, dead early-clobber %6:vreg_128 = BUNDLE %0, implicit $exec {
# GCN-NEXT: dead %6:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 80, 0, 0, implicit $exec # GCN-NEXT: dead %6:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 80, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %7:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 96, 0, 0, implicit $exec # GCN-NEXT: dead %7:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 96, 0, 0, 0, implicit $exec
# GCN-NEXT: } # GCN-NEXT: }
--- ---
name: reg_pressure name: reg_pressure
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_64 } - { id: 0, class: vreg_64 }
- { id: 1, class: vreg_128 } - { id: 1, class: vreg_128 }
- { id: 2, class: vreg_128 } - { id: 2, class: vreg_128 }
- { id: 3, class: vreg_128 } - { id: 3, class: vreg_128 }
- { id: 4, class: vreg_128 } - { id: 4, class: vreg_128 }
- { id: 5, class: vreg_128 } - { id: 5, class: vreg_128 }
- { id: 6, class: vreg_128 } - { id: 6, class: vreg_128 }
- { id: 7, class: vreg_128 } - { id: 7, class: vreg_128 }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, 0, implicit $exec
%2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, implicit $exec %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, 0, implicit $exec
%3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, implicit $exec %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, 0, implicit $exec
%4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, implicit $exec %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, 0, implicit $exec
%5:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 64, 0, 0, implicit $exec %5:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 64, 0, 0, 0, implicit $exec
%6:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 80, 0, 0, implicit $exec %6:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 80, 0, 0, 0, implicit $exec
%7:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 96, 0, 0, implicit $exec %7:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 96, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: {{^}}name: image_clause{{$}} # GCN-LABEL: {{^}}name: image_clause{{$}}
# GCN: early-clobber %4:vreg_128, early-clobber %3:vreg_128, early-clobber %5:vreg_128 = BUNDLE %0, undef %2:sreg_128, %1, implicit $exec { # GCN: early-clobber %4:vreg_128, early-clobber %3:vreg_128, early-clobber %5:vreg_128 = BUNDLE %0, undef %2:sreg_128, %1, implicit $exec {
# GCN-NEXT: %3:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec # GCN-NEXT: %3:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: %4:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec # GCN-NEXT: %4:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: %5:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec # GCN-NEXT: %5:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: } # GCN-NEXT: }
Show All 19 Lines bb.0:
IMAGE_STORE_V4_V2 %3, %0, %1, 15, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec IMAGE_STORE_V4_V2 %3, %0, %1, 15, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec
IMAGE_STORE_V4_V2 %4, %0, %1, 15, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec IMAGE_STORE_V4_V2 %4, %0, %1, 15, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec
IMAGE_STORE_V4_V2 %5, %0, %1, 15, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec IMAGE_STORE_V4_V2 %5, %0, %1, 15, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: {{^}}name: mixed_clause{{$}} # GCN-LABEL: {{^}}name: mixed_clause{{$}}
# GCN: dead early-clobber %4:vreg_128, dead early-clobber %3:vreg_128, dead early-clobber %5:vgpr_32 = BUNDLE %0, %2, %1, implicit $exec { # GCN: dead early-clobber %4:vreg_128, dead early-clobber %3:vreg_128, dead early-clobber %5:vgpr_32 = BUNDLE %0, %2, %1, implicit $exec {
# GCN-NEXT: dead %3:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, %2, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec # GCN-NEXT: dead %3:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, %2, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec # GCN-NEXT: dead %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: dead %5:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 %0, %2, 0, 0, 0, 0, 0, implicit $exec # GCN-NEXT: dead %5:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 %0, %2, 0, 0, 0, 0, 0, 0, implicit $exec
# GCN-NEXT: } # GCN-NEXT: }
--- ---
name: mixed_clause name: mixed_clause
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_64 } - { id: 0, class: vreg_64 }
- { id: 1, class: sreg_256 } - { id: 1, class: sreg_256 }
- { id: 2, class: sreg_128 } - { id: 2, class: sreg_128 }
- { id: 3, class: vreg_128 } - { id: 3, class: vreg_128 }
- { id: 4, class: vreg_128 } - { id: 4, class: vreg_128 }
- { id: 5, class: vgpr_32 } - { id: 5, class: vgpr_32 }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1 = IMPLICIT_DEF %1 = IMPLICIT_DEF
%2 = IMPLICIT_DEF %2 = IMPLICIT_DEF
%3:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, %2, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec %3:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, %2, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
%4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, 0, implicit $exec
%5:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 %0, %2, 0, 0, 0, 0, 0, implicit $exec %5:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 %0, %2, 0, 0, 0, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: {{^}}name: atomic{{$}} # GCN-LABEL: {{^}}name: atomic{{$}}
# GCN: %1:vgpr_32 = IMPLICIT_DEF # GCN: %1:vgpr_32 = IMPLICIT_DEF
# GCN-NEXT: dead %2:vgpr_32 = FLAT_ATOMIC_ADD_RTN %0, %1, 0, 0, implicit $exec, implicit $flat_scr # GCN-NEXT: dead %2:vgpr_32 = FLAT_ATOMIC_ADD_RTN %0, %1, 0, 0, implicit $exec, implicit $flat_scr
# GCN-NEXT: dead %3:vgpr_32 = FLAT_ATOMIC_ADD_RTN %0, %1, 0, 0, implicit $exec, implicit $flat_scr # GCN-NEXT: dead %3:vgpr_32 = FLAT_ATOMIC_ADD_RTN %0, %1, 0, 0, implicit $exec, implicit $flat_scr
# GCN-NEXT: FLAT_ATOMIC_ADD %0, %1, 0, 0, implicit $exec, implicit $flat_scr # GCN-NEXT: FLAT_ATOMIC_ADD %0, %1, 0, 0, implicit $exec, implicit $flat_scr
# GCN-NEXT: FLAT_ATOMIC_ADD %0, %1, 0, 0, implicit $exec, implicit $flat_scr # GCN-NEXT: FLAT_ATOMIC_ADD %0, %1, 0, 0, implicit $exec, implicit $flat_scr
Show All 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir

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# COMMON: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec # COMMON: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
# COMMON: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec # COMMON: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
# COMMON: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec # COMMON: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
# COMMON: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3 # COMMON: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
# COMMON: [[CMP0:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec # COMMON: [[CMP0:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
# COMMON: [[CMP1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec # COMMON: [[CMP1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
# COMMON: [[CMP:%[0-9]+]]:sreg_64 = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc # COMMON: [[CMP:%[0-9]+]]:sreg_64 = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
# COMMON: [[TMPEXEC:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec # COMMON: [[TMPEXEC:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
# COMMON: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, implicit $exec # COMMON: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, 0, implicit $exec
# COMMON: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc # COMMON: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
# COMMON: S_CBRANCH_EXECNZ %bb.1, implicit $exec # COMMON: S_CBRANCH_EXECNZ %bb.1, implicit $exec
# COMMON-LABEL bb.2: # COMMON-LABEL bb.2:
# COMMON: $exec = S_MOV_B64 [[SAVEEXEC]] # COMMON: $exec = S_MOV_B64 [[SAVEEXEC]]
--- ---
name: idxen name: idxen
liveins: liveins:
- { reg: '$vgpr0', virtual-reg: '%0' } - { reg: '$vgpr0', virtual-reg: '%0' }
- { reg: '$vgpr1', virtual-reg: '%1' } - { reg: '$vgpr1', virtual-reg: '%1' }
- { reg: '$vgpr2', virtual-reg: '%2' } - { reg: '$vgpr2', virtual-reg: '%2' }
- { reg: '$vgpr3', virtual-reg: '%3' } - { reg: '$vgpr3', virtual-reg: '%3' }
- { reg: '$vgpr4', virtual-reg: '%4' } - { reg: '$vgpr4', virtual-reg: '%4' }
- { reg: '$sgpr30_sgpr31', virtual-reg: '%5' } - { reg: '$sgpr30_sgpr31', virtual-reg: '%5' }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31
%5:sreg_64 = COPY $sgpr30_sgpr31 %5:sreg_64 = COPY $sgpr30_sgpr31
%4:vgpr_32 = COPY $vgpr4 %4:vgpr_32 = COPY $vgpr4
%3:vgpr_32 = COPY $vgpr3 %3:vgpr_32 = COPY $vgpr3
%2:vgpr_32 = COPY $vgpr2 %2:vgpr_32 = COPY $vgpr2
%1:vgpr_32 = COPY $vgpr1 %1:vgpr_32 = COPY $vgpr1
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3 %6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN %4, killed %6, 0, 0, 0, 0, 0, implicit $exec %7:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN %4, killed %6, 0, 0, 0, 0, 0, 0, implicit $exec
$sgpr30_sgpr31 = COPY %5 $sgpr30_sgpr31 = COPY %5
$vgpr0 = COPY %7 $vgpr0 = COPY %7
S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0 S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
... ...
# COMMON-LABEL: name: offen # COMMON-LABEL: name: offen
# COMMON-LABEL: bb.0: # COMMON-LABEL: bb.0:
# COMMON-NEXT: successors: %bb.1({{.*}}) # COMMON-NEXT: successors: %bb.1({{.*}})
# COMMON: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3 # COMMON: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
# COMMON: [[SAVEEXEC:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec # COMMON: [[SAVEEXEC:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
# COMMON-LABEL: bb.1: # COMMON-LABEL: bb.1:
# COMMON-NEXT: successors: %bb.1({{.*}}), %bb.2({{.*}}) # COMMON-NEXT: successors: %bb.1({{.*}}), %bb.2({{.*}})
# COMMON: [[SRSRC0:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub0, implicit $exec # COMMON: [[SRSRC0:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub0, implicit $exec
# COMMON: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec # COMMON: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
# COMMON: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec # COMMON: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
# COMMON: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec # COMMON: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
# COMMON: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3 # COMMON: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
# COMMON: [[CMP0:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec # COMMON: [[CMP0:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
# COMMON: [[CMP1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec # COMMON: [[CMP1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
# COMMON: [[CMP:%[0-9]+]]:sreg_64 = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc # COMMON: [[CMP:%[0-9]+]]:sreg_64 = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
# COMMON: [[TMPEXEC:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec # COMMON: [[TMPEXEC:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
# COMMON: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, implicit $exec # COMMON: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, 0, implicit $exec
# COMMON: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc # COMMON: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
# COMMON: S_CBRANCH_EXECNZ %bb.1, implicit $exec # COMMON: S_CBRANCH_EXECNZ %bb.1, implicit $exec
# COMMON-LABEL bb.2: # COMMON-LABEL bb.2:
# COMMON: $exec = S_MOV_B64 [[SAVEEXEC]] # COMMON: $exec = S_MOV_B64 [[SAVEEXEC]]
--- ---
name: offen name: offen
liveins: liveins:
- { reg: '$vgpr0', virtual-reg: '%0' } - { reg: '$vgpr0', virtual-reg: '%0' }
- { reg: '$vgpr1', virtual-reg: '%1' } - { reg: '$vgpr1', virtual-reg: '%1' }
- { reg: '$vgpr2', virtual-reg: '%2' } - { reg: '$vgpr2', virtual-reg: '%2' }
- { reg: '$vgpr3', virtual-reg: '%3' } - { reg: '$vgpr3', virtual-reg: '%3' }
- { reg: '$vgpr4', virtual-reg: '%4' } - { reg: '$vgpr4', virtual-reg: '%4' }
- { reg: '$sgpr30_sgpr31', virtual-reg: '%5' } - { reg: '$sgpr30_sgpr31', virtual-reg: '%5' }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31
%5:sreg_64 = COPY $sgpr30_sgpr31 %5:sreg_64 = COPY $sgpr30_sgpr31
%4:vgpr_32 = COPY $vgpr4 %4:vgpr_32 = COPY $vgpr4
%3:vgpr_32 = COPY $vgpr3 %3:vgpr_32 = COPY $vgpr3
%2:vgpr_32 = COPY $vgpr2 %2:vgpr_32 = COPY $vgpr2
%1:vgpr_32 = COPY $vgpr1 %1:vgpr_32 = COPY $vgpr1
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3 %6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFEN %4, killed %6, 0, 0, 0, 0, 0, implicit $exec %7:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFEN %4, killed %6, 0, 0, 0, 0, 0, 0, implicit $exec
$sgpr30_sgpr31 = COPY %5 $sgpr30_sgpr31 = COPY %5
$vgpr0 = COPY %7 $vgpr0 = COPY %7
S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0 S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
... ...
# COMMON-LABEL: name: bothen # COMMON-LABEL: name: bothen
# COMMON-LABEL: bb.0: # COMMON-LABEL: bb.0:
# COMMON-NEXT: successors: %bb.1({{.*}}) # COMMON-NEXT: successors: %bb.1({{.*}})
# COMMON: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3 # COMMON: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
# COMMON: [[SAVEEXEC:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec # COMMON: [[SAVEEXEC:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
# COMMON-LABEL: bb.1: # COMMON-LABEL: bb.1:
# COMMON-NEXT: successors: %bb.1({{.*}}), %bb.2({{.*}}) # COMMON-NEXT: successors: %bb.1({{.*}}), %bb.2({{.*}})
# COMMON: [[SRSRC0:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub0, implicit $exec # COMMON: [[SRSRC0:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub0, implicit $exec
# COMMON: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec # COMMON: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
# COMMON: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec # COMMON: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
# COMMON: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec # COMMON: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
# COMMON: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3 # COMMON: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
# COMMON: [[CMP0:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec # COMMON: [[CMP0:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
# COMMON: [[CMP1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec # COMMON: [[CMP1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
# COMMON: [[CMP:%[0-9]+]]:sreg_64 = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc # COMMON: [[CMP:%[0-9]+]]:sreg_64 = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
# COMMON: [[TMPEXEC:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec # COMMON: [[TMPEXEC:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
# COMMON: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, implicit $exec # COMMON: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, 0, implicit $exec
# COMMON: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc # COMMON: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
# COMMON: S_CBRANCH_EXECNZ %bb.1, implicit $exec # COMMON: S_CBRANCH_EXECNZ %bb.1, implicit $exec
# COMMON-LABEL bb.2: # COMMON-LABEL bb.2:
# COMMON: $exec = S_MOV_B64 [[SAVEEXEC]] # COMMON: $exec = S_MOV_B64 [[SAVEEXEC]]
--- ---
name: bothen name: bothen
liveins: liveins:
- { reg: '$vgpr0', virtual-reg: '%0' } - { reg: '$vgpr0', virtual-reg: '%0' }
- { reg: '$vgpr1', virtual-reg: '%1' } - { reg: '$vgpr1', virtual-reg: '%1' }
- { reg: '$vgpr2', virtual-reg: '%2' } - { reg: '$vgpr2', virtual-reg: '%2' }
- { reg: '$vgpr3', virtual-reg: '%3' } - { reg: '$vgpr3', virtual-reg: '%3' }
- { reg: '$vgpr4_vgpr5', virtual-reg: '%4' } - { reg: '$vgpr4_vgpr5', virtual-reg: '%4' }
- { reg: '$sgpr30_sgpr31', virtual-reg: '%5' } - { reg: '$sgpr30_sgpr31', virtual-reg: '%5' }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31
%5:sreg_64 = COPY $sgpr30_sgpr31 %5:sreg_64 = COPY $sgpr30_sgpr31
%4:vreg_64 = COPY $vgpr4_vgpr5 %4:vreg_64 = COPY $vgpr4_vgpr5
%3:vgpr_32 = COPY $vgpr3 %3:vgpr_32 = COPY $vgpr3
%2:vgpr_32 = COPY $vgpr2 %2:vgpr_32 = COPY $vgpr2
%1:vgpr_32 = COPY $vgpr1 %1:vgpr_32 = COPY $vgpr1
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3 %6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN %4, killed %6, 0, 0, 0, 0, 0, implicit $exec %7:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN %4, killed %6, 0, 0, 0, 0, 0, 0, implicit $exec
$sgpr30_sgpr31 = COPY %5 $sgpr30_sgpr31 = COPY %5
$vgpr0 = COPY %7 $vgpr0 = COPY %7
S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0 S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
... ...
# COMMON-LABEL: name: addr64 # COMMON-LABEL: name: addr64
# COMMON-LABEL: bb.0: # COMMON-LABEL: bb.0:
# COMMON: %12:vreg_64 = COPY %8.sub0_sub1 # COMMON: %12:vreg_64 = COPY %8.sub0_sub1
# COMMON: %13:sreg_64 = S_MOV_B64 0 # COMMON: %13:sreg_64 = S_MOV_B64 0
# COMMON: %14:sgpr_32 = S_MOV_B32 0 # COMMON: %14:sgpr_32 = S_MOV_B32 0
# COMMON: %15:sgpr_32 = S_MOV_B32 61440 # COMMON: %15:sgpr_32 = S_MOV_B32 61440
# COMMON: %16:sreg_128 = REG_SEQUENCE %13, %subreg.sub0_sub1, %14, %subreg.sub2, %15, %subreg.sub3 # COMMON: %16:sreg_128 = REG_SEQUENCE %13, %subreg.sub0_sub1, %14, %subreg.sub2, %15, %subreg.sub3
# COMMON: %9:vgpr_32 = V_ADD_I32_e32 %12.sub0, %4.sub0, implicit-def $vcc, implicit $exec # COMMON: %9:vgpr_32 = V_ADD_I32_e32 %12.sub0, %4.sub0, implicit-def $vcc, implicit $exec
# COMMON: %10:vgpr_32 = V_ADDC_U32_e32 %12.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec # COMMON: %10:vgpr_32 = V_ADDC_U32_e32 %12.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec
# COMMON: %11:vreg_64 = REG_SEQUENCE %9, %subreg.sub0, %10, %subreg.sub1 # COMMON: %11:vreg_64 = REG_SEQUENCE %9, %subreg.sub0, %10, %subreg.sub1
# COMMON: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_ADDR64 %11, killed %16, 0, 0, 0, 0, 0, implicit $exec # COMMON: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_ADDR64 %11, killed %16, 0, 0, 0, 0, 0, 0, implicit $exec
--- ---
name: addr64 name: addr64
liveins: liveins:
- { reg: '$vgpr0', virtual-reg: '%0' } - { reg: '$vgpr0', virtual-reg: '%0' }
- { reg: '$vgpr1', virtual-reg: '%1' } - { reg: '$vgpr1', virtual-reg: '%1' }
- { reg: '$vgpr2', virtual-reg: '%2' } - { reg: '$vgpr2', virtual-reg: '%2' }
- { reg: '$vgpr3', virtual-reg: '%3' } - { reg: '$vgpr3', virtual-reg: '%3' }
- { reg: '$vgpr4_vgpr5', virtual-reg: '%4' } - { reg: '$vgpr4_vgpr5', virtual-reg: '%4' }
- { reg: '$sgpr30_sgpr31', virtual-reg: '%5' } - { reg: '$sgpr30_sgpr31', virtual-reg: '%5' }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31
%5:sreg_64 = COPY $sgpr30_sgpr31 %5:sreg_64 = COPY $sgpr30_sgpr31
%4:vreg_64 = COPY $vgpr4_vgpr5 %4:vreg_64 = COPY $vgpr4_vgpr5
%3:vgpr_32 = COPY $vgpr3 %3:vgpr_32 = COPY $vgpr3
%2:vgpr_32 = COPY $vgpr2 %2:vgpr_32 = COPY $vgpr2
%1:vgpr_32 = COPY $vgpr1 %1:vgpr_32 = COPY $vgpr1
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3 %6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_ADDR64 %4, killed %6, 0, 0, 0, 0, 0, implicit $exec %7:vgpr_32 = BUFFER_LOAD_FORMAT_X_ADDR64 %4, killed %6, 0, 0, 0, 0, 0, 0, implicit $exec
$sgpr30_sgpr31 = COPY %5 $sgpr30_sgpr31 = COPY %5
$vgpr0 = COPY %7 $vgpr0 = COPY %7
S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0 S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
... ...
# COMMON-LABEL: name: offset # COMMON-LABEL: name: offset
# COMMON-LABEL: bb.0: # COMMON-LABEL: bb.0:
# NO-ADDR64-NEXT: successors: %bb.1({{.*}}) # NO-ADDR64-NEXT: successors: %bb.1({{.*}})
# NO-ADDR64: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3 # NO-ADDR64: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
# NO-ADDR64: [[SAVEEXEC:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec # NO-ADDR64: [[SAVEEXEC:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
# NO-ADDR64-LABEL: bb.1: # NO-ADDR64-LABEL: bb.1:
# NO-ADDR64-NEXT: successors: %bb.1({{.*}}), %bb.2({{.*}}) # NO-ADDR64-NEXT: successors: %bb.1({{.*}}), %bb.2({{.*}})
# NO-ADDR64: [[SRSRC0:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub0, implicit $exec # NO-ADDR64: [[SRSRC0:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub0, implicit $exec
# NO-ADDR64: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec # NO-ADDR64: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
# NO-ADDR64: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec # NO-ADDR64: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
# NO-ADDR64: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec # NO-ADDR64: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
# NO-ADDR64: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3 # NO-ADDR64: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
# NO-ADDR64: [[CMP0:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec # NO-ADDR64: [[CMP0:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
# NO-ADDR64: [[CMP1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec # NO-ADDR64: [[CMP1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
# NO-ADDR64: [[CMP:%[0-9]+]]:sreg_64 = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc # NO-ADDR64: [[CMP:%[0-9]+]]:sreg_64 = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
# NO-ADDR64: [[TMPEXEC:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec # NO-ADDR64: [[TMPEXEC:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
# NO-ADDR64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFSET killed [[SRSRC]], 0, 0, 0, 0, 0, implicit $exec # NO-ADDR64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFSET killed [[SRSRC]], 0, 0, 0, 0, 0, 0, implicit $exec
# NO-ADDR64: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc # NO-ADDR64: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
# NO-ADDR64: S_CBRANCH_EXECNZ %bb.1, implicit $exec # NO-ADDR64: S_CBRANCH_EXECNZ %bb.1, implicit $exec
# NO-ADDR64-LABEL bb.2: # NO-ADDR64-LABEL bb.2:
# NO-ADDR64: $exec = S_MOV_B64 [[SAVEEXEC]] # NO-ADDR64: $exec = S_MOV_B64 [[SAVEEXEC]]
# ADDR64: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3 # ADDR64: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
# ADDR64: [[RSRCPTR:%[0-9]+]]:vreg_64 = COPY [[VRSRC]].sub0_sub1 # ADDR64: [[RSRCPTR:%[0-9]+]]:vreg_64 = COPY [[VRSRC]].sub0_sub1
# ADDR64: [[ZERO64:%[0-9]+]]:sreg_64 = S_MOV_B64 0 # ADDR64: [[ZERO64:%[0-9]+]]:sreg_64 = S_MOV_B64 0
# ADDR64: [[RSRCFMTLO:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 # ADDR64: [[RSRCFMTLO:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
# ADDR64: [[RSRCFMTHI:%[0-9]+]]:sgpr_32 = S_MOV_B32 61440 # ADDR64: [[RSRCFMTHI:%[0-9]+]]:sgpr_32 = S_MOV_B32 61440
# ADDR64: [[ZERORSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[ZERO64]], %subreg.sub0_sub1, [[RSRCFMTLO]], %subreg.sub2, [[RSRCFMTHI]], %subreg.sub3 # ADDR64: [[ZERORSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[ZERO64]], %subreg.sub0_sub1, [[RSRCFMTLO]], %subreg.sub2, [[RSRCFMTHI]], %subreg.sub3
# ADDR64: [[VADDR64:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[RSRCPTR]].sub0, %subreg.sub0, [[RSRCPTR]].sub1, %subreg.sub1 # ADDR64: [[VADDR64:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[RSRCPTR]].sub0, %subreg.sub0, [[RSRCPTR]].sub1, %subreg.sub1
# ADDR64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_ADDR64 [[VADDR64]], [[ZERORSRC]], 0, 0, 0, 0, 0, implicit $exec # ADDR64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_ADDR64 [[VADDR64]], [[ZERORSRC]], 0, 0, 0, 0, 0, 0, implicit $exec
--- ---
name: offset name: offset
liveins: liveins:
- { reg: '$vgpr0', virtual-reg: '%0' } - { reg: '$vgpr0', virtual-reg: '%0' }
- { reg: '$vgpr1', virtual-reg: '%1' } - { reg: '$vgpr1', virtual-reg: '%1' }
- { reg: '$vgpr2', virtual-reg: '%2' } - { reg: '$vgpr2', virtual-reg: '%2' }
- { reg: '$vgpr3', virtual-reg: '%3' } - { reg: '$vgpr3', virtual-reg: '%3' }
- { reg: '$vgpr4_vgpr5', virtual-reg: '%4' } - { reg: '$vgpr4_vgpr5', virtual-reg: '%4' }
- { reg: '$sgpr30_sgpr31', virtual-reg: '%5' } - { reg: '$sgpr30_sgpr31', virtual-reg: '%5' }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31
%5:sreg_64 = COPY $sgpr30_sgpr31 %5:sreg_64 = COPY $sgpr30_sgpr31
%4:vreg_64 = COPY $vgpr4_vgpr5 %4:vreg_64 = COPY $vgpr4_vgpr5
%3:vgpr_32 = COPY $vgpr3 %3:vgpr_32 = COPY $vgpr3
%2:vgpr_32 = COPY $vgpr2 %2:vgpr_32 = COPY $vgpr2
%1:vgpr_32 = COPY $vgpr1 %1:vgpr_32 = COPY $vgpr1
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3 %6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFSET killed %6, 0, 0, 0, 0, 0, implicit $exec %7:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFSET killed %6, 0, 0, 0, 0, 0, 0, implicit $exec
$sgpr30_sgpr31 = COPY %5 $sgpr30_sgpr31 = COPY %5
$vgpr0 = COPY %7 $vgpr0 = COPY %7
S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0 S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
... ...

llvm/trunk/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir

Show First 20 Lines • Show All 99 Lines • ▼ Show 20 Linesliveins:
- { reg: '$sgpr0_sgpr1', virtual-reg: '%3' } - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' }
body: | body: |
bb.0.bb: bb.0.bb:
successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000) successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000)
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
%3 = COPY $sgpr0_sgpr1 %3 = COPY $sgpr0_sgpr1
%2 = COPY $vgpr0 %2 = COPY $vgpr0
%7 = S_LOAD_DWORDX2_IMM %3, 9, 0 %7 = S_LOAD_DWORDX2_IMM %3, 9, 0, 0
%8 = S_LOAD_DWORDX2_IMM %3, 11, 0 %8 = S_LOAD_DWORDX2_IMM %3, 11, 0, 0
%6 = COPY %7 %6 = COPY %7
%9 = S_MOV_B32 0 %9 = S_MOV_B32 0
%10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1 %10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1
%0 = COPY %10 %0 = COPY %10
%11 = COPY %10.sub0 %11 = COPY %10.sub0
%12 = COPY %10.sub1 %12 = COPY %10.sub1
%13 = COPY %8.sub0 %13 = COPY %8.sub0
%14 = COPY %8.sub1 %14 = COPY %8.sub1
Show All 14 Lines bb.1.bb1:
%23 = S_MOV_B32 2 %23 = S_MOV_B32 2
%24 = S_LSHL_B64 %0, killed %23, implicit-def dead $scc %24 = S_LSHL_B64 %0, killed %23, implicit-def dead $scc
%25 = S_MOV_B32 61440 %25 = S_MOV_B32 61440
%26 = S_MOV_B32 0 %26 = S_MOV_B32 0
%27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1 %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1
%28 = REG_SEQUENCE %6, 17, killed %27, 18 %28 = REG_SEQUENCE %6, 17, killed %27, 18
%29 = V_MOV_B32_e32 0, implicit $exec %29 = V_MOV_B32_e32 0, implicit $exec
%30 = COPY %24 %30 = COPY %24
BUFFER_STORE_DWORD_ADDR64 killed %29, killed %30, killed %28, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 killed %29, killed %30, killed %28, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.bb2: bb.2.bb2:
SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: const_to_sgpr_multiple_use name: const_to_sgpr_multiple_use
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesliveins:
- { reg: '$sgpr0_sgpr1', virtual-reg: '%3' } - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' }
body: | body: |
bb.0.bb: bb.0.bb:
successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000) successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000)
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
%3 = COPY $sgpr0_sgpr1 %3 = COPY $sgpr0_sgpr1
%2 = COPY $vgpr0 %2 = COPY $vgpr0
%7 = S_LOAD_DWORDX2_IMM %3, 9, 0 %7 = S_LOAD_DWORDX2_IMM %3, 9, 0, 0
%8 = S_LOAD_DWORDX2_IMM %3, 11, 0 %8 = S_LOAD_DWORDX2_IMM %3, 11, 0, 0
%9 = S_LOAD_DWORDX2_IMM %3, 13, 0 %9 = S_LOAD_DWORDX2_IMM %3, 13, 0, 0
%6 = COPY %7 %6 = COPY %7
%10 = S_MOV_B32 0 %10 = S_MOV_B32 0
%11 = REG_SEQUENCE %2, %subreg.sub0, killed %10, %subreg.sub1 %11 = REG_SEQUENCE %2, %subreg.sub0, killed %10, %subreg.sub1
%0 = COPY %11 %0 = COPY %11
%12 = COPY %11.sub0 %12 = COPY %11.sub0
%13 = COPY %11.sub1 %13 = COPY %11.sub1
%14 = COPY %8.sub0 %14 = COPY %8.sub0
%15 = COPY %8.sub1 %15 = COPY %8.sub1
Show All 21 Lines bb.1.bb1:
%32 = S_MOV_B32 2 %32 = S_MOV_B32 2
%33 = S_LSHL_B64 %0, killed %32, implicit-def dead $scc %33 = S_LSHL_B64 %0, killed %32, implicit-def dead $scc
%34 = S_MOV_B32 61440 %34 = S_MOV_B32 61440
%35 = S_MOV_B32 0 %35 = S_MOV_B32 0
%36 = REG_SEQUENCE killed %35, %subreg.sub0, killed %34, %subreg.sub1 %36 = REG_SEQUENCE killed %35, %subreg.sub0, killed %34, %subreg.sub1
%37 = REG_SEQUENCE %6, 17, killed %36, 18 %37 = REG_SEQUENCE %6, 17, killed %36, 18
%38 = V_MOV_B32_e32 0, implicit $exec %38 = V_MOV_B32_e32 0, implicit $exec
%39 = COPY %33 %39 = COPY %33
BUFFER_STORE_DWORD_ADDR64 killed %38, killed %39, killed %37, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 killed %38, killed %39, killed %37, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.bb2: bb.2.bb2:
SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: const_to_sgpr_subreg name: const_to_sgpr_subreg
Show All 40 Linesliveins:
- { reg: '$sgpr0_sgpr1', virtual-reg: '%3' } - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' }
body: | body: |
bb.0.bb: bb.0.bb:
successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000) successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000)
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
%3 = COPY $sgpr0_sgpr1 %3 = COPY $sgpr0_sgpr1
%2 = COPY $vgpr0 %2 = COPY $vgpr0
%7 = S_LOAD_DWORDX2_IMM %3, 9, 0 %7 = S_LOAD_DWORDX2_IMM %3, 9, 0, 0
%8 = S_LOAD_DWORDX2_IMM %3, 11, 0 %8 = S_LOAD_DWORDX2_IMM %3, 11, 0, 0
%6 = COPY %7 %6 = COPY %7
%9 = S_MOV_B32 0 %9 = S_MOV_B32 0
%10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1 %10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1
%0 = COPY %10 %0 = COPY %10
%11 = COPY %10.sub0 %11 = COPY %10.sub0
%12 = COPY %10.sub1 %12 = COPY %10.sub1
%13 = COPY %8.sub0 %13 = COPY %8.sub0
%14 = COPY %8.sub1 %14 = COPY %8.sub1
Show All 14 Lines bb.1.bb1:
%23 = S_MOV_B32 2 %23 = S_MOV_B32 2
%24 = S_LSHL_B64 %0, killed %23, implicit-def dead $scc %24 = S_LSHL_B64 %0, killed %23, implicit-def dead $scc
%25 = S_MOV_B32 61440 %25 = S_MOV_B32 61440
%26 = S_MOV_B32 0 %26 = S_MOV_B32 0
%27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1 %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1
%28 = REG_SEQUENCE %6, 17, killed %27, 18 %28 = REG_SEQUENCE %6, 17, killed %27, 18
%29 = V_MOV_B32_e32 0, implicit $exec %29 = V_MOV_B32_e32 0, implicit $exec
%30 = COPY %24 %30 = COPY %24
BUFFER_STORE_DWORD_ADDR64 killed %29, killed %30, killed %28, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 killed %29, killed %30, killed %28, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.bb2: bb.2.bb2:
SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Lines bb.0.main_body:
SI_MASK_BRANCH %bb.2, implicit $exec SI_MASK_BRANCH %bb.2, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1.if: bb.1.if:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.end: bb.2.end:
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# CHECK-LABEL: name: optimize_if_and_saveexec{{$}} # CHECK-LABEL: name: optimize_if_and_saveexec{{$}}
# CHECK: $sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec # CHECK: $sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
# CHECK-NEXT: SI_MASK_BRANCH # CHECK-NEXT: SI_MASK_BRANCH
Show All 12 Lines bb.0.main_body:
SI_MASK_BRANCH %bb.2, implicit $exec SI_MASK_BRANCH %bb.2, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1.if: bb.1.if:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.end: bb.2.end:
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# CHECK-LABEL: name: optimize_if_or_saveexec{{$}} # CHECK-LABEL: name: optimize_if_or_saveexec{{$}}
# CHECK: $sgpr0_sgpr1 = S_OR_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec # CHECK: $sgpr0_sgpr1 = S_OR_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
# CHECK-NEXT: SI_MASK_BRANCH # CHECK-NEXT: SI_MASK_BRANCH
Show All 12 Lines bb.0.main_body:
SI_MASK_BRANCH %bb.2, implicit $exec SI_MASK_BRANCH %bb.2, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1.if: bb.1.if:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.end: bb.2.end:
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# CHECK-LABEL: name: optimize_if_and_saveexec_xor_valu_middle # CHECK-LABEL: name: optimize_if_and_saveexec_xor_valu_middle
# CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc # CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
# CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, undef $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec # CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, undef $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
# CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc # CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
# CHECK-NEXT: $exec = COPY killed $sgpr2_sgpr3 # CHECK-NEXT: $exec = COPY killed $sgpr2_sgpr3
# CHECK-NEXT: SI_MASK_BRANCH # CHECK-NEXT: SI_MASK_BRANCH
name: optimize_if_and_saveexec_xor_valu_middle name: optimize_if_and_saveexec_xor_valu_middle
liveins: liveins:
- { reg: '$vgpr0' } - { reg: '$vgpr0' }
body: | body: |
bb.0.main_body: bb.0.main_body:
liveins: $vgpr0 liveins: $vgpr0
$sgpr0_sgpr1 = COPY $exec $sgpr0_sgpr1 = COPY $exec
$vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
$vgpr0 = V_MOV_B32_e32 4, implicit $exec $vgpr0 = V_MOV_B32_e32 4, implicit $exec
$sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
BUFFER_STORE_DWORD_OFFSET $vgpr0, undef $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET $vgpr0, undef $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
$sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
$exec = S_MOV_B64_term killed $sgpr2_sgpr3 $exec = S_MOV_B64_term killed $sgpr2_sgpr3
SI_MASK_BRANCH %bb.2, implicit $exec SI_MASK_BRANCH %bb.2, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1.if: bb.1.if:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.end: bb.2.end:
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# CHECK-LABEL: name: optimize_if_and_saveexec_xor_wrong_reg{{$}} # CHECK-LABEL: name: optimize_if_and_saveexec_xor_wrong_reg{{$}}
# CHECK: $sgpr0_sgpr1 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc # CHECK: $sgpr0_sgpr1 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
# CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 undef $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc # CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 undef $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
# CHECK-NEXT: $exec = COPY $sgpr0_sgpr1 # CHECK-NEXT: $exec = COPY $sgpr0_sgpr1
Show All 13 Lines bb.0.main_body:
$sgpr0_sgpr1 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc $sgpr0_sgpr1 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
$sgpr0_sgpr1 = S_XOR_B64 undef $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc $sgpr0_sgpr1 = S_XOR_B64 undef $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
$exec = S_MOV_B64_term $sgpr0_sgpr1 $exec = S_MOV_B64_term $sgpr0_sgpr1
SI_MASK_BRANCH %bb.2, implicit $exec SI_MASK_BRANCH %bb.2, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1.if: bb.1.if:
liveins: $sgpr0_sgpr1 , $sgpr4_sgpr5_sgpr6_sgpr7 liveins: $sgpr0_sgpr1 , $sgpr4_sgpr5_sgpr6_sgpr7
$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.end: bb.2.end:
liveins: $vgpr0, $sgpr0_sgpr1, $sgpr4_sgpr5_sgpr6_sgpr7 liveins: $vgpr0, $sgpr0_sgpr1, $sgpr4_sgpr5_sgpr6_sgpr7
$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# CHECK-LABEL: name: optimize_if_and_saveexec_xor_modify_copy_to_exec{{$}} # CHECK-LABEL: name: optimize_if_and_saveexec_xor_modify_copy_to_exec{{$}}
# CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc # CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
# CHECK-NEXT: $sgpr2_sgpr3 = S_OR_B64 killed $sgpr2_sgpr3, 1, implicit-def $scc # CHECK-NEXT: $sgpr2_sgpr3 = S_OR_B64 killed $sgpr2_sgpr3, 1, implicit-def $scc
# CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc # CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
Show All 17 Lines bb.0.main_body:
SI_MASK_BRANCH %bb.2, implicit $exec SI_MASK_BRANCH %bb.2, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1.if: bb.1.if:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.end: bb.2.end:
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
$sgpr0 = S_MOV_B32 0 $sgpr0 = S_MOV_B32 0
$sgpr1 = S_MOV_B32 1 $sgpr1 = S_MOV_B32 1
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# CHECK-LABEL: name: optimize_if_and_saveexec_xor_live_out_setexec{{$}} # CHECK-LABEL: name: optimize_if_and_saveexec_xor_live_out_setexec{{$}}
# CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc # CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
# CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc # CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
# CHECK-NEXT: $exec = COPY $sgpr2_sgpr3 # CHECK-NEXT: $exec = COPY $sgpr2_sgpr3
Show All 14 Lines bb.0.main_body:
SI_MASK_BRANCH %bb.2, implicit $exec SI_MASK_BRANCH %bb.2, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1.if: bb.1.if:
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
S_SLEEP 0, implicit $sgpr2_sgpr3 S_SLEEP 0, implicit $sgpr2_sgpr3
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.end: bb.2.end:
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
# CHECK-LABEL: name: optimize_if_unknown_saveexec{{$}} # CHECK-LABEL: name: optimize_if_unknown_saveexec{{$}}
# CHECK: $sgpr0_sgpr1 = COPY $exec # CHECK: $sgpr0_sgpr1 = COPY $exec
# CHECK: $sgpr2_sgpr3 = S_LSHR_B64 $sgpr0_sgpr1, killed $vcc_lo, implicit-def $scc # CHECK: $sgpr2_sgpr3 = S_LSHR_B64 $sgpr0_sgpr1, killed $vcc_lo, implicit-def $scc
# CHECK-NEXT: $exec = COPY killed $sgpr2_sgpr3 # CHECK-NEXT: $exec = COPY killed $sgpr2_sgpr3
Show All 14 Lines bb.0.main_body:
SI_MASK_BRANCH %bb.2, implicit $exec SI_MASK_BRANCH %bb.2, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1.if: bb.1.if:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.end: bb.2.end:
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# CHECK-LABEL: name: optimize_if_andn2_saveexec{{$}} # CHECK-LABEL: name: optimize_if_andn2_saveexec{{$}}
# CHECK: $sgpr0_sgpr1 = S_ANDN2_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec # CHECK: $sgpr0_sgpr1 = S_ANDN2_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
# CHECK-NEXT: SI_MASK_BRANCH # CHECK-NEXT: SI_MASK_BRANCH
Show All 12 Lines bb.0.main_body:
SI_MASK_BRANCH %bb.2, implicit $exec SI_MASK_BRANCH %bb.2, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1.if: bb.1.if:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.end: bb.2.end:
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# CHECK-LABEL: name: optimize_if_andn2_saveexec_no_commute{{$}} # CHECK-LABEL: name: optimize_if_andn2_saveexec_no_commute{{$}}
# CHECK: $sgpr2_sgpr3 = S_ANDN2_B64 killed $vcc, $sgpr0_sgpr1, implicit-def $scc # CHECK: $sgpr2_sgpr3 = S_ANDN2_B64 killed $vcc, $sgpr0_sgpr1, implicit-def $scc
# CHECK-NEXT: $exec = COPY killed $sgpr2_sgpr3 # CHECK-NEXT: $exec = COPY killed $sgpr2_sgpr3
# CHECK-NEXT: SI_MASK_BRANCH %bb.2, implicit $exec # CHECK-NEXT: SI_MASK_BRANCH %bb.2, implicit $exec
Show All 12 Lines bb.0.main_body:
SI_MASK_BRANCH %bb.2, implicit $exec SI_MASK_BRANCH %bb.2, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1.if: bb.1.if:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.end: bb.2.end:
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# A read from exec copy subreg prevents optimization # A read from exec copy subreg prevents optimization
# CHECK-LABEL: name: if_and_xor_read_exec_copy_subreg{{$}} # CHECK-LABEL: name: if_and_xor_read_exec_copy_subreg{{$}}
# CHECK: $sgpr0_sgpr1 = COPY $exec # CHECK: $sgpr0_sgpr1 = COPY $exec
# CHECK-NEXT: $sgpr4 = S_MOV_B32 $sgpr1 # CHECK-NEXT: $sgpr4 = S_MOV_B32 $sgpr1
Show All 14 Lines bb.0.main_body:
SI_MASK_BRANCH %bb.2, implicit $exec SI_MASK_BRANCH %bb.2, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1.if: bb.1.if:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.end: bb.2.end:
liveins: $vgpr0, $sgpr0_sgpr1 liveins: $vgpr0, $sgpr0_sgpr1
$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir

Show All 21 Lines
body: | body: |
; CHECK-LABEL: name: scavenge_register_position ; CHECK-LABEL: name: scavenge_register_position
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $sgpr4, $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK: liveins: $sgpr4, $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: $sgpr5 = COPY $sgpr4 ; CHECK: $sgpr5 = COPY $sgpr4
; CHECK: $sgpr6 = S_ADD_U32 $sgpr5, 524288, implicit-def $scc ; CHECK: $sgpr6 = S_ADD_U32 $sgpr5, 524288, implicit-def $scc
; CHECK: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr6, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.0, align 8192, addrspace 5) ; CHECK: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr6, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.0, align 8192, addrspace 5)
; CHECK: S_BRANCH %bb.1 ; CHECK: S_BRANCH %bb.1
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: liveins: $sgpr5, $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK: liveins: $sgpr5, $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: $sgpr4 = S_ADD_U32 $sgpr5, 524288, implicit-def $scc ; CHECK: $sgpr4 = S_ADD_U32 $sgpr5, 524288, implicit-def $scc
; CHECK: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr4, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.0, align 8192, addrspace 5) ; CHECK: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr4, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.0, align 8192, addrspace 5)
; CHECK: S_ENDPGM 0, implicit $vgpr0 ; CHECK: S_ENDPGM 0, implicit $vgpr0
bb.0: bb.0:
$vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5) $vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
$vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5) $vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
S_ENDPGM 0, implicit $vgpr0 S_ENDPGM 0, implicit $vgpr0
... ...

llvm/trunk/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir

# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefix=GFX9 %s # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefix=GFX9 %s
# GFX9-LABEL: name: diffoporder_add # GFX9-LABEL: name: diffoporder_add
# GFX9: %{{[0-9]+}}:vreg_64 = GLOBAL_LOAD_DWORDX2 %{{[0-9]+}}, -2048, 0, 0 # GFX9: %{{[0-9]+}}:vreg_64 = GLOBAL_LOAD_DWORDX2 %{{[0-9]+}}, -2048, 0, 0
# GFX9: %{{[0-9]+}}:vreg_64 = GLOBAL_LOAD_DWORDX2 %{{[0-9]+}}, 0, 0, 0 # GFX9: %{{[0-9]+}}:vreg_64 = GLOBAL_LOAD_DWORDX2 %{{[0-9]+}}, 0, 0, 0
name: diffoporder_add name: diffoporder_add
body: | body: |
bb.0.entry: bb.0.entry:
%0:sgpr_64 = COPY $sgpr0_sgpr1 %0:sgpr_64 = COPY $sgpr0_sgpr1
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0 %1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
%3:sreg_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99 %3:sreg_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99
%4:sreg_32_xm0 = COPY $sgpr101 %4:sreg_32_xm0 = COPY $sgpr101
%5:sreg_32_xm0 = S_MOV_B32 0 %5:sreg_32_xm0 = S_MOV_B32 0
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3 $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
$sgpr4 = COPY %4 $sgpr4 = COPY %4
$vgpr0 = V_MOV_B32_e32 0, implicit $exec $vgpr0 = V_MOV_B32_e32 0, implicit $exec
%6:vreg_64 = COPY $vgpr0_vgpr1 %6:vreg_64 = COPY $vgpr0_vgpr1
%7:vgpr_32 = V_AND_B32_e32 255, %6.sub0, implicit $exec %7:vgpr_32 = V_AND_B32_e32 255, %6.sub0, implicit $exec
Show All 9 Lines bb.0.entry:
%19:vreg_64 = REG_SEQUENCE %14, %subreg.sub0, %17, %subreg.sub1 %19:vreg_64 = REG_SEQUENCE %14, %subreg.sub0, %17, %subreg.sub1
%20:vreg_64 = V_LSHLREV_B64 3, %9, implicit $exec %20:vreg_64 = V_LSHLREV_B64 3, %9, implicit $exec
%21:vgpr_32, %22:sreg_64_xexec = V_ADD_I32_e64 %14, %20.sub0, 0, implicit $exec %21:vgpr_32, %22:sreg_64_xexec = V_ADD_I32_e64 %14, %20.sub0, 0, implicit $exec
%23:vgpr_32, dead %24:sreg_64_xexec = V_ADDC_U32_e64 %17, %20.sub1, killed %22, 0, implicit $exec %23:vgpr_32, dead %24:sreg_64_xexec = V_ADDC_U32_e64 %17, %20.sub1, killed %22, 0, implicit $exec
%25:sgpr_32 = S_MOV_B32 4096 %25:sgpr_32 = S_MOV_B32 4096
%26:vgpr_32, %27:sreg_64_xexec = V_ADD_I32_e64 %25, %21, 0, implicit $exec %26:vgpr_32, %27:sreg_64_xexec = V_ADD_I32_e64 %25, %21, 0, implicit $exec
%28:vgpr_32, dead %29:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %27, 0, implicit $exec %28:vgpr_32, dead %29:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %27, 0, implicit $exec
%30:vreg_64 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1 %30:vreg_64 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1
%31:vreg_64 = GLOBAL_LOAD_DWORDX2 %30, 0, 0, 0, implicit $exec %31:vreg_64 = GLOBAL_LOAD_DWORDX2 %30, 0, 0, 0, 0, implicit $exec
%32:sgpr_32 = S_MOV_B32 6144 %32:sgpr_32 = S_MOV_B32 6144
%33:vgpr_32, %34:sreg_64_xexec = V_ADD_I32_e64 %21, %32, 0, implicit $exec %33:vgpr_32, %34:sreg_64_xexec = V_ADD_I32_e64 %21, %32, 0, implicit $exec
%35:vgpr_32, dead %36:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %34, 0, implicit $exec %35:vgpr_32, dead %36:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %34, 0, implicit $exec
%37:vreg_64 = REG_SEQUENCE %33, %subreg.sub0, %35, %subreg.sub1 %37:vreg_64 = REG_SEQUENCE %33, %subreg.sub0, %35, %subreg.sub1
%38:vreg_64 = GLOBAL_LOAD_DWORDX2 %37, 0, 0, 0, implicit $exec %38:vreg_64 = GLOBAL_LOAD_DWORDX2 %37, 0, 0, 0, 0, implicit $exec
... ...
--- ---
# GFX9-LABEL: name: LowestInMiddle # GFX9-LABEL: name: LowestInMiddle
# GFX9: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11200 # GFX9: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11200
# GFX9: [[BASE_LO:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_5:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 %{{[0-9]+}}, [[S_MOV_B32_1]] # GFX9: [[BASE_LO:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_5:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 %{{[0-9]+}}, [[S_MOV_B32_1]]
# GFX9: [[BASE_HI:%[0-9]+]]:vgpr_32, dead %{{[0-9]+}}:sreg_64_xexec = V_ADDC_U32_e64 %{{[0-9]+}}, 0, killed [[V_ADD_I32_e64_5]] # GFX9: [[BASE_HI:%[0-9]+]]:vgpr_32, dead %{{[0-9]+}}:sreg_64_xexec = V_ADDC_U32_e64 %{{[0-9]+}}, 0, killed [[V_ADD_I32_e64_5]]
# GFX9: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BASE_LO]], %subreg.sub0, [[BASE_HI]], %subreg.sub1 # GFX9: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BASE_LO]], %subreg.sub0, [[BASE_HI]], %subreg.sub1
# GFX9: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[REG_SEQUENCE2]], -3200, 0, 0 # GFX9: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[REG_SEQUENCE2]], -3200, 0, 0
# #
# GFX9: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 6400 # GFX9: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 6400
# GFX9: [[BASE1_LO:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_7:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 %{{[0-9]+}}, [[S_MOV_B32_2]] # GFX9: [[BASE1_LO:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_7:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 %{{[0-9]+}}, [[S_MOV_B32_2]]
# GFX9: [[BASE1_HI:%[0-9]+]]:vgpr_32, dead %{{[0-9]+}}:sreg_64_xexec = V_ADDC_U32_e64 %{{[0-9]+}}, 0, killed [[V_ADD_I32_e64_7]] # GFX9: [[BASE1_HI:%[0-9]+]]:vgpr_32, dead %{{[0-9]+}}:sreg_64_xexec = V_ADDC_U32_e64 %{{[0-9]+}}, 0, killed [[V_ADD_I32_e64_7]]
# GFX9: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BASE1_LO]], %subreg.sub0, [[BASE1_HI]], %subreg.sub1 # GFX9: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BASE1_LO]], %subreg.sub0, [[BASE1_HI]], %subreg.sub1
# GFX9: [[GLOBAL_LOAD_DWORDX2_1:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[REG_SEQUENCE3]], 0, 0, 0, # GFX9: [[GLOBAL_LOAD_DWORDX2_1:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[REG_SEQUENCE3]], 0, 0, 0,
# GFX9: [[GLOBAL_LOAD_DWORDX2_2:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[REG_SEQUENCE2]], 0, 0, 0, # GFX9: [[GLOBAL_LOAD_DWORDX2_2:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[REG_SEQUENCE2]], 0, 0, 0,
name: LowestInMiddle name: LowestInMiddle
body: | body: |
bb.0.entry: bb.0.entry:
%0:sgpr_64 = COPY $sgpr0_sgpr1 %0:sgpr_64 = COPY $sgpr0_sgpr1
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0 %1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
%3:sreg_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99 %3:sreg_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99
%4:sreg_32_xm0 = COPY $sgpr101 %4:sreg_32_xm0 = COPY $sgpr101
%5:sreg_32_xm0 = S_MOV_B32 0 %5:sreg_32_xm0 = S_MOV_B32 0
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3 $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
$sgpr4 = COPY %4 $sgpr4 = COPY %4
$vgpr0 = V_MOV_B32_e32 0, implicit $exec $vgpr0 = V_MOV_B32_e32 0, implicit $exec
%6:vreg_64 = COPY $vgpr0_vgpr1 %6:vreg_64 = COPY $vgpr0_vgpr1
%7:vgpr_32 = V_AND_B32_e32 255, %6.sub0, implicit $exec %7:vgpr_32 = V_AND_B32_e32 255, %6.sub0, implicit $exec
Show All 9 Lines bb.0.entry:
%19:vreg_64 = REG_SEQUENCE %14, %subreg.sub0, %17, %subreg.sub1 %19:vreg_64 = REG_SEQUENCE %14, %subreg.sub0, %17, %subreg.sub1
%20:vreg_64 = V_LSHLREV_B64 3, %9, implicit $exec %20:vreg_64 = V_LSHLREV_B64 3, %9, implicit $exec
%21:vgpr_32, %22:sreg_64_xexec = V_ADD_I32_e64 %14, %20.sub0, 0, implicit $exec %21:vgpr_32, %22:sreg_64_xexec = V_ADD_I32_e64 %14, %20.sub0, 0, implicit $exec
%23:vgpr_32, dead %24:sreg_64_xexec = V_ADDC_U32_e64 %17, %20.sub1, killed %22, 0, implicit $exec %23:vgpr_32, dead %24:sreg_64_xexec = V_ADDC_U32_e64 %17, %20.sub1, killed %22, 0, implicit $exec
%25:sgpr_32 = S_MOV_B32 8000 %25:sgpr_32 = S_MOV_B32 8000
%26:vgpr_32, %27:sreg_64_xexec = V_ADD_I32_e64 %21, %25, 0, implicit $exec %26:vgpr_32, %27:sreg_64_xexec = V_ADD_I32_e64 %21, %25, 0, implicit $exec
%28:vgpr_32, dead %29:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %27, 0, implicit $exec %28:vgpr_32, dead %29:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %27, 0, implicit $exec
%30:vreg_64 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1 %30:vreg_64 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1
%31:vreg_64 = GLOBAL_LOAD_DWORDX2 %30, 0, 0, 0, implicit $exec %31:vreg_64 = GLOBAL_LOAD_DWORDX2 %30, 0, 0, 0, 0, implicit $exec
%32:sgpr_32 = S_MOV_B32 6400 %32:sgpr_32 = S_MOV_B32 6400
%33:vgpr_32, %34:sreg_64_xexec = V_ADD_I32_e64 %21, %32, 0, implicit $exec %33:vgpr_32, %34:sreg_64_xexec = V_ADD_I32_e64 %21, %32, 0, implicit $exec
%35:vgpr_32, dead %36:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %34, 0, implicit $exec %35:vgpr_32, dead %36:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %34, 0, implicit $exec
%37:vreg_64 = REG_SEQUENCE %33, %subreg.sub0, %35, %subreg.sub1 %37:vreg_64 = REG_SEQUENCE %33, %subreg.sub0, %35, %subreg.sub1
%38:vreg_64 = GLOBAL_LOAD_DWORDX2 %37, 0, 0, 0, implicit $exec %38:vreg_64 = GLOBAL_LOAD_DWORDX2 %37, 0, 0, 0, 0, implicit $exec
%39:sgpr_32 = S_MOV_B32 11200 %39:sgpr_32 = S_MOV_B32 11200
%40:vgpr_32, %41:sreg_64_xexec = V_ADD_I32_e64 %21, %39, 0, implicit $exec %40:vgpr_32, %41:sreg_64_xexec = V_ADD_I32_e64 %21, %39, 0, implicit $exec
%42:vgpr_32, dead %43:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %41, 0, implicit $exec %42:vgpr_32, dead %43:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %41, 0, implicit $exec
%44:vreg_64 = REG_SEQUENCE %40, %subreg.sub0, %42, %subreg.sub1 %44:vreg_64 = REG_SEQUENCE %40, %subreg.sub0, %42, %subreg.sub1
%45:vreg_64 = GLOBAL_LOAD_DWORDX2 %44, 0, 0, 0, implicit $exec %45:vreg_64 = GLOBAL_LOAD_DWORDX2 %44, 0, 0, 0, 0, implicit $exec
... ...
--- ---
# GFX9-LABEL: name: NegativeDistance # GFX9-LABEL: name: NegativeDistance
# GFX9: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 10240 # GFX9: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 10240
# GFX9: [[V_ADD_I32_e64_4:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_5:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 %{{[0-9]+}}, [[S_MOV_B32_1]] # GFX9: [[V_ADD_I32_e64_4:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_5:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 %{{[0-9]+}}, [[S_MOV_B32_1]]
# GFX9: [[BASE_HI:%[0-9]+]]:vgpr_32, dead %{{[0-9]+}}:sreg_64_xexec = V_ADDC_U32_e64 %{{[0-9]+}}, 0, killed [[V_ADD_I32_e64_5]] # GFX9: [[BASE_HI:%[0-9]+]]:vgpr_32, dead %{{[0-9]+}}:sreg_64_xexec = V_ADDC_U32_e64 %{{[0-9]+}}, 0, killed [[V_ADD_I32_e64_5]]
# GFX9: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_4]], %subreg.sub0, [[BASE_HI]], %subreg.sub1 # GFX9: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_I32_e64_4]], %subreg.sub0, [[BASE_HI]], %subreg.sub1
# GFX9: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[REG_SEQUENCE2]], -4096, 0, 0 # GFX9: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[REG_SEQUENCE2]], -4096, 0, 0
# GFX9: [[GLOBAL_LOAD_DWORDX2_1:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[REG_SEQUENCE2]], -2048, 0, 0 # GFX9: [[GLOBAL_LOAD_DWORDX2_1:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[REG_SEQUENCE2]], -2048, 0, 0
# GFX9: [[GLOBAL_LOAD_DWORDX2_2:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[REG_SEQUENCE2]], 0, 0, 0 # GFX9: [[GLOBAL_LOAD_DWORDX2_2:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[REG_SEQUENCE2]], 0, 0, 0
name: NegativeDistance name: NegativeDistance
body: | body: |
bb.0.entry: bb.0.entry:
%0:sgpr_64 = COPY $sgpr0_sgpr1 %0:sgpr_64 = COPY $sgpr0_sgpr1
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0 %1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
%3:sreg_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99 %3:sreg_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99
%4:sreg_32_xm0 = COPY $sgpr101 %4:sreg_32_xm0 = COPY $sgpr101
%5:sreg_32_xm0 = S_MOV_B32 0 %5:sreg_32_xm0 = S_MOV_B32 0
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3 $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
$sgpr4 = COPY %4 $sgpr4 = COPY %4
$vgpr0 = V_MOV_B32_e32 0, implicit $exec $vgpr0 = V_MOV_B32_e32 0, implicit $exec
%6:vreg_64 = COPY $vgpr0_vgpr1 %6:vreg_64 = COPY $vgpr0_vgpr1
%7:vgpr_32 = V_AND_B32_e32 255, %6.sub0, implicit $exec %7:vgpr_32 = V_AND_B32_e32 255, %6.sub0, implicit $exec
Show All 9 Lines bb.0.entry:
%19:vreg_64 = REG_SEQUENCE %14, %subreg.sub0, %17, %subreg.sub1 %19:vreg_64 = REG_SEQUENCE %14, %subreg.sub0, %17, %subreg.sub1
%20:vreg_64 = V_LSHLREV_B64 3, %9, implicit $exec %20:vreg_64 = V_LSHLREV_B64 3, %9, implicit $exec
%21:vgpr_32, %22:sreg_64_xexec = V_ADD_I32_e64 %14, %20.sub0, 0, implicit $exec %21:vgpr_32, %22:sreg_64_xexec = V_ADD_I32_e64 %14, %20.sub0, 0, implicit $exec
%23:vgpr_32, dead %24:sreg_64_xexec = V_ADDC_U32_e64 %17, %20.sub1, killed %22, 0, implicit $exec %23:vgpr_32, dead %24:sreg_64_xexec = V_ADDC_U32_e64 %17, %20.sub1, killed %22, 0, implicit $exec
%25:sgpr_32 = S_MOV_B32 6144 %25:sgpr_32 = S_MOV_B32 6144
%26:vgpr_32, %27:sreg_64_xexec = V_ADD_I32_e64 %21, %25, 0, implicit $exec %26:vgpr_32, %27:sreg_64_xexec = V_ADD_I32_e64 %21, %25, 0, implicit $exec
%28:vgpr_32, dead %29:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %27, 0, implicit $exec %28:vgpr_32, dead %29:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %27, 0, implicit $exec
%30:vreg_64 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1 %30:vreg_64 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1
%31:vreg_64 = GLOBAL_LOAD_DWORDX2 %30, 0, 0, 0, implicit $exec %31:vreg_64 = GLOBAL_LOAD_DWORDX2 %30, 0, 0, 0, 0, implicit $exec
%32:sgpr_32 = S_MOV_B32 8192 %32:sgpr_32 = S_MOV_B32 8192
%33:vgpr_32, %34:sreg_64_xexec = V_ADD_I32_e64 %21, %32, 0, implicit $exec %33:vgpr_32, %34:sreg_64_xexec = V_ADD_I32_e64 %21, %32, 0, implicit $exec
%35:vgpr_32, dead %36:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %34, 0, implicit $exec %35:vgpr_32, dead %36:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %34, 0, implicit $exec
%37:vreg_64 = REG_SEQUENCE %33, %subreg.sub0, %35, %subreg.sub1 %37:vreg_64 = REG_SEQUENCE %33, %subreg.sub0, %35, %subreg.sub1
%38:vreg_64 = GLOBAL_LOAD_DWORDX2 %37, 0, 0, 0, implicit $exec %38:vreg_64 = GLOBAL_LOAD_DWORDX2 %37, 0, 0, 0, 0, implicit $exec
%39:sgpr_32 = S_MOV_B32 10240 %39:sgpr_32 = S_MOV_B32 10240
%40:vgpr_32, %41:sreg_64_xexec = V_ADD_I32_e64 %21, %39, 0, implicit $exec %40:vgpr_32, %41:sreg_64_xexec = V_ADD_I32_e64 %21, %39, 0, implicit $exec
%42:vgpr_32, dead %43:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %41, 0, implicit $exec %42:vgpr_32, dead %43:sreg_64_xexec = V_ADDC_U32_e64 %23, 0, killed %41, 0, implicit $exec
%44:vreg_64 = REG_SEQUENCE %40, %subreg.sub0, %42, %subreg.sub1 %44:vreg_64 = REG_SEQUENCE %40, %subreg.sub0, %42, %subreg.sub1
%45:vreg_64 = GLOBAL_LOAD_DWORDX2 %44, 0, 0, 0, implicit $exec %45:vreg_64 = GLOBAL_LOAD_DWORDX2 %44, 0, 0, 0, 0, implicit $exec
... ...
--- ---
# Tests for a successful compilation. # Tests for a successful compilation.
name: assert_hit name: assert_hit
body: | body: |
bb.0.entry: bb.0.entry:
%0:sgpr_64 = COPY $sgpr0_sgpr1 %0:sgpr_64 = COPY $sgpr0_sgpr1
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0 %1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
%3:sreg_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99 %3:sreg_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99
%4:sreg_32_xm0 = COPY $sgpr101 %4:sreg_32_xm0 = COPY $sgpr101
%5:sreg_32_xm0 = S_MOV_B32 0 %5:sreg_32_xm0 = S_MOV_B32 0
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3 $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
$sgpr4 = COPY %4 $sgpr4 = COPY %4
$vgpr0 = V_MOV_B32_e32 0, implicit $exec $vgpr0 = V_MOV_B32_e32 0, implicit $exec
%6:vreg_64 = COPY $vgpr0_vgpr1 %6:vreg_64 = COPY $vgpr0_vgpr1
%7:vgpr_32 = V_AND_B32_e32 255, %6.sub0, implicit $exec %7:vgpr_32 = V_AND_B32_e32 255, %6.sub0, implicit $exec
Show All 10 Linesbody: |
%20:vreg_64 = V_LSHLREV_B64 3, %9, implicit $exec %20:vreg_64 = V_LSHLREV_B64 3, %9, implicit $exec
%21:vgpr_32, %22:sreg_64_xexec = V_ADD_I32_e64 %14, %20.sub0, 0, implicit $exec %21:vgpr_32, %22:sreg_64_xexec = V_ADD_I32_e64 %14, %20.sub0, 0, implicit $exec
%23:vgpr_32, dead %24:sreg_64_xexec = V_ADDC_U32_e64 %17, %20.sub1, killed %22, 0, implicit $exec %23:vgpr_32, dead %24:sreg_64_xexec = V_ADDC_U32_e64 %17, %20.sub1, killed %22, 0, implicit $exec
%25:sgpr_32 = S_MOV_B32 6144 %25:sgpr_32 = S_MOV_B32 6144
%26:vgpr_32, %27:sreg_64_xexec = V_ADD_I32_e64 %21, %25, 0, implicit $exec %26:vgpr_32, %27:sreg_64_xexec = V_ADD_I32_e64 %21, %25, 0, implicit $exec
%28:vgpr_32, dead %29:sreg_64_xexec = V_ADDC_U32_e64 %23, 4294967295, killed %27, 0, implicit $exec %28:vgpr_32, dead %29:sreg_64_xexec = V_ADDC_U32_e64 %23, 4294967295, killed %27, 0, implicit $exec
%30:vreg_64 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1 %30:vreg_64 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1
%31:vreg_64 = GLOBAL_LOAD_DWORDX2 %30, 0, 0, 0, implicit $exec %31:vreg_64 = GLOBAL_LOAD_DWORDX2 %30, 0, 0, 0, 0, implicit $exec
... ...

llvm/trunk/test/CodeGen/AMDGPU/readlane_exec0.mir

Show All 16 Lines bb.0:
$sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 killed $vcc, implicit-def $exec, implicit-def $scc, implicit $exec $sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 killed $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
SI_MASK_BRANCH %bb.2, implicit $exec SI_MASK_BRANCH %bb.2, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
$sgpr10 = V_READFIRSTLANE_B32 $vgpr2, implicit $exec $sgpr10 = V_READFIRSTLANE_B32 $vgpr2, implicit $exec
$sgpr11 = V_READFIRSTLANE_B32 $vgpr3, implicit $exec $sgpr11 = V_READFIRSTLANE_B32 $vgpr3, implicit $exec
$sgpr10 = S_LOAD_DWORD_IMM killed $sgpr10_sgpr11, 0, 0 $sgpr10 = S_LOAD_DWORD_IMM killed $sgpr10_sgpr11, 0, 0, 0
S_WAITCNT 127 S_WAITCNT 127
$vgpr0 = V_XOR_B32_e32 killed $sgpr10, killed $vgpr0, implicit $exec $vgpr0 = V_XOR_B32_e32 killed $sgpr10, killed $vgpr0, implicit $exec
bb.2: bb.2:
$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
... ...

llvm/trunk/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir

Show First 20 Lines • Show All 179 Lines • ▼ Show 20 Linesbody: |
bb.27: bb.27:
S_CBRANCH_SCC1 %bb.32, implicit undef $scc S_CBRANCH_SCC1 %bb.32, implicit undef $scc
S_BRANCH %bb.28 S_BRANCH %bb.28
bb.28: bb.28:
%9 = S_FF1_I32_B32 undef %10 %9 = S_FF1_I32_B32 undef %10
%13 = V_MAD_U32_U24 killed %9, 48, 32, 0, implicit $exec %13 = V_MAD_U32_U24 killed %9, 48, 32, 0, implicit $exec
%45 = BUFFER_LOAD_DWORD_OFFEN killed %13, undef %15, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4) %45 = BUFFER_LOAD_DWORD_OFFEN killed %13, undef %15, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
%46 = V_AND_B32_e32 1, killed %45, implicit $exec %46 = V_AND_B32_e32 1, killed %45, implicit $exec
%21 = S_BUFFER_LOAD_DWORD_SGPR undef %22, undef %23, 0 :: (dereferenceable invariant load 4) %21 = S_BUFFER_LOAD_DWORD_SGPR undef %22, undef %23, 0, 0 :: (dereferenceable invariant load 4)
%25 = V_CMP_GE_F32_e64 0, 0, 0, killed %21, 0, implicit $exec %25 = V_CMP_GE_F32_e64 0, 0, 0, killed %21, 0, implicit $exec
%26 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed %25, implicit $exec %26 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed %25, implicit $exec
%62 = IMPLICIT_DEF %62 = IMPLICIT_DEF
bb.29: bb.29:
successors: %bb.30(0x30000000), %bb.36(0x50000000) successors: %bb.30(0x30000000), %bb.36(0x50000000)
%53 = COPY killed %62 %53 = COPY killed %62
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/regcoal-subrange-join.mir

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines bb.0:
%15 = COPY killed $sgpr5 %15 = COPY killed $sgpr5
%12 = COPY killed $sgpr2 %12 = COPY killed $sgpr2
%17 = S_MOV_B32 1 %17 = S_MOV_B32 1
undef %18.sub1 = COPY %17 undef %18.sub1 = COPY %17
%0 = COPY %18 %0 = COPY %18
%0.sub0 = COPY killed %12 %0.sub0 = COPY killed %12
%21 = COPY killed %18 %21 = COPY killed %18
%21.sub0 = COPY killed %15 %21.sub0 = COPY killed %15
%22 = S_LOAD_DWORD_IMM killed %21, 2, 0 %22 = S_LOAD_DWORD_IMM killed %21, 2, 0, 0
%23 = S_MOV_B32 491436 %23 = S_MOV_B32 491436
undef %24.sub0 = COPY killed %22 undef %24.sub0 = COPY killed %22
%24.sub1 = COPY killed %23 %24.sub1 = COPY killed %23
%25 = S_LOAD_DWORDX4_IMM killed %24, 0, 0 %25 = S_LOAD_DWORDX4_IMM killed %24, 0, 0, 0
%1 = COPY killed %25 %1 = COPY killed %25
%26 = S_LOAD_DWORDX2_IMM %0, 2, 0 %26 = S_LOAD_DWORDX2_IMM %0, 2, 0, 0
dead %27 = S_LOAD_DWORD_IMM killed %26, 0, 0 dead %27 = S_LOAD_DWORD_IMM killed %26, 0, 0, 0
S_CBRANCH_SCC0 %bb.1, implicit undef $scc S_CBRANCH_SCC0 %bb.1, implicit undef $scc
bb.5: bb.5:
%58 = COPY killed %1 %58 = COPY killed %1
%59 = COPY killed %17 %59 = COPY killed %17
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.1: bb.1:
Show All 9 Lines bb.1:
%28 = S_MOV_B32 0 %28 = S_MOV_B32 0
%2 = COPY killed %56 %2 = COPY killed %56
%58 = COPY killed %2 %58 = COPY killed %2
%59 = COPY killed %28 %59 = COPY killed %28
bb.2: bb.2:
%4 = COPY killed %59 %4 = COPY killed %59
%3 = COPY killed %58 %3 = COPY killed %58
%39 = S_LOAD_DWORDX2_IMM killed %0, 6, 0 %39 = S_LOAD_DWORDX2_IMM killed %0, 6, 0, 0
%40 = S_LOAD_DWORD_IMM killed %39, 0, 0 %40 = S_LOAD_DWORD_IMM killed %39, 0, 0, 0
%43 = V_MOV_B32_e32 -1102263091, implicit $exec %43 = V_MOV_B32_e32 -1102263091, implicit $exec
%60 = COPY killed %4 %60 = COPY killed %4
%61 = COPY killed %3 %61 = COPY killed %3
bb.3: bb.3:
successors: %bb.3, %bb.4 successors: %bb.3, %bb.4
%7 = COPY killed %61 %7 = COPY killed %61
Show All 21 Lines

llvm/trunk/test/CodeGen/AMDGPU/regcoalesce-dbg.mir

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Linesliveins:
- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
- { reg: '$vgpr0', virtual-reg: '%3' } - { reg: '$vgpr0', virtual-reg: '%3' }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY killed $vgpr0 %3 = COPY killed $vgpr0
%0 = COPY killed $sgpr0_sgpr1 %0 = COPY killed $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%5 = S_LOAD_DWORD_IMM killed %0, 13, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) %5 = S_LOAD_DWORD_IMM killed %0, 13, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
%18 = V_ASHRREV_I32_e32 31, %3, implicit $exec %18 = V_ASHRREV_I32_e32 31, %3, implicit $exec
undef %19.sub0 = COPY killed %3 undef %19.sub0 = COPY killed %3
%19.sub1 = COPY killed %18 %19.sub1 = COPY killed %18
%10 = S_MOV_B32 61440 %10 = S_MOV_B32 61440
%11 = S_MOV_B32 0 %11 = S_MOV_B32 0
DBG_VALUE debug-use %11, debug-use $noreg, !1, !8, debug-location !9 DBG_VALUE debug-use %11, debug-use $noreg, !1, !8, debug-location !9
undef %12.sub0 = COPY killed %11 undef %12.sub0 = COPY killed %11
%12.sub1 = COPY killed %10 %12.sub1 = COPY killed %10
undef %13.sub0_sub1 = COPY killed %4 undef %13.sub0_sub1 = COPY killed %4
%13.sub2_sub3 = COPY killed %12 %13.sub2_sub3 = COPY killed %12
%20 = V_LSHL_B64 killed %19, 2, implicit $exec %20 = V_LSHL_B64 killed %19, 2, implicit $exec
%16 = COPY killed %5 %16 = COPY killed %5
BUFFER_STORE_DWORD_ADDR64 killed %16, killed %20, killed %13, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out) BUFFER_STORE_DWORD_ADDR64 killed %16, killed %20, killed %13, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir

Show All 10 Lines
body: | body: |
bb.0: bb.0:
successors: %bb.1, %bb.2 successors: %bb.1, %bb.2
%21:vgpr_32 = V_TRUNC_F32_e32 undef %22:vgpr_32, implicit $exec %21:vgpr_32 = V_TRUNC_F32_e32 undef %22:vgpr_32, implicit $exec
%23:vgpr_32 = V_CVT_U32_F32_e32 killed %21, implicit $exec %23:vgpr_32 = V_CVT_U32_F32_e32 killed %21, implicit $exec
%108:vgpr_32 = V_LSHRREV_B32_e32 4, killed %23, implicit $exec %108:vgpr_32 = V_LSHRREV_B32_e32 4, killed %23, implicit $exec
undef %109.sub1:vreg_128 = COPY %108 undef %109.sub1:vreg_128 = COPY %108
%28:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %29:sreg_128, 3044, 0 :: (dereferenceable invariant load 4) %28:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %29:sreg_128, 3044, 0, 0 :: (dereferenceable invariant load 4)
S_CMP_EQ_U32 killed %28, 0, implicit-def $scc S_CMP_EQ_U32 killed %28, 0, implicit-def $scc
S_CBRANCH_SCC0 %bb.2, implicit killed $scc S_CBRANCH_SCC0 %bb.2, implicit killed $scc
bb.1: bb.1:
%138:vreg_128 = COPY killed %109 %138:vreg_128 = COPY killed %109
S_BRANCH %bb.9 S_BRANCH %bb.9
bb.2: bb.2:
Show All 14 Lines bb.5:
%110:vreg_128 = COPY killed %136 %110:vreg_128 = COPY killed %136
dead %32:sreg_32_xm0 = S_MOV_B32 0 dead %32:sreg_32_xm0 = S_MOV_B32 0
%111:vreg_128 = COPY %110 %111:vreg_128 = COPY %110
%111.sub3:vreg_128 = COPY undef %32 %111.sub3:vreg_128 = COPY undef %32
S_CBRANCH_SCC1 %bb.8, implicit undef $scc S_CBRANCH_SCC1 %bb.8, implicit undef $scc
S_BRANCH %bb.6 S_BRANCH %bb.6
bb.6: bb.6:
%36:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %37:sreg_128, 2708, 0 :: (dereferenceable invariant load 4) %36:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %37:sreg_128, 2708, 0, 0 :: (dereferenceable invariant load 4)
%39:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, killed %110.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 0, 0, 0, implicit $exec %39:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, killed %110.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 0, 0, 0, implicit $exec
%40:vgpr_32 = V_MAD_F32 0, %111.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 0, 0, 0, implicit $exec %40:vgpr_32 = V_MAD_F32 0, %111.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 0, 0, 0, implicit $exec
%41:vgpr_32 = V_MUL_F32_e64 0, 0, 0, killed %40, 1, 0, implicit $exec %41:vgpr_32 = V_MUL_F32_e64 0, 0, 0, killed %40, 1, 0, implicit $exec
%43:vgpr_32 = V_MUL_F32_e32 0, %39, implicit $exec %43:vgpr_32 = V_MUL_F32_e32 0, %39, implicit $exec
%44:vgpr_32 = COPY killed %43 %44:vgpr_32 = COPY killed %43
%44:vgpr_32 = V_MAC_F32_e32 0, killed %41, %44, implicit $exec %44:vgpr_32 = V_MAC_F32_e32 0, killed %41, %44, implicit $exec
%47:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec %47:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
%46:vgpr_32 = COPY killed %47 %46:vgpr_32 = COPY killed %47
Show All 19 Lines bb.7:
%117.sub2:vreg_128 = COPY killed %56 %117.sub2:vreg_128 = COPY killed %56
%64:sreg_64 = S_AND_B64 $exec, %50, implicit-def dead $scc %64:sreg_64 = S_AND_B64 $exec, %50, implicit-def dead $scc
$vcc = COPY killed %64 $vcc = COPY killed %64
%137:vreg_128 = COPY killed %117 %137:vreg_128 = COPY killed %117
S_CBRANCH_VCCNZ %bb.7, implicit killed $vcc S_CBRANCH_VCCNZ %bb.7, implicit killed $vcc
S_BRANCH %bb.8 S_BRANCH %bb.8
bb.8: bb.8:
dead %66:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %67:sreg_128, 2704, 0 :: (dereferenceable invariant load 4) dead %66:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %67:sreg_128, 2704, 0, 0 :: (dereferenceable invariant load 4)
%138:vreg_128 = COPY killed %111 %138:vreg_128 = COPY killed %111
bb.9: bb.9:
%113:vreg_128 = COPY killed %138 %113:vreg_128 = COPY killed %138
S_CBRANCH_SCC1 %bb.18, implicit undef $scc S_CBRANCH_SCC1 %bb.18, implicit undef $scc
S_BRANCH %bb.10 S_BRANCH %bb.10
bb.10: bb.10:
▲ Show 20 Lines • Show All 105 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines bb.2:
undef %13.sub0 = COPY %8 undef %13.sub0 = COPY %8
%13.sub1 = COPY %8 %13.sub1 = COPY %8
%13.sub2 = COPY killed %8 %13.sub2 = COPY killed %8
%0 = COPY killed %13 %0 = COPY killed %13
%17 = COPY killed %0 %17 = COPY killed %0
bb.3: bb.3:
%1 = COPY killed %17 %1 = COPY killed %17
FLAT_STORE_DWORD undef %10, %1.sub2, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD undef %10, %1.sub2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%14 = COPY %1.sub1 %14 = COPY %1.sub1
%16 = COPY killed %1.sub0 %16 = COPY killed %1.sub0
undef %15.sub0 = COPY killed %16 undef %15.sub0 = COPY killed %16
%15.sub1 = COPY killed %14 %15.sub1 = COPY killed %14
FLAT_STORE_DWORDX2 undef %11, killed %15, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORDX2 undef %11, killed %15, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Make sure others uses after the mac are properly handled and not # Make sure others uses after the mac are properly handled and not
# left unreplaced due to iterator issues from substituteRegister. # left unreplaced due to iterator issues from substituteRegister.
# GCN-LABEL: name: vreg_does_not_dominate # GCN-LABEL: name: vreg_does_not_dominate
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines bb.1:
successors: %bb.2 successors: %bb.2
%6.sub3 = V_ADD_F32_e32 undef %3, undef %3, implicit $exec %6.sub3 = V_ADD_F32_e32 undef %3, undef %3, implicit $exec
%6.sub0 = V_ADD_F32_e64 0, 0, 0, 0, 0, 0, implicit $exec %6.sub0 = V_ADD_F32_e64 0, 0, 0, 0, 0, 0, implicit $exec
%6.sub1 = V_ADD_F32_e32 %6.sub1, %6.sub1, implicit $exec %6.sub1 = V_ADD_F32_e32 %6.sub1, %6.sub1, implicit $exec
%6.sub2 = COPY %6.sub0 %6.sub2 = COPY %6.sub0
bb.2: bb.2:
BUFFER_STORE_DWORD_OFFEN %6.sub3, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 12, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFEN %6.sub3, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 12, 0, 0, 0, 0, implicit $exec
BUFFER_STORE_DWORD_OFFEN %6.sub2, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 8, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFEN %6.sub2, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 8, 0, 0, 0, 0, implicit $exec
BUFFER_STORE_DWORD_OFFEN %6.sub1, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFEN %6.sub1, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, 0, 0, implicit $exec
BUFFER_STORE_DWORD_OFFEN %6.sub0, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFEN %6.sub0, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
$sgpr30_sgpr31 = COPY %5 $sgpr30_sgpr31 = COPY %5
S_SETPC_B64_return $sgpr30_sgpr31 S_SETPC_B64_return $sgpr30_sgpr31
... ...
# GCN-LABEL: name: inf_loop_tied_operand # GCN-LABEL: name: inf_loop_tied_operand
# GCN: bb.0: # GCN: bb.0:
# GCN-NEXT: undef %2.sub0:vreg_128 = V_MAC_F32_e32 1073741824, undef %0:vgpr_32, undef %2.sub0, implicit $exec # GCN-NEXT: undef %2.sub0:vreg_128 = V_MAC_F32_e32 1073741824, undef %0:vgpr_32, undef %2.sub0, implicit $exec
Show All 15 Lines

llvm/trunk/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
name: basic_insert_dcache_wb name: basic_insert_dcache_wb
tracksRegLiveness: false tracksRegLiveness: false
machineFunctionInfo: machineFunctionInfo:
isEntryFunction: true isEntryFunction: true
body: | body: |
bb.0: bb.0:
S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0 S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Already has an explicitly requested flush after the last store. # Already has an explicitly requested flush after the last store.
# CHECK-LABEL: name: explicit_flush_after # CHECK-LABEL: name: explicit_flush_after
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: S_STORE_DWORD # CHECK-NEXT: S_STORE_DWORD
# CHECK-NEXT: S_DCACHE_WB # CHECK-NEXT: S_DCACHE_WB
# CHECK-NEXT: S_ENDPGM 0 # CHECK-NEXT: S_ENDPGM 0
name: explicit_flush_after name: explicit_flush_after
tracksRegLiveness: false tracksRegLiveness: false
machineFunctionInfo: machineFunctionInfo:
isEntryFunction: true isEntryFunction: true
body: | body: |
bb.0: bb.0:
S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0 S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0, 0
S_DCACHE_WB S_DCACHE_WB
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# Already has an explicitly requested flush before the last store. # Already has an explicitly requested flush before the last store.
# CHECK-LABEL: name: explicit_flush_before # CHECK-LABEL: name: explicit_flush_before
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: S_DCACHE_WB # CHECK-NEXT: S_DCACHE_WB
# CHECK-NEXT: S_STORE_DWORD # CHECK-NEXT: S_STORE_DWORD
# CHECK-NEXT: S_DCACHE_WB # CHECK-NEXT: S_DCACHE_WB
# CHECK-NEXT: S_ENDPGM 0 # CHECK-NEXT: S_ENDPGM 0
name: explicit_flush_before name: explicit_flush_before
tracksRegLiveness: false tracksRegLiveness: false
machineFunctionInfo: machineFunctionInfo:
isEntryFunction: true isEntryFunction: true
body: | body: |
bb.0: bb.0:
S_DCACHE_WB S_DCACHE_WB
S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0 S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# CHECK-LABEL: no_scalar_store # CHECK-LABEL: no_scalar_store
# CHECK: bb.0 # CHECK: bb.0
# CHECK-NEXT: S_ENDPGM 0 # CHECK-NEXT: S_ENDPGM 0
name: no_scalar_store name: no_scalar_store
tracksRegLiveness: false tracksRegLiveness: false
Show All 18 Lines
name: multi_block_store name: multi_block_store
tracksRegLiveness: false tracksRegLiveness: false
machineFunctionInfo: machineFunctionInfo:
isEntryFunction: true isEntryFunction: true
body: | body: |
bb.0: bb.0:
S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0 S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
bb.1: bb.1:
S_STORE_DWORD_SGPR undef $sgpr4, undef $sgpr6_sgpr7, undef $m0, 0 S_STORE_DWORD_SGPR undef $sgpr4, undef $sgpr6_sgpr7, undef $m0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
... ...
# This one should be able to omit the flush in the storeless block but # This one should be able to omit the flush in the storeless block but
# this isn't handled now. # this isn't handled now.
# CHECK-LABEL: name: one_block_store # CHECK-LABEL: name: one_block_store
Show All 11 Lines
machineFunctionInfo: machineFunctionInfo:
isEntryFunction: true isEntryFunction: true
body: | body: |
bb.0: bb.0:
S_ENDPGM 0 S_ENDPGM 0
bb.1: bb.1:
S_STORE_DWORD_SGPR undef $sgpr4, undef $sgpr6_sgpr7, undef $m0, 0 S_STORE_DWORD_SGPR undef $sgpr4, undef $sgpr6_sgpr7, undef $m0, 0, 0
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# CHECK-LABEL: name: si_return # CHECK-LABEL: name: si_return
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: S_STORE_DWORD # CHECK-NEXT: S_STORE_DWORD
# CHECK-NEXT: S_WAITCNT # CHECK-NEXT: S_WAITCNT
# CHECK-NEXT: S_DCACHE_WB # CHECK-NEXT: S_DCACHE_WB
# CHECK-NEXT: SI_RETURN # CHECK-NEXT: SI_RETURN
name: si_return name: si_return
tracksRegLiveness: false tracksRegLiveness: false
machineFunctionInfo: machineFunctionInfo:
isEntryFunction: true isEntryFunction: true
body: | body: |
bb.0: bb.0:
S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0 S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0, 0
SI_RETURN_TO_EPILOG undef $vgpr0 SI_RETURN_TO_EPILOG undef $vgpr0
... ...

llvm/trunk/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir

Show All 17 LinesmachineFunctionInfo:
waveLimiter: true waveLimiter: true
body: | body: |
; CHECK-LABEL: name: only_dbg_value_sched_region ; CHECK-LABEL: name: only_dbg_value_sched_region
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[DEF]], 0, 0, 0, implicit $exec ; CHECK: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[DEF]], 0, 0, 0, 0, implicit $exec
; CHECK: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 8, 0, 0, implicit $exec ; CHECK: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 8, 0, 0, 0, implicit $exec
; CHECK: undef %4.sub1:vreg_64 = V_ADD_U32_e32 [[COPY]], [[COPY]], implicit $exec ; CHECK: undef %4.sub1:vreg_64 = V_ADD_U32_e32 [[COPY]], [[COPY]], implicit $exec
; CHECK: %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec ; CHECK: %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec
; CHECK: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; CHECK: [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; CHECK: [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: undef %11.sub1:vreg_64 = IMPLICIT_DEF ; CHECK: undef %11.sub1:vreg_64 = IMPLICIT_DEF
; CHECK: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; CHECK: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF ; CHECK: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; CHECK: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[GLOBAL_LOAD_DWORDX2_]] ; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[GLOBAL_LOAD_DWORDX2_]]
; CHECK: undef %6.sub0:vreg_64 = V_ADD_F32_e32 [[DEF]].sub0, [[COPY1]].sub0, implicit $exec ; CHECK: undef %6.sub0:vreg_64 = V_ADD_F32_e32 [[DEF]].sub0, [[COPY1]].sub0, implicit $exec
; CHECK: dead undef %6.sub1:vreg_64 = V_ADD_F32_e32 [[DEF]].sub1, [[COPY1]].sub0, implicit $exec ; CHECK: dead undef %6.sub1:vreg_64 = V_ADD_F32_e32 [[DEF]].sub1, [[COPY1]].sub0, implicit $exec
; CHECK: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY1]], 0, 0, 0, implicit $exec ; CHECK: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY1]], 0, 0, 0, 0, implicit $exec
; CHECK: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; CHECK: undef %19.sub0:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD1]], [[GLOBAL_LOAD_DWORDX2_]].sub0, implicit $exec ; CHECK: undef %19.sub0:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD1]], [[GLOBAL_LOAD_DWORDX2_]].sub0, implicit $exec
; CHECK: %19.sub1:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD]], [[GLOBAL_LOAD_DWORD]], implicit $exec ; CHECK: %19.sub1:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD]], [[GLOBAL_LOAD_DWORD]], implicit $exec
; CHECK: GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, implicit $exec ; CHECK: GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, 0, implicit $exec
; CHECK: %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF1]], 0, 0, 0, implicit $exec ; CHECK: %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF1]], 0, 0, 0, 0, implicit $exec
; CHECK: [[DEF2]].sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF3]], 0, 0, 0, implicit $exec ; CHECK: [[DEF2]].sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF3]], 0, 0, 0, 0, implicit $exec
; CHECK: dead %20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, 0, implicit $exec ; CHECK: dead %20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, 0, 0, implicit $exec
; CHECK: dead %21:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF4]], 0, 0, 0, implicit $exec ; CHECK: dead %21:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF4]], 0, 0, 0, 0, implicit $exec
; CHECK: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 2, [[DEF2]], implicit $exec ; CHECK: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 2, [[DEF2]], implicit $exec
; CHECK: dead %22:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF5]], 0, 0, 0, implicit $exec ; CHECK: dead %22:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF5]], 0, 0, 0, 0, implicit $exec
; CHECK: S_NOP 0, implicit [[DEF7]], implicit [[V_LSHLREV_B64_]].sub0, implicit [[DEF6]], implicit [[V_MOV_B32_e32_]] ; CHECK: S_NOP 0, implicit [[DEF7]], implicit [[V_LSHLREV_B64_]].sub0, implicit [[DEF6]], implicit [[V_MOV_B32_e32_]]
; CHECK: GLOBAL_STORE_DWORD [[DEF5]], [[V_MOV_B32_e32_1]], 0, 0, 0, implicit $exec ; CHECK: GLOBAL_STORE_DWORD [[DEF5]], [[V_MOV_B32_e32_1]], 0, 0, 0, 0, implicit $exec
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: S_SETREG_IMM32_B32 0, 1 ; CHECK: S_SETREG_IMM32_B32 0, 1
; CHECK: DBG_VALUE ; CHECK: DBG_VALUE
; CHECK: DBG_VALUE ; CHECK: DBG_VALUE
; CHECK: DBG_VALUE ; CHECK: DBG_VALUE
; CHECK: S_SETREG_IMM32_B32 0, 1 ; CHECK: S_SETREG_IMM32_B32 0, 1
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: S_NOP 0, implicit [[COPY]] ; CHECK: S_NOP 0, implicit [[COPY]]
; CHECK: S_NOP 0, implicit [[DEF8]] ; CHECK: S_NOP 0, implicit [[DEF8]]
; CHECK: S_ENDPGM 0 ; CHECK: S_ENDPGM 0
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%1:vreg_64 = IMPLICIT_DEF %1:vreg_64 = IMPLICIT_DEF
%2:vreg_64 = GLOBAL_LOAD_DWORDX2 %1, 0, 0, 0, implicit $exec %2:vreg_64 = GLOBAL_LOAD_DWORDX2 %1, 0, 0, 0, 0, implicit $exec
%3:vgpr_32 = GLOBAL_LOAD_DWORD %1, 8, 0, 0, implicit $exec %3:vgpr_32 = GLOBAL_LOAD_DWORD %1, 8, 0, 0, 0, implicit $exec
undef %4.sub1:vreg_64 = V_ADD_U32_e32 %0, %0, implicit $exec undef %4.sub1:vreg_64 = V_ADD_U32_e32 %0, %0, implicit $exec
%4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec
%5:vreg_64 = COPY %2 %5:vreg_64 = COPY %2
undef %6.sub0:vreg_64 = V_ADD_F32_e32 %1.sub0, %5.sub0, implicit $exec undef %6.sub0:vreg_64 = V_ADD_F32_e32 %1.sub0, %5.sub0, implicit $exec
%6.sub1:vreg_64 = V_ADD_F32_e32 %1.sub1, %5.sub0, implicit $exec %6.sub1:vreg_64 = V_ADD_F32_e32 %1.sub1, %5.sub0, implicit $exec
%7:vgpr_32 = GLOBAL_LOAD_DWORD %5, 0, 0, 0, implicit $exec %7:vgpr_32 = GLOBAL_LOAD_DWORD %5, 0, 0, 0, 0, implicit $exec
%8:vreg_64 = IMPLICIT_DEF %8:vreg_64 = IMPLICIT_DEF
%9:vreg_64 = IMPLICIT_DEF %9:vreg_64 = IMPLICIT_DEF
%10:vreg_64 = IMPLICIT_DEF %10:vreg_64 = IMPLICIT_DEF
undef %11.sub1:vreg_64 = IMPLICIT_DEF undef %11.sub1:vreg_64 = IMPLICIT_DEF
%12:vgpr_32 = IMPLICIT_DEF %12:vgpr_32 = IMPLICIT_DEF
%13:vgpr_32 = IMPLICIT_DEF %13:vgpr_32 = IMPLICIT_DEF
%14:vreg_64 = IMPLICIT_DEF %14:vreg_64 = IMPLICIT_DEF
%15:vreg_64 = IMPLICIT_DEF %15:vreg_64 = IMPLICIT_DEF
%16:vgpr_32 = IMPLICIT_DEF %16:vgpr_32 = IMPLICIT_DEF
%17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec %17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
undef %19.sub0:vreg_64 = V_ADD_F32_e32 %7, %2.sub0, implicit $exec undef %19.sub0:vreg_64 = V_ADD_F32_e32 %7, %2.sub0, implicit $exec
%19.sub1:vreg_64 = V_ADD_F32_e32 %3, %3, implicit $exec %19.sub1:vreg_64 = V_ADD_F32_e32 %3, %3, implicit $exec
GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, implicit $exec GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, 0, implicit $exec
%11.sub0:vreg_64 = GLOBAL_LOAD_DWORD %9, 0, 0, 0, implicit $exec %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD %9, 0, 0, 0, 0, implicit $exec
%8.sub0:vreg_64 = GLOBAL_LOAD_DWORD %10, 0, 0, 0, implicit $exec %8.sub0:vreg_64 = GLOBAL_LOAD_DWORD %10, 0, 0, 0, 0, implicit $exec
%20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, 0, implicit $exec %20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, 0, 0, implicit $exec
%21:vgpr_32 = GLOBAL_LOAD_DWORD %14, 0, 0, 0, implicit $exec %21:vgpr_32 = GLOBAL_LOAD_DWORD %14, 0, 0, 0, 0, implicit $exec
%22:vgpr_32 = GLOBAL_LOAD_DWORD %15, 0, 0, 0, implicit $exec %22:vgpr_32 = GLOBAL_LOAD_DWORD %15, 0, 0, 0, 0, implicit $exec
%23:vreg_64 = V_LSHLREV_B64 2, %8, implicit $exec %23:vreg_64 = V_LSHLREV_B64 2, %8, implicit $exec
S_NOP 0, implicit %13, implicit %23.sub0, implicit %12, implicit %17 S_NOP 0, implicit %13, implicit %23.sub0, implicit %12, implicit %17
GLOBAL_STORE_DWORD %15, %18, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORD %15, %18, 0, 0, 0, 0, implicit $exec
bb.1: bb.1:
S_SETREG_IMM32_B32 0, 1 S_SETREG_IMM32_B32 0, 1
DBG_VALUE DBG_VALUE
DBG_VALUE DBG_VALUE
DBG_VALUE DBG_VALUE
S_SETREG_IMM32_B32 0, 1 S_SETREG_IMM32_B32 0, 1
bb.2: bb.2:
S_NOP 0, implicit %0 S_NOP 0, implicit %0
S_NOP 0, implicit %16 S_NOP 0, implicit %16
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir

Show First 20 Lines • Show All 194 Lines • ▼ Show 20 Linesbody: |
bb.0.bb: bb.0.bb:
liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr32, $sgpr101 liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr32, $sgpr101
%4:sgpr_64 = COPY $sgpr6_sgpr7 %4:sgpr_64 = COPY $sgpr6_sgpr7
%3:sgpr_64 = COPY $sgpr4_sgpr5 %3:sgpr_64 = COPY $sgpr4_sgpr5
%2:vgpr_32 = COPY $vgpr2 %2:vgpr_32 = COPY $vgpr2
%1:vgpr_32 = COPY $vgpr1 %1:vgpr_32 = COPY $vgpr1
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%5:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %5:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 0, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%6:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 8, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %6:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 8, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%7:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 16, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %7:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 16, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%8:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 24, 0 %8:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 24, 0, 0
%9:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 32, 0 %9:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 32, 0, 0
%10:sreg_64_xexec = S_LOAD_DWORDX2_IMM %3, 4, 0 %10:sreg_64_xexec = S_LOAD_DWORDX2_IMM %3, 4, 0, 0
%11:sreg_32_xm0 = S_LSHR_B32 %10.sub0, 16, implicit-def dead $scc %11:sreg_32_xm0 = S_LSHR_B32 %10.sub0, 16, implicit-def dead $scc
%12:sreg_32_xm0 = S_MUL_I32 %11, %10.sub1 %12:sreg_32_xm0 = S_MUL_I32 %11, %10.sub1
%13:vgpr_32 = V_MUL_LO_I32 0, %0, implicit $exec %13:vgpr_32 = V_MUL_LO_I32 0, %0, implicit $exec
%14:vgpr_32 = V_MUL_LO_I32 %1, %10.sub1, implicit $exec %14:vgpr_32 = V_MUL_LO_I32 %1, %10.sub1, implicit $exec
%15:vgpr_32 = V_ADD_I32_e32 0, %13, implicit-def dead $vcc, implicit $exec %15:vgpr_32 = V_ADD_I32_e32 0, %13, implicit-def dead $vcc, implicit $exec
%16:vgpr_32 = V_ADD_I32_e32 0, %15, implicit-def dead $vcc, implicit $exec %16:vgpr_32 = V_ADD_I32_e32 0, %15, implicit-def dead $vcc, implicit $exec
%17:vgpr_32 = IMPLICIT_DEF %17:vgpr_32 = IMPLICIT_DEF
%18:sreg_64 = S_MOV_B64 0 %18:sreg_64 = S_MOV_B64 0
%19:sreg_32_xm0_xexec = IMPLICIT_DEF %19:sreg_32_xm0_xexec = IMPLICIT_DEF
%20:vgpr_32 = V_ADD_I32_e32 %19, %0, implicit-def dead $vcc, implicit $exec %20:vgpr_32 = V_ADD_I32_e32 %19, %0, implicit-def dead $vcc, implicit $exec
%21:vreg_64, dead %22:sreg_64 = V_MAD_I64_I32 %20, 12, %7, 0, implicit $exec %21:vreg_64, dead %22:sreg_64 = V_MAD_I64_I32 %20, 12, %7, 0, implicit $exec
%23:vgpr_32 = GLOBAL_LOAD_DWORD %21, 4, 0, 0, implicit $exec %23:vgpr_32 = GLOBAL_LOAD_DWORD %21, 4, 0, 0, 0, implicit $exec
%24:vreg_64, dead %25:sreg_64 = V_MAD_I64_I32 %20, 48, %8, 0, implicit $exec %24:vreg_64, dead %25:sreg_64 = V_MAD_I64_I32 %20, 48, %8, 0, implicit $exec
%26:vreg_128 = IMPLICIT_DEF %26:vreg_128 = IMPLICIT_DEF
undef %27.sub0:sreg_64_xexec = S_LOAD_DWORD_IMM %6, 0, 0 undef %27.sub0:sreg_64_xexec = S_LOAD_DWORD_IMM %6, 0, 0, 0
%27.sub1:sreg_64_xexec = S_MOV_B32 0 %27.sub1:sreg_64_xexec = S_MOV_B32 0
%28:sreg_64 = S_LSHL_B64 %27, 2, implicit-def dead $scc %28:sreg_64 = S_LSHL_B64 %27, 2, implicit-def dead $scc
undef %29.sub0:sreg_64 = S_ADD_U32 %5.sub0, %28.sub0, implicit-def $scc undef %29.sub0:sreg_64 = S_ADD_U32 %5.sub0, %28.sub0, implicit-def $scc
%29.sub1:sreg_64 = S_ADDC_U32 %5.sub1, %28.sub1, implicit-def dead $scc, implicit killed $scc %29.sub1:sreg_64 = S_ADDC_U32 %5.sub1, %28.sub1, implicit-def dead $scc, implicit killed $scc
undef %30.sub0:sreg_64_xexec = S_LOAD_DWORD_IMM %6, 4, 0 undef %30.sub0:sreg_64_xexec = S_LOAD_DWORD_IMM %6, 4, 0, 0
%27.sub0:sreg_64_xexec = IMPLICIT_DEF %27.sub0:sreg_64_xexec = IMPLICIT_DEF
%31:sreg_64 = S_LSHL_B64 %27, 2, implicit-def dead $scc %31:sreg_64 = S_LSHL_B64 %27, 2, implicit-def dead $scc
%32:sreg_32_xm0 = S_ADD_U32 0, %31.sub0, implicit-def $scc %32:sreg_32_xm0 = S_ADD_U32 0, %31.sub0, implicit-def $scc
%33:sgpr_32 = S_ADDC_U32 %5.sub1, %31.sub1, implicit-def dead $scc, implicit killed $scc %33:sgpr_32 = S_ADDC_U32 %5.sub1, %31.sub1, implicit-def dead $scc, implicit killed $scc
%34:vgpr_32 = IMPLICIT_DEF %34:vgpr_32 = IMPLICIT_DEF
%35:vreg_64, dead %36:sreg_64 = V_MAD_I64_I32 %23, %34, 0, 0, implicit $exec %35:vreg_64, dead %36:sreg_64 = V_MAD_I64_I32 %23, %34, 0, 0, implicit $exec
%37:vreg_64 = GLOBAL_LOAD_DWORDX2 %35, 32, 0, 0, implicit $exec %37:vreg_64 = GLOBAL_LOAD_DWORDX2 %35, 32, 0, 0, 0, implicit $exec
undef %38.sub1:vreg_64 = V_ASHRREV_I32_e32 31, %37.sub0, implicit $exec undef %38.sub1:vreg_64 = V_ASHRREV_I32_e32 31, %37.sub0, implicit $exec
%38.sub0:vreg_64 = COPY %37.sub0 %38.sub0:vreg_64 = COPY %37.sub0
%39:vreg_64 = V_LSHLREV_B64 3, %38, implicit $exec %39:vreg_64 = V_LSHLREV_B64 3, %38, implicit $exec
undef %40.sub0:vreg_64, %41:sreg_64_xexec = V_ADD_I32_e64 0, %39.sub0, 0, implicit $exec undef %40.sub0:vreg_64, %41:sreg_64_xexec = V_ADD_I32_e64 0, %39.sub0, 0, implicit $exec
%42:vgpr_32 = COPY %33 %42:vgpr_32 = COPY %33
%40.sub1:vreg_64, dead %43:sreg_64_xexec = V_ADDC_U32_e64 %42, %39.sub1, %41, 0, implicit $exec %40.sub1:vreg_64, dead %43:sreg_64_xexec = V_ADDC_U32_e64 %42, %39.sub1, %41, 0, implicit $exec
%44:vreg_64 = GLOBAL_LOAD_DWORDX2 %40, 0, 0, 0, implicit $exec :: (load 8 from %ir.tmp34) %44:vreg_64 = GLOBAL_LOAD_DWORDX2 %40, 0, 0, 0, 0, implicit $exec :: (load 8 from %ir.tmp34)
undef %45.sub1:vreg_64 = IMPLICIT_DEF undef %45.sub1:vreg_64 = IMPLICIT_DEF
%45.sub0:vreg_64 = COPY %37.sub1 %45.sub0:vreg_64 = COPY %37.sub1
%46:vreg_64 = V_LSHLREV_B64 3, %45, implicit $exec %46:vreg_64 = V_LSHLREV_B64 3, %45, implicit $exec
undef %47.sub0:vreg_64, %48:sreg_64_xexec = V_ADD_I32_e64 %32, %46.sub0, 0, implicit $exec undef %47.sub0:vreg_64, %48:sreg_64_xexec = V_ADD_I32_e64 %32, %46.sub0, 0, implicit $exec
%49:vgpr_32 = COPY %33 %49:vgpr_32 = COPY %33
%47.sub1:vreg_64, dead %50:sreg_64_xexec = V_ADDC_U32_e64 %49, %46.sub1, %48, 0, implicit $exec %47.sub1:vreg_64, dead %50:sreg_64_xexec = V_ADDC_U32_e64 %49, %46.sub1, %48, 0, implicit $exec
%51:vreg_64 = IMPLICIT_DEF %51:vreg_64 = IMPLICIT_DEF
undef %52.sub0:vreg_64 = GLOBAL_LOAD_DWORD %35, 40, 0, 0, implicit $exec :: (load 4 from %ir.18 + 8) undef %52.sub0:vreg_64 = GLOBAL_LOAD_DWORD %35, 40, 0, 0, 0, implicit $exec :: (load 4 from %ir.18 + 8)
%52.sub1:vreg_64 = IMPLICIT_DEF %52.sub1:vreg_64 = IMPLICIT_DEF
%53:vreg_64 = V_LSHLREV_B64 3, %52, implicit $exec %53:vreg_64 = V_LSHLREV_B64 3, %52, implicit $exec
undef %54.sub0:vreg_64, %55:sreg_64_xexec = V_ADD_I32_e64 0, %53.sub0, 0, implicit $exec undef %54.sub0:vreg_64, %55:sreg_64_xexec = V_ADD_I32_e64 0, %53.sub0, 0, implicit $exec
%56:vgpr_32 = COPY %33 %56:vgpr_32 = COPY %33
%54.sub1:vreg_64, dead %57:sreg_64_xexec = V_ADDC_U32_e64 0, %53.sub1, %55, 0, implicit $exec %54.sub1:vreg_64, dead %57:sreg_64_xexec = V_ADDC_U32_e64 0, %53.sub1, %55, 0, implicit $exec
%58:vreg_64 = IMPLICIT_DEF %58:vreg_64 = IMPLICIT_DEF
%30.sub1:sreg_64_xexec = IMPLICIT_DEF %30.sub1:sreg_64_xexec = IMPLICIT_DEF
%59:sreg_64 = IMPLICIT_DEF %59:sreg_64 = IMPLICIT_DEF
%60:sreg_32_xm0 = S_ADD_U32 %5.sub0, %59.sub0, implicit-def $scc %60:sreg_32_xm0 = S_ADD_U32 %5.sub0, %59.sub0, implicit-def $scc
%61:sgpr_32 = S_ADDC_U32 %5.sub1, %59.sub1, implicit-def dead $scc, implicit killed $scc %61:sgpr_32 = S_ADDC_U32 %5.sub1, %59.sub1, implicit-def dead $scc, implicit killed $scc
%62:vreg_64 = GLOBAL_LOAD_DWORDX2 %35, 0, 0, 0, implicit $exec :: (load 8 from %ir.20, align 4) %62:vreg_64 = GLOBAL_LOAD_DWORDX2 %35, 0, 0, 0, 0, implicit $exec :: (load 8 from %ir.20, align 4)
undef %63.sub1:vreg_64 = V_ASHRREV_I32_e32 31, %62.sub0, implicit $exec undef %63.sub1:vreg_64 = V_ASHRREV_I32_e32 31, %62.sub0, implicit $exec
%63.sub0:vreg_64 = COPY %62.sub0 %63.sub0:vreg_64 = COPY %62.sub0
%64:vreg_64 = IMPLICIT_DEF %64:vreg_64 = IMPLICIT_DEF
undef %65.sub0:vreg_64, %66:sreg_64_xexec = V_ADD_I32_e64 %60, %64.sub0, 0, implicit $exec undef %65.sub0:vreg_64, %66:sreg_64_xexec = V_ADD_I32_e64 %60, %64.sub0, 0, implicit $exec
%67:vgpr_32 = COPY %61 %67:vgpr_32 = COPY %61
%65.sub1:vreg_64, dead %68:sreg_64_xexec = V_ADDC_U32_e64 %67, %64.sub1, %66, 0, implicit $exec %65.sub1:vreg_64, dead %68:sreg_64_xexec = V_ADDC_U32_e64 %67, %64.sub1, %66, 0, implicit $exec
%69:vreg_128 = GLOBAL_LOAD_DWORDX4 %65, 0, 0, 0, implicit $exec :: (load 16 from %ir.tmp58) %69:vreg_128 = GLOBAL_LOAD_DWORDX4 %65, 0, 0, 0, 0, implicit $exec :: (load 16 from %ir.tmp58)
undef %70.sub1:vreg_64 = IMPLICIT_DEF undef %70.sub1:vreg_64 = IMPLICIT_DEF
%70.sub0:vreg_64 = IMPLICIT_DEF %70.sub0:vreg_64 = IMPLICIT_DEF
%71:vreg_64 = IMPLICIT_DEF %71:vreg_64 = IMPLICIT_DEF
undef %72.sub0:vreg_64, %73:sreg_64_xexec = V_ADD_I32_e64 %60, %71.sub0, 0, implicit $exec undef %72.sub0:vreg_64, %73:sreg_64_xexec = V_ADD_I32_e64 %60, %71.sub0, 0, implicit $exec
%74:vgpr_32 = COPY %61 %74:vgpr_32 = COPY %61
%72.sub1:vreg_64, dead %75:sreg_64_xexec = V_ADDC_U32_e64 0, %71.sub1, %73, 0, implicit $exec %72.sub1:vreg_64, dead %75:sreg_64_xexec = V_ADDC_U32_e64 0, %71.sub1, %73, 0, implicit $exec
%76:vreg_128 = GLOBAL_LOAD_DWORDX4 %72, 0, 0, 0, implicit $exec %76:vreg_128 = GLOBAL_LOAD_DWORDX4 %72, 0, 0, 0, 0, implicit $exec
%77:vgpr_32 = IMPLICIT_DEF %77:vgpr_32 = IMPLICIT_DEF
%78:vgpr_32 = IMPLICIT_DEF %78:vgpr_32 = IMPLICIT_DEF
%79:vgpr_32 = V_MUL_F32_e32 0, %77, implicit $exec %79:vgpr_32 = V_MUL_F32_e32 0, %77, implicit $exec
%80:vgpr_32 = IMPLICIT_DEF %80:vgpr_32 = IMPLICIT_DEF
%81:vgpr_32 = IMPLICIT_DEF %81:vgpr_32 = IMPLICIT_DEF
%84:vgpr_32 = IMPLICIT_DEF %84:vgpr_32 = IMPLICIT_DEF
BUFFER_STORE_DWORD_OFFEN %84, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 108, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFEN %84, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 108, 0, 0, 0, 0, implicit $exec
BUFFER_STORE_DWORD_OFFEN %81, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 104, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFEN %81, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 104, 0, 0, 0, 0, implicit $exec
BUFFER_STORE_DWORD_OFFEN %80, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 100, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFEN %80, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 100, 0, 0, 0, 0, implicit $exec
BUFFER_STORE_DWORD_OFFEN %78, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 96, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFEN %78, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 96, 0, 0, 0, 0, implicit $exec
%85:vgpr_32 = IMPLICIT_DEF %85:vgpr_32 = IMPLICIT_DEF
%86:vgpr_32 = IMPLICIT_DEF %86:vgpr_32 = IMPLICIT_DEF
%87:vgpr_32 = IMPLICIT_DEF %87:vgpr_32 = IMPLICIT_DEF
%88:vgpr_32 = IMPLICIT_DEF %88:vgpr_32 = IMPLICIT_DEF
%90:vgpr_32 = IMPLICIT_DEF %90:vgpr_32 = IMPLICIT_DEF
%91:vgpr_32, dead %92:sreg_64 = V_DIV_SCALE_F32 %90, %90, 1065353216, implicit $exec %91:vgpr_32, dead %92:sreg_64 = V_DIV_SCALE_F32 %90, %90, 1065353216, implicit $exec
%95:vgpr_32 = V_FMA_F32 0, 0, 0, 0, 0, undef %93:vgpr_32, 0, 0, implicit $exec %95:vgpr_32 = V_FMA_F32 0, 0, 0, 0, 0, undef %93:vgpr_32, 0, 0, implicit $exec
%96:vgpr_32, %97:sreg_64 = V_DIV_SCALE_F32 1065353216, %90, 1065353216, implicit $exec %96:vgpr_32, %97:sreg_64 = V_DIV_SCALE_F32 1065353216, %90, 1065353216, implicit $exec
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/schedule-regpressure.mir

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 LinesframeInfo:
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr4_sgpr5 liveins: $sgpr4_sgpr5
%1 = COPY $sgpr4_sgpr5 %1 = COPY $sgpr4_sgpr5
%5 = S_LOAD_DWORD_IMM %1, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) %5 = S_LOAD_DWORD_IMM %1, 0, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
$m0 = S_MOV_B32 -1 $m0 = S_MOV_B32 -1
%7 = COPY %5 %7 = COPY %5
%6 = DS_READ_B32 %7, 0, 0, implicit $m0, implicit $exec %6 = DS_READ_B32 %7, 0, 0, implicit $m0, implicit $exec
DS_WRITE_B32 %7, %6, 4, 0, implicit killed $m0, implicit $exec DS_WRITE_B32 %7, %6, 4, 0, implicit killed $m0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/sdwa-gfx9.mir

Show All 31 Linesregisters:
- { id: 12, class: sreg_32_xm0 } - { id: 12, class: sreg_32_xm0 }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
%2 = COPY $sgpr30_sgpr31 %2 = COPY $sgpr30_sgpr31
%1 = COPY $vgpr2_vgpr3 %1 = COPY $vgpr2_vgpr3
%0 = COPY $vgpr0_vgpr1 %0 = COPY $vgpr0_vgpr1
%3 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
%12 = S_MOV_B32 123 %12 = S_MOV_B32 123
%10 = V_LSHRREV_B32_e64 16, %3, implicit $exec %10 = V_LSHRREV_B32_e64 16, %3, implicit $exec
%11 = V_ADD_I32_e32 %12, killed %10, implicit-def $vcc, implicit $exec %11 = V_ADD_I32_e32 %12, killed %10, implicit-def $vcc, implicit $exec
FLAT_STORE_DWORD %0, %11, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) FLAT_STORE_DWORD %0, %11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
$sgpr30_sgpr31 = COPY %2 $sgpr30_sgpr31 = COPY %2
S_SETPC_B64_return $sgpr30_sgpr31 S_SETPC_B64_return $sgpr30_sgpr31
... ...
# GCN-LABEL: {{^}}name: trunc_shr_f32 # GCN-LABEL: {{^}}name: trunc_shr_f32
# CI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit $exec # CI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit $exec
Show All 22 Linesregisters:
- { id: 11, class: vgpr_32 } - { id: 11, class: vgpr_32 }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
%2 = COPY $sgpr30_sgpr31 %2 = COPY $sgpr30_sgpr31
%1 = COPY $vgpr2_vgpr3 %1 = COPY $vgpr2_vgpr3
%0 = COPY $vgpr0_vgpr1 %0 = COPY $vgpr0_vgpr1
%3 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
%10 = V_LSHRREV_B32_e64 16, %3, implicit $exec %10 = V_LSHRREV_B32_e64 16, %3, implicit $exec
%11 = V_TRUNC_F32_e64 0, killed %10, 1, 2, implicit-def $vcc, implicit $exec %11 = V_TRUNC_F32_e64 0, killed %10, 1, 2, implicit-def $vcc, implicit $exec
FLAT_STORE_DWORD %0, %11, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) FLAT_STORE_DWORD %0, %11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
$sgpr30_sgpr31 = COPY %2 $sgpr30_sgpr31 = COPY %2
S_SETPC_B64_return $sgpr30_sgpr31 S_SETPC_B64_return $sgpr30_sgpr31

llvm/trunk/test/CodeGen/AMDGPU/sdwa-ops.mir

Show All 23 Lines bb.0:
%1:sgpr_64 = COPY $sgpr0_sgpr1 %1:sgpr_64 = COPY $sgpr0_sgpr1
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%22:sreg_32_xm0 = S_MOV_B32 255 %22:sreg_32_xm0 = S_MOV_B32 255
%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%30:vreg_64 = COPY $sgpr0_sgpr1 %30:vreg_64 = COPY $sgpr0_sgpr1
%63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec
%64:vgpr_32, dead %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec %64:vgpr_32, dead %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec
%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
%161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%163:vgpr_32, %165:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %161, 0, implicit $exec %163:vgpr_32, %165:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %161, 0, implicit $exec
%164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec %164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec
%162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1 %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %30, %162, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %30, %162, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
%171:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %171:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%173:vgpr_32, %175:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %171, 0, implicit $exec %173:vgpr_32, %175:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %171, 0, implicit $exec
%174:vgpr_32, dead %176:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %175, 0, implicit $exec %174:vgpr_32, dead %176:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %175, 0, implicit $exec
%172:vreg_64 = REG_SEQUENCE %173, %subreg.sub0, %174, %subreg.sub1 %172:vreg_64 = REG_SEQUENCE %173, %subreg.sub0, %174, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %30, %172, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %30, %172, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
... ...
# test for VCC interference on sdwa, should generate 1 xform only # test for VCC interference on sdwa, should generate 1 xform only
# GFX9-LABEL: name: test2_add_co_sdwa # GFX9-LABEL: name: test2_add_co_sdwa
# GFX9: V_ADD_I32_sdwa # GFX9: V_ADD_I32_sdwa
# GFX9: V_ADDC_U32_e32 # GFX9: V_ADDC_U32_e32
# GFX9-NOT: V_ADD_I32_sdwa # GFX9-NOT: V_ADD_I32_sdwa
Show All 19 Lines bb.0:
%161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%163:vgpr_32, %165:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %161, 0, implicit $exec %163:vgpr_32, %165:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %161, 0, implicit $exec
%164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec %164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec
%162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1 %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
%64:vgpr_32, dead %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec %64:vgpr_32, dead %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec
%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
%161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%163:vgpr_32, %165:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %161, 0, implicit $exec %163:vgpr_32, %165:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %161, 0, implicit $exec
%164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec %164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec
%162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1 %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %30, %162, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %30, %162, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
... ...
# test for CarryOut used, should reject # test for CarryOut used, should reject
# GFX9-LABEL: name: test3_add_co_sdwa # GFX9-LABEL: name: test3_add_co_sdwa
# GFX9: V_ADD_I32_e64 # GFX9: V_ADD_I32_e64
# GFX9: V_ADDC_U32_e64 # GFX9: V_ADDC_U32_e64
# GFX9-NOT: V_ADD_I32_sdwa # GFX9-NOT: V_ADD_I32_sdwa
Show All 13 Lines bb.0:
%1:sgpr_64 = COPY $sgpr0_sgpr1 %1:sgpr_64 = COPY $sgpr0_sgpr1
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%22:sreg_32_xm0 = S_MOV_B32 255 %22:sreg_32_xm0 = S_MOV_B32 255
%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%30:vreg_64 = COPY $sgpr0_sgpr1 %30:vreg_64 = COPY $sgpr0_sgpr1
%63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec
%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec
%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %66, %subreg.sub1 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %66, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
... ...
# test for CarryIn used more than once, should reject # test for CarryIn used more than once, should reject
# GFX9-LABEL: name: test4_add_co_sdwa # GFX9-LABEL: name: test4_add_co_sdwa
# GFX9: V_ADD_I32_e64 # GFX9: V_ADD_I32_e64
# GFX9: V_ADDC_U32_e64 # GFX9: V_ADDC_U32_e64
# GFX9-NOT: V_ADD_I32_sdwa # GFX9-NOT: V_ADD_I32_sdwa
Show All 13 Lines bb.0:
%1:sgpr_64 = COPY $sgpr0_sgpr1 %1:sgpr_64 = COPY $sgpr0_sgpr1
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%22:sreg_32_xm0 = S_MOV_B32 255 %22:sreg_32_xm0 = S_MOV_B32 255
%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%30:vreg_64 = COPY $sgpr0_sgpr1 %30:vreg_64 = COPY $sgpr0_sgpr1
%63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec
%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %65, %subreg.sub1 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %65, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
... ...
# test for simple example, should generate sdwa # test for simple example, should generate sdwa
# GFX9-LABEL: name: test5_add_co_sdwa # GFX9-LABEL: name: test5_add_co_sdwa
# GFX9: V_ADD_I32_sdwa # GFX9: V_ADD_I32_sdwa
# GFX9: V_ADDC_U32_e32 # GFX9: V_ADDC_U32_e32
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%1:sgpr_64 = COPY $sgpr0_sgpr1 %1:sgpr_64 = COPY $sgpr0_sgpr1
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%22:sreg_32_xm0 = S_MOV_B32 255 %22:sreg_32_xm0 = S_MOV_B32 255
%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%30:vreg_64 = COPY $sgpr0_sgpr1 %30:vreg_64 = COPY $sgpr0_sgpr1
%63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec
%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
... ...
# test for V_ADD_I32_e64 only, should reject # test for V_ADD_I32_e64 only, should reject
# GFX9-LABEL: name: test6_add_co_sdwa # GFX9-LABEL: name: test6_add_co_sdwa
# GFX9: V_ADD_I32_e64 # GFX9: V_ADD_I32_e64
# GFX9-NOT: V_ADD_I32_sdwa # GFX9-NOT: V_ADD_I32_sdwa
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%1:sgpr_64 = COPY $sgpr0_sgpr1 %1:sgpr_64 = COPY $sgpr0_sgpr1
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%22:sreg_32_xm0 = S_MOV_B32 255 %22:sreg_32_xm0 = S_MOV_B32 255
%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%30:vreg_64 = COPY $sgpr0_sgpr1 %30:vreg_64 = COPY $sgpr0_sgpr1
%63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec
%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %23, %subreg.sub1 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %23, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
... ...
# test for V_ADDC_U32_e64 only, should reject # test for V_ADDC_U32_e64 only, should reject
# GFX9-LABEL: name: test7_add_co_sdwa # GFX9-LABEL: name: test7_add_co_sdwa
# GFX9: V_ADDC_U32_e64 # GFX9: V_ADDC_U32_e64
# GFX9-NOT: V_ADD_I32_sdwa # GFX9-NOT: V_ADD_I32_sdwa
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%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%22:sreg_32_xm0 = S_MOV_B32 255 %22:sreg_32_xm0 = S_MOV_B32 255
%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%24:sreg_64_xexec = COPY $sgpr0_sgpr1 %24:sreg_64_xexec = COPY $sgpr0_sgpr1
%30:vreg_64 = COPY $sgpr0_sgpr1 %30:vreg_64 = COPY $sgpr0_sgpr1
%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %24, 0, implicit $exec %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %24, 0, implicit $exec
%62:vreg_64 = REG_SEQUENCE %23, %subreg.sub0, %23, %subreg.sub1 %62:vreg_64 = REG_SEQUENCE %23, %subreg.sub0, %23, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
... ...
# test for $vcc defined between two adds, should not generate # test for $vcc defined between two adds, should not generate
# GFX9-LABEL: name: test8_add_co_sdwa # GFX9-LABEL: name: test8_add_co_sdwa
# GFX9-NOT: V_ADD_I32_sdwa # GFX9-NOT: V_ADD_I32_sdwa
# GFX9: V_ADDC_U32_e64 # GFX9: V_ADDC_U32_e64
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%22:sreg_32_xm0 = S_MOV_B32 255 %22:sreg_32_xm0 = S_MOV_B32 255
%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%30:vreg_64 = COPY $sgpr0_sgpr1 %30:vreg_64 = COPY $sgpr0_sgpr1
%63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec
$vcc = COPY %30 $vcc = COPY %30
%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
%31:vreg_64 = COPY $vcc %31:vreg_64 = COPY $vcc
%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
... ...
# test for non dead $vcc, should not generate # test for non dead $vcc, should not generate
# GFX9-LABEL: name: test9_add_co_sdwa # GFX9-LABEL: name: test9_add_co_sdwa
# GFX9-NOT: V_ADD_I32_sdwa # GFX9-NOT: V_ADD_I32_sdwa
# GFX9: V_ADDC_U32_e64 # GFX9: V_ADDC_U32_e64
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%22:sreg_32_xm0 = S_MOV_B32 255 %22:sreg_32_xm0 = S_MOV_B32 255
%30:vreg_64 = COPY $sgpr0_sgpr1 %30:vreg_64 = COPY $sgpr0_sgpr1
$vcc = COPY %30 $vcc = COPY %30
%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec
%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
%31:vreg_64 = COPY $vcc %31:vreg_64 = COPY $vcc
%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
... ...
# test for def $vcc_lo, should not generate # test for def $vcc_lo, should not generate
# GFX9-LABEL: name: test10_add_co_sdwa # GFX9-LABEL: name: test10_add_co_sdwa
# GFX9-NOT: V_ADD_I32_sdwa # GFX9-NOT: V_ADD_I32_sdwa
# GFX9: V_ADDC_U32_e64 # GFX9: V_ADDC_U32_e64
--- ---
Show All 14 Lines bb.0:
%30:vreg_64 = COPY $sgpr0_sgpr1 %30:vreg_64 = COPY $sgpr0_sgpr1
$vcc_lo = COPY %30.sub0 $vcc_lo = COPY %30.sub0
%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec
%31:vgpr_32 = COPY $vcc_lo %31:vgpr_32 = COPY $vcc_lo
%32:vreg_64 = REG_SEQUENCE %31, %subreg.sub0, %23, %subreg.sub1 %32:vreg_64 = REG_SEQUENCE %31, %subreg.sub0, %23, %subreg.sub1
%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %32, %62, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %32, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
... ...
# test for read $vcc_hi, should not generate # test for read $vcc_hi, should not generate
# GFX9-LABEL: name: test11_add_co_sdwa # GFX9-LABEL: name: test11_add_co_sdwa
# GFX9-NOT: V_ADD_I32_sdwa # GFX9-NOT: V_ADD_I32_sdwa
# GFX9: V_ADDC_U32_e64 # GFX9: V_ADDC_U32_e64
--- ---
Show All 14 Lines bb.0:
%30:vreg_64 = COPY $sgpr0_sgpr1 %30:vreg_64 = COPY $sgpr0_sgpr1
$vcc_hi = COPY %30.sub0 $vcc_hi = COPY %30.sub0
%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec
%31:vgpr_32 = COPY $vcc_hi %31:vgpr_32 = COPY $vcc_hi
%32:vreg_64 = REG_SEQUENCE %31, %subreg.sub0, %23, %subreg.sub1 %32:vreg_64 = REG_SEQUENCE %31, %subreg.sub0, %23, %subreg.sub1
%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %32, %62, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %32, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
... ...
# test for $vcc defined and used between adds, should not generate # test for $vcc defined and used between adds, should not generate
# GFX9-LABEL: name: test12_add_co_sdwa # GFX9-LABEL: name: test12_add_co_sdwa
# GFX9-NOT: V_ADD_I32_sdwa # GFX9-NOT: V_ADD_I32_sdwa
# GFX9: V_ADDC_U32_e64 # GFX9: V_ADDC_U32_e64
--- ---
Show All 13 Lines bb.0:
%22:sreg_32_xm0 = S_MOV_B32 255 %22:sreg_32_xm0 = S_MOV_B32 255
%30:vreg_64 = COPY $sgpr0_sgpr1 %30:vreg_64 = COPY $sgpr0_sgpr1
%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
%63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec %63:vgpr_32, %65:sreg_64_xexec = V_ADD_I32_e64 %30.sub0, %23, 0, implicit $exec
$vcc = COPY %30 $vcc = COPY %30
%31:vreg_64 = COPY killed $vcc %31:vreg_64 = COPY killed $vcc
%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)

llvm/trunk/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir

Show First 20 Lines • Show All 83 Lines • ▼ Show 20 Linesregisters:
- { id: 100, class: vgpr_32 } - { id: 100, class: vgpr_32 }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
%2 = COPY $sgpr30_sgpr31 %2 = COPY $sgpr30_sgpr31
%1 = COPY $vgpr2_vgpr3 %1 = COPY $vgpr2_vgpr3
%0 = COPY $vgpr0_vgpr1 %0 = COPY $vgpr0_vgpr1
%3 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
%5 = S_MOV_B32 65535 %5 = S_MOV_B32 65535
%6 = S_MOV_B32 65535 %6 = S_MOV_B32 65535
%10 = V_LSHRREV_B32_e64 16, %3, implicit $exec %10 = V_LSHRREV_B32_e64 16, %3, implicit $exec
%11 = V_MOV_B32_e32 %10, implicit $exec %11 = V_MOV_B32_e32 %10, implicit $exec
%12 = V_LSHLREV_B32_e64 16, %11, implicit $exec %12 = V_LSHLREV_B32_e64 16, %11, implicit $exec
%14 = V_FRACT_F32_e32 123, implicit $exec %14 = V_FRACT_F32_e32 123, implicit $exec
Show All 33 Lines bb.0:
%45 = V_LSHLREV_B32_e64 16, %44, implicit $exec %45 = V_LSHLREV_B32_e64 16, %44, implicit $exec
%46 = V_LSHRREV_B32_e64 16, %45, implicit $exec %46 = V_LSHRREV_B32_e64 16, %45, implicit $exec
%47 = V_CVT_F32_I32_e64 %46, 0, 1, implicit $exec %47 = V_CVT_F32_I32_e64 %46, 0, 1, implicit $exec
%48 = V_LSHLREV_B32_e64 16, %47, implicit $exec %48 = V_LSHLREV_B32_e64 16, %47, implicit $exec
%100 = V_MOV_B32_e32 %48, implicit $exec %100 = V_MOV_B32_e32 %48, implicit $exec
FLAT_STORE_DWORD %0, %100, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) FLAT_STORE_DWORD %0, %100, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
$sgpr30_sgpr31 = COPY %2 $sgpr30_sgpr31 = COPY %2
S_SETPC_B64_return $sgpr30_sgpr31 S_SETPC_B64_return $sgpr30_sgpr31
... ...
--- ---
# GCN-LABEL: {{^}}name: vop2_instructions # GCN-LABEL: {{^}}name: vop2_instructions
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Linesregisters:
- { id: 100, class: vgpr_32 } - { id: 100, class: vgpr_32 }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
%2 = COPY $sgpr30_sgpr31 %2 = COPY $sgpr30_sgpr31
%1 = COPY $vgpr2_vgpr3 %1 = COPY $vgpr2_vgpr3
%0 = COPY $vgpr0_vgpr1 %0 = COPY $vgpr0_vgpr1
%3 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
%5 = S_MOV_B32 65535 %5 = S_MOV_B32 65535
%6 = S_MOV_B32 65535 %6 = S_MOV_B32 65535
%11 = V_LSHRREV_B32_e64 16, %3, implicit $exec %11 = V_LSHRREV_B32_e64 16, %3, implicit $exec
%12 = V_AND_B32_e32 %6, %11, implicit $exec %12 = V_AND_B32_e32 %6, %11, implicit $exec
%13 = V_LSHLREV_B32_e64 16, %12, implicit $exec %13 = V_LSHLREV_B32_e64 16, %12, implicit $exec
%14 = V_LSHRREV_B32_e64 16, %13, implicit $exec %14 = V_LSHRREV_B32_e64 16, %13, implicit $exec
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines bb.0:
%56 = V_LSHLREV_B32_e64 16, %55, implicit $exec %56 = V_LSHLREV_B32_e64 16, %55, implicit $exec
%57 = V_LSHRREV_B32_e64 16, %56, implicit $exec %57 = V_LSHRREV_B32_e64 16, %56, implicit $exec
%58 = V_BFE_U32 %56, 8, 8, implicit $exec %58 = V_BFE_U32 %56, 8, 8, implicit $exec
%59 = V_MAC_F16_e64 1, %57, 1, %58, 1, %58, 0, 2, implicit $exec %59 = V_MAC_F16_e64 1, %57, 1, %58, 1, %58, 0, 2, implicit $exec
%60 = V_LSHLREV_B32_e64 16, %59, implicit $exec %60 = V_LSHLREV_B32_e64 16, %59, implicit $exec
%100 = V_MOV_B32_e32 %60, implicit $exec %100 = V_MOV_B32_e32 %60, implicit $exec
FLAT_STORE_DWORD %0, %100, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) FLAT_STORE_DWORD %0, %100, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
$sgpr30_sgpr31 = COPY %2 $sgpr30_sgpr31 = COPY %2
S_SETPC_B64_return $sgpr30_sgpr31 S_SETPC_B64_return $sgpr30_sgpr31
... ...
--- ---
# GCN-LABEL: {{^}}name: vopc_instructions # GCN-LABEL: {{^}}name: vopc_instructions
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Linesregisters:
- { id: 100, class: vgpr_32 } - { id: 100, class: vgpr_32 }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
%2 = COPY $sgpr30_sgpr31 %2 = COPY $sgpr30_sgpr31
%1 = COPY $vgpr2_vgpr3 %1 = COPY $vgpr2_vgpr3
%0 = COPY $vgpr0_vgpr1 %0 = COPY $vgpr0_vgpr1
%3 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
%5 = S_MOV_B32 65535 %5 = S_MOV_B32 65535
%6 = S_MOV_B32 65535 %6 = S_MOV_B32 65535
%10 = V_AND_B32_e64 %5, %3, implicit $exec %10 = V_AND_B32_e64 %5, %3, implicit $exec
V_CMP_EQ_F32_e32 123, killed %10, implicit-def $vcc, implicit $exec V_CMP_EQ_F32_e32 123, killed %10, implicit-def $vcc, implicit $exec
%11 = V_AND_B32_e64 %5, %3, implicit $exec %11 = V_AND_B32_e64 %5, %3, implicit $exec
V_CMPX_GT_F32_e32 123, killed %11, implicit-def $vcc, implicit-def $exec, implicit $exec V_CMPX_GT_F32_e32 123, killed %11, implicit-def $vcc, implicit-def $exec, implicit $exec
Show All 24 Lines bb.0:
%26 = V_AND_B32_e64 %5, %3, implicit $exec %26 = V_AND_B32_e64 %5, %3, implicit $exec
$vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %26, 0, implicit-def $exec, implicit $exec $vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %26, 0, implicit-def $exec, implicit $exec
%27 = V_AND_B32_e64 %5, %3, implicit $exec %27 = V_AND_B32_e64 %5, %3, implicit $exec
$vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %27, 1, implicit-def $exec, implicit $exec $vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %27, 1, implicit-def $exec, implicit $exec
%100 = V_MOV_B32_e32 $vcc_lo, implicit $exec %100 = V_MOV_B32_e32 $vcc_lo, implicit $exec
FLAT_STORE_DWORD %0, %100, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) FLAT_STORE_DWORD %0, %100, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
$sgpr30_sgpr31 = COPY %2 $sgpr30_sgpr31 = COPY %2
S_SETPC_B64_return $sgpr30_sgpr31 S_SETPC_B64_return $sgpr30_sgpr31

llvm/trunk/test/CodeGen/AMDGPU/sdwa-preserve.mir

Show All 30 Linesregisters:
- { id: 13, class: vgpr_32 } - { id: 13, class: vgpr_32 }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
%2 = COPY $sgpr30_sgpr31 %2 = COPY $sgpr30_sgpr31
%1 = COPY $vgpr2_vgpr3 %1 = COPY $vgpr2_vgpr3
%0 = COPY $vgpr0_vgpr1 %0 = COPY $vgpr0_vgpr1
%3 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %3 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
%4 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %4 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
%5 = V_AND_B32_e32 65535, %3, implicit $exec %5 = V_AND_B32_e32 65535, %3, implicit $exec
%6 = V_LSHRREV_B32_e64 16, %4, implicit $exec %6 = V_LSHRREV_B32_e64 16, %4, implicit $exec
%7 = V_BFE_U32 %3, 8, 8, implicit $exec %7 = V_BFE_U32 %3, 8, 8, implicit $exec
%8 = V_LSHRREV_B32_e32 24, %4, implicit $exec %8 = V_LSHRREV_B32_e32 24, %4, implicit $exec
%9 = V_ADD_F16_e64 0, %5, 0, %6, 0, 0, implicit $exec %9 = V_ADD_F16_e64 0, %5, 0, %6, 0, 0, implicit $exec
%10 = V_LSHLREV_B16_e64 8, %9, implicit $exec %10 = V_LSHLREV_B16_e64 8, %9, implicit $exec
%11 = V_MUL_F32_e64 0, %7, 0, %8, 0, 0, implicit $exec %11 = V_MUL_F32_e64 0, %7, 0, %8, 0, 0, implicit $exec
%12 = V_LSHLREV_B32_e64 16, %11, implicit $exec %12 = V_LSHLREV_B32_e64 16, %11, implicit $exec
%13 = V_OR_B32_e64 %10, %12, implicit $exec %13 = V_OR_B32_e64 %10, %12, implicit $exec
FLAT_STORE_DWORD %0, %13, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) FLAT_STORE_DWORD %0, %13, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
$sgpr30_sgpr31 = COPY %2 $sgpr30_sgpr31 = COPY %2
S_SETPC_B64_return $sgpr30_sgpr31 S_SETPC_B64_return $sgpr30_sgpr31
--- ---
# SDWA-LABEL: sdwa_preserve_keep # SDWA-LABEL: sdwa_preserve_keep
# SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] # SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
# SDWA: flat_load_dword [[SECOND:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] # SDWA: flat_load_dword [[SECOND:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
Show All 20 Linesregisters:
- { id: 17, class: vgpr_32 } - { id: 17, class: vgpr_32 }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
%2 = COPY $sgpr30_sgpr31 %2 = COPY $sgpr30_sgpr31
%1 = COPY $vgpr2_vgpr3 %1 = COPY $vgpr2_vgpr3
%0 = COPY $vgpr0_vgpr1 %0 = COPY $vgpr0_vgpr1
%3 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %3 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
%4 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %4 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
%9:vgpr_32 = V_LSHRREV_B16_e64 8, %3, implicit $exec %9:vgpr_32 = V_LSHRREV_B16_e64 8, %3, implicit $exec
%10:sreg_32_xm0 = S_MOV_B32 255 %10:sreg_32_xm0 = S_MOV_B32 255
%11:vgpr_32 = V_AND_B32_e64 %3, killed %10, implicit $exec %11:vgpr_32 = V_AND_B32_e64 %3, killed %10, implicit $exec
%17:vgpr_32 = V_MOV_B32_sdwa 0, %4, 0, 5, 2, 4, implicit $exec, implicit %11(tied-def 0) %17:vgpr_32 = V_MOV_B32_sdwa 0, %4, 0, 5, 2, 4, implicit $exec, implicit %11(tied-def 0)
FLAT_STORE_DWORD %0, %17, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) FLAT_STORE_DWORD %0, %17, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# SDWA-LABEL: sdwa_preserve_remove # SDWA-LABEL: sdwa_preserve_remove
# SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] # SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
# SDWA: flat_load_dword [[SECOND:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] # SDWA: flat_load_dword [[SECOND:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
Show All 19 Linesregisters:
- { id: 17, class: vgpr_32 } - { id: 17, class: vgpr_32 }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
%2 = COPY $sgpr30_sgpr31 %2 = COPY $sgpr30_sgpr31
%1 = COPY $vgpr2_vgpr3 %1 = COPY $vgpr2_vgpr3
%0 = COPY $vgpr0_vgpr1 %0 = COPY $vgpr0_vgpr1
%3 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %3 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
%4 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %4 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
%9:vgpr_32 = V_LSHRREV_B16_e64 8, %3, implicit $exec %9:vgpr_32 = V_LSHRREV_B16_e64 8, %3, implicit $exec
%10:sreg_32_xm0 = S_MOV_B32 65535 %10:sreg_32_xm0 = S_MOV_B32 65535
%11:vgpr_32 = V_AND_B32_e64 %3, killed %10, implicit $exec %11:vgpr_32 = V_AND_B32_e64 %3, killed %10, implicit $exec
%17:vgpr_32 = V_MOV_B32_sdwa 0, %4, 0, 5, 2, 4, implicit $exec, implicit %11(tied-def 0) %17:vgpr_32 = V_MOV_B32_sdwa 0, %4, 0, 5, 2, 4, implicit $exec, implicit %11(tied-def 0)
FLAT_STORE_DWORD %0, %17, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) FLAT_STORE_DWORD %0, %17, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir

Show First 20 Lines • Show All 197 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0.bb: bb.0.bb:
successors: %bb.2.bb2(0x80000000) successors: %bb.2.bb2(0x80000000)
liveins: $sgpr4_sgpr5 liveins: $sgpr4_sgpr5
%4 = COPY $sgpr4_sgpr5 %4 = COPY $sgpr4_sgpr5
%9 = S_LOAD_DWORDX2_IMM %4, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %9 = S_LOAD_DWORDX2_IMM %4, 0, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%8 = S_MOV_B64 0 %8 = S_MOV_B64 0
%7 = COPY %9 %7 = COPY %9
%30 = V_MOV_B32_e32 1, implicit $exec %30 = V_MOV_B32_e32 1, implicit $exec
S_BRANCH %bb.2.bb2 S_BRANCH %bb.2.bb2
bb.1.bb1: bb.1.bb1:
S_ENDPGM 0 S_ENDPGM 0
bb.2.bb2: bb.2.bb2:
successors: %bb.1.bb1(0x04000000), %bb.2.bb2(0x7c000000) successors: %bb.1.bb1(0x04000000), %bb.2.bb2(0x7c000000)
%0 = PHI %8, %bb.0.bb, %1, %bb.2.bb2 %0 = PHI %8, %bb.0.bb, %1, %bb.2.bb2
%13 = COPY %7.sub1 %13 = COPY %7.sub1
%14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def $scc %14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def $scc
%15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead $scc, implicit $scc %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead $scc, implicit $scc
%16 = REG_SEQUENCE %14, 1, %15, 2 %16 = REG_SEQUENCE %14, 1, %15, 2
%18 = COPY %16 %18 = COPY %16
%17 = FLAT_LOAD_DWORD %18, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.uglygep45) %17 = FLAT_LOAD_DWORD %18, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.uglygep45)
%60 = V_BFE_U32 %17, 8, 8, implicit $exec %60 = V_BFE_U32 %17, 8, 8, implicit $exec
%61 = V_LSHLREV_B32_e32 2, killed %60, implicit $exec %61 = V_LSHLREV_B32_e32 2, killed %60, implicit $exec
%70 = V_ADD_I32_e32 %7.sub0, %61, implicit-def $vcc, implicit $exec %70 = V_ADD_I32_e32 %7.sub0, %61, implicit-def $vcc, implicit $exec
%66 = COPY %13 %66 = COPY %13
%65 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec %65 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec
%67 = REG_SEQUENCE %70, 1, killed %65, 2 %67 = REG_SEQUENCE %70, 1, killed %65, 2
FLAT_STORE_DWORD %67, %30, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.tmp9) FLAT_STORE_DWORD %67, %30, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.tmp9)
%37 = S_ADD_U32 %14, 4, implicit-def $scc %37 = S_ADD_U32 %14, 4, implicit-def $scc
%38 = S_ADDC_U32 %15, 0, implicit-def dead $scc, implicit $scc %38 = S_ADDC_U32 %15, 0, implicit-def dead $scc, implicit $scc
%71 = COPY killed %37 %71 = COPY killed %37
%72 = COPY killed %38 %72 = COPY killed %38
%41 = REG_SEQUENCE killed %71, 1, killed %72, 2 %41 = REG_SEQUENCE killed %71, 1, killed %72, 2
%40 = FLAT_LOAD_DWORD killed %41, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.scevgep) %40 = FLAT_LOAD_DWORD killed %41, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.scevgep)
%73 = V_BFE_U32 %40, 8, 8, implicit $exec %73 = V_BFE_U32 %40, 8, 8, implicit $exec
%74 = V_LSHLREV_B32_e32 2, killed %73, implicit $exec %74 = V_LSHLREV_B32_e32 2, killed %73, implicit $exec
%83 = V_ADD_I32_e32 %7.sub0, %74, implicit-def $vcc, implicit $exec %83 = V_ADD_I32_e32 %7.sub0, %74, implicit-def $vcc, implicit $exec
%78 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec %78 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec
%80 = REG_SEQUENCE %83, 1, killed %78, 2 %80 = REG_SEQUENCE %83, 1, killed %78, 2
FLAT_STORE_DWORD %80, %30, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.tmp17) FLAT_STORE_DWORD %80, %30, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.tmp17)
%55 = S_ADD_U32 %0.sub0, 8, implicit-def $scc %55 = S_ADD_U32 %0.sub0, 8, implicit-def $scc
%56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead $scc, implicit $scc %56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead $scc, implicit $scc
%57 = REG_SEQUENCE %55, 1, killed %56, 2 %57 = REG_SEQUENCE %55, 1, killed %56, 2
%1 = COPY %57 %1 = COPY %57
S_CMPK_EQ_I32 %55, 4096, implicit-def $scc S_CMPK_EQ_I32 %55, 4096, implicit-def $scc
S_CBRANCH_SCC1 %bb.1.bb1, implicit $scc S_CBRANCH_SCC1 %bb.1.bb1, implicit $scc
S_BRANCH %bb.2.bb2 S_BRANCH %bb.2.bb2
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0.bb: bb.0.bb:
successors: %bb.2.bb2(0x80000000) successors: %bb.2.bb2(0x80000000)
liveins: $sgpr4_sgpr5 liveins: $sgpr4_sgpr5
%4 = COPY $sgpr4_sgpr5 %4 = COPY $sgpr4_sgpr5
%9 = S_LOAD_DWORDX2_IMM %4, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) %9 = S_LOAD_DWORDX2_IMM %4, 0, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%8 = S_MOV_B64 0 %8 = S_MOV_B64 0
%7 = COPY %9 %7 = COPY %9
%30 = V_MOV_B32_e32 1, implicit $exec %30 = V_MOV_B32_e32 1, implicit $exec
%84 = S_MOV_B32 2 %84 = S_MOV_B32 2
S_BRANCH %bb.2.bb2 S_BRANCH %bb.2.bb2
bb.1.bb1: bb.1.bb1:
S_ENDPGM 0 S_ENDPGM 0
bb.2.bb2: bb.2.bb2:
successors: %bb.1.bb1(0x04000000), %bb.2.bb2(0x7c000000) successors: %bb.1.bb1(0x04000000), %bb.2.bb2(0x7c000000)
%0 = PHI %8, %bb.0.bb, %1, %bb.2.bb2 %0 = PHI %8, %bb.0.bb, %1, %bb.2.bb2
%13 = COPY %7.sub1 %13 = COPY %7.sub1
%14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def $scc %14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def $scc
%15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead $scc, implicit $scc %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead $scc, implicit $scc
%16 = REG_SEQUENCE %14, 1, %15, 2 %16 = REG_SEQUENCE %14, 1, %15, 2
%18 = COPY %16 %18 = COPY %16
%17 = FLAT_LOAD_DWORD %18, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.uglygep45) %17 = FLAT_LOAD_DWORD %18, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.uglygep45)
%60 = V_BFE_U32 %17, 8, 8, implicit $exec %60 = V_BFE_U32 %17, 8, 8, implicit $exec
%61 = V_LSHLREV_B32_e32 %84, killed %60, implicit $exec %61 = V_LSHLREV_B32_e32 %84, killed %60, implicit $exec
%70 = V_ADD_I32_e32 %7.sub0, %61, implicit-def $vcc, implicit $exec %70 = V_ADD_I32_e32 %7.sub0, %61, implicit-def $vcc, implicit $exec
%66 = COPY %13 %66 = COPY %13
%65 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec %65 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec
%67 = REG_SEQUENCE %70, 1, killed %65, 2 %67 = REG_SEQUENCE %70, 1, killed %65, 2
FLAT_STORE_DWORD %67, %30, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.tmp9) FLAT_STORE_DWORD %67, %30, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.tmp9)
%37 = S_ADD_U32 %14, 4, implicit-def $scc %37 = S_ADD_U32 %14, 4, implicit-def $scc
%38 = S_ADDC_U32 %15, 0, implicit-def dead $scc, implicit $scc %38 = S_ADDC_U32 %15, 0, implicit-def dead $scc, implicit $scc
%71 = COPY killed %37 %71 = COPY killed %37
%72 = COPY killed %38 %72 = COPY killed %38
%41 = REG_SEQUENCE killed %71, 1, killed %72, 2 %41 = REG_SEQUENCE killed %71, 1, killed %72, 2
%40 = FLAT_LOAD_DWORD killed %41, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.scevgep) %40 = FLAT_LOAD_DWORD killed %41, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.scevgep)
%73 = V_BFE_U32 %40, 8, 8, implicit $exec %73 = V_BFE_U32 %40, 8, 8, implicit $exec
%74 = V_LSHLREV_B32_e32 %84, killed %73, implicit $exec %74 = V_LSHLREV_B32_e32 %84, killed %73, implicit $exec
%83 = V_ADD_I32_e32 %7.sub0, %74, implicit-def $vcc, implicit $exec %83 = V_ADD_I32_e32 %7.sub0, %74, implicit-def $vcc, implicit $exec
%78 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec %78 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec
%80 = REG_SEQUENCE %83, 1, killed %78, 2 %80 = REG_SEQUENCE %83, 1, killed %78, 2
FLAT_STORE_DWORD %80, %30, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.tmp17) FLAT_STORE_DWORD %80, %30, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.tmp17)
%55 = S_ADD_U32 %0.sub0, 8, implicit-def $scc %55 = S_ADD_U32 %0.sub0, 8, implicit-def $scc
%56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead $scc, implicit $scc %56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead $scc, implicit $scc
%57 = REG_SEQUENCE %55, 1, killed %56, 2 %57 = REG_SEQUENCE %55, 1, killed %56, 2
%1 = COPY %57 %1 = COPY %57
S_CMPK_EQ_I32 %55, 4096, implicit-def $scc S_CMPK_EQ_I32 %55, 4096, implicit-def $scc
S_CBRANCH_SCC1 %bb.1.bb1, implicit $scc S_CBRANCH_SCC1 %bb.1.bb1, implicit $scc
S_BRANCH %bb.2.bb2 S_BRANCH %bb.2.bb2
... ...

llvm/trunk/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir

Show All 35 Linesregisters:
- { id: 20, class: vgpr_32 } - { id: 20, class: vgpr_32 }
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
%2 = COPY $sgpr30_sgpr31 %2 = COPY $sgpr30_sgpr31
%1 = COPY $vgpr2_vgpr3 %1 = COPY $vgpr2_vgpr3
%0 = COPY $vgpr0_vgpr1 %0 = COPY $vgpr0_vgpr1
%3 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) %3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
%12 = V_LSHRREV_B32_e64 16, %3, implicit $exec %12 = V_LSHRREV_B32_e64 16, %3, implicit $exec
%13 = V_BCNT_U32_B32_e64 %3, killed %12, implicit-def $vcc, implicit $exec %13 = V_BCNT_U32_B32_e64 %3, killed %12, implicit-def $vcc, implicit $exec
%14 = V_LSHRREV_B32_e64 16, %13, implicit $exec %14 = V_LSHRREV_B32_e64 16, %13, implicit $exec
%15 = V_BFM_B32_e64 %13, killed %14, implicit-def $vcc, implicit $exec %15 = V_BFM_B32_e64 %13, killed %14, implicit-def $vcc, implicit $exec
%16 = V_LSHRREV_B32_e64 16, %15, implicit $exec %16 = V_LSHRREV_B32_e64 16, %15, implicit $exec
%17 = V_CVT_PKNORM_I16_F32_e64 0, %15, 0, killed %16, 0, implicit-def $vcc, implicit $exec %17 = V_CVT_PKNORM_I16_F32_e64 0, %15, 0, killed %16, 0, implicit-def $vcc, implicit $exec
%18 = V_LSHRREV_B32_e64 16, %17, implicit $exec %18 = V_LSHRREV_B32_e64 16, %17, implicit $exec
%19 = V_READLANE_B32 killed %18, 0, implicit-def $vcc, implicit $exec %19 = V_READLANE_B32 killed %18, 0, implicit-def $vcc, implicit $exec
%20 = V_MOV_B32_e64 %19, implicit $exec %20 = V_MOV_B32_e64 %19, implicit $exec
FLAT_STORE_DWORD %0, %20, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) FLAT_STORE_DWORD %0, %20, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
$sgpr30_sgpr31 = COPY %2 $sgpr30_sgpr31 = COPY %2
S_SETPC_B64_return $sgpr30_sgpr31 S_SETPC_B64_return $sgpr30_sgpr31

llvm/trunk/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 LinesmachineFunctionInfo:
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3 scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
scratchWaveOffsetReg: $sgpr4 scratchWaveOffsetReg: $sgpr4
frameOffsetReg: $sgpr5 frameOffsetReg: $sgpr5
stackPtrOffsetReg: $sgpr32 stackPtrOffsetReg: $sgpr32
body: | body: |
bb.0: bb.0:
%0:sreg_32_xm0 = COPY $sgpr5 %0:sreg_32_xm0 = COPY $sgpr5
%1:vreg_64 = IMPLICIT_DEF %1:vreg_64 = IMPLICIT_DEF
%2:vgpr_32 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit $exec, implicit $flat_scr %2:vgpr_32 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%3:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @func + 4, target-flags(amdgpu-rel32-hi) @func + 4, implicit-def dead $scc %3:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @func + 4, target-flags(amdgpu-rel32-hi) @func + 4, implicit-def dead $scc
ADJCALLSTACKUP 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5 ADJCALLSTACKUP 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5
dead $sgpr30_sgpr31 = SI_CALL %3, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit undef $vgpr0 dead $sgpr30_sgpr31 = SI_CALL %3, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit undef $vgpr0
$sgpr5 = COPY %0 $sgpr5 = COPY %0
%4:sreg_32_xm0 = COPY $sgpr5 %4:sreg_32_xm0 = COPY $sgpr5
ADJCALLSTACKDOWN 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5 ADJCALLSTACKDOWN 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5
ADJCALLSTACKUP 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5 ADJCALLSTACKUP 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5
$vgpr0 = COPY %2 $vgpr0 = COPY %2
dead $sgpr30_sgpr31 = SI_CALL %3, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit killed $vgpr0 dead $sgpr30_sgpr31 = SI_CALL %3, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit killed $vgpr0
$sgpr5 = COPY %4 $sgpr5 = COPY %4
ADJCALLSTACKDOWN 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5 ADJCALLSTACKDOWN 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5
... ...

llvm/trunk/test/CodeGen/AMDGPU/shrink-carry.mir

Show All 15 Lines
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1 = IMPLICIT_DEF %1 = IMPLICIT_DEF
%2 = IMPLICIT_DEF %2 = IMPLICIT_DEF
%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec %3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
%4, %5 = V_SUBBREV_U32_e64 0, %0, %3, 0, implicit $exec %4, %5 = V_SUBBREV_U32_e64 0, %0, %3, 0, implicit $exec
GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: name: subb{{$}} # GCN-LABEL: name: subb{{$}}
# GCN: V_SUBBREV_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec # GCN: V_SUBBREV_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec
--- ---
name: subb name: subb
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vgpr_32 } - { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 } - { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 } - { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64_xexec } - { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 } - { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64_xexec } - { id: 5, class: sreg_64_xexec }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1 = IMPLICIT_DEF %1 = IMPLICIT_DEF
%2 = IMPLICIT_DEF %2 = IMPLICIT_DEF
%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec %3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
%4, %5 = V_SUBB_U32_e64 %0, 0, %3, 0, implicit $exec %4, %5 = V_SUBB_U32_e64 %0, 0, %3, 0, implicit $exec
GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: name: addc{{$}} # GCN-LABEL: name: addc{{$}}
# GCN: V_ADDC_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec # GCN: V_ADDC_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec
--- ---
name: addc name: addc
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vgpr_32 } - { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 } - { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 } - { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64_xexec } - { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 } - { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64_xexec } - { id: 5, class: sreg_64_xexec }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1 = IMPLICIT_DEF %1 = IMPLICIT_DEF
%2 = IMPLICIT_DEF %2 = IMPLICIT_DEF
%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec %3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
%4, %5 = V_ADDC_U32_e64 0, %0, %3, 0, implicit $exec %4, %5 = V_ADDC_U32_e64 0, %0, %3, 0, implicit $exec
GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: name: addc2{{$}} # GCN-LABEL: name: addc2{{$}}
# GCN: V_ADDC_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec # GCN: V_ADDC_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec
--- ---
name: addc2 name: addc2
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vgpr_32 } - { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 } - { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 } - { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64_xexec } - { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 } - { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64_xexec } - { id: 5, class: sreg_64_xexec }
body: | body: |
bb.0: bb.0:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
%1 = IMPLICIT_DEF %1 = IMPLICIT_DEF
%2 = IMPLICIT_DEF %2 = IMPLICIT_DEF
%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec %3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
%4, %5 = V_ADDC_U32_e64 %0, 0, %3, 0, implicit $exec %4, %5 = V_ADDC_U32_e64 %0, 0, %3, 0, implicit $exec
GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, 0, 0, implicit $exec
... ...

llvm/trunk/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
%26 = V_ASHRREV_I32_e32 31, %3, implicit $exec %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%27 = REG_SEQUENCE %3, 1, %26, 2 %27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440 %10 = S_MOV_B32 61440
%11 = S_MOV_B32 0 %11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18 %13 = REG_SEQUENCE killed %5, 17, %12, 18
%28 = V_LSHL_B64 killed %27, 2, implicit $exec %28 = V_LSHL_B64 killed %27, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18 %16 = REG_SEQUENCE killed %4, 17, %12, 18
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, implicit $exec
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, implicit $exec
%29, %9 = V_ADD_I32_e64 %19, %17, 0, implicit $exec %29, %9 = V_ADD_I32_e64 %19, %17, 0, implicit $exec
%24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: shrink_sub_vop3{{$}} # GCN-LABEL: name: shrink_sub_vop3{{$}}
# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUB_I32_e64 %19, %17, 0, implicit $exec # GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUB_I32_e64 %19, %17, 0, implicit $exec
# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
%26 = V_ASHRREV_I32_e32 31, %3, implicit $exec %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%27 = REG_SEQUENCE %3, 1, %26, 2 %27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440 %10 = S_MOV_B32 61440
%11 = S_MOV_B32 0 %11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18 %13 = REG_SEQUENCE killed %5, 17, %12, 18
%28 = V_LSHL_B64 killed %27, 2, implicit $exec %28 = V_LSHL_B64 killed %27, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18 %16 = REG_SEQUENCE killed %4, 17, %12, 18
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, implicit $exec
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, implicit $exec
%29, %9 = V_SUB_I32_e64 %19, %17, 0, implicit $exec %29, %9 = V_SUB_I32_e64 %19, %17, 0, implicit $exec
%24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: shrink_subrev_vop3{{$}} # GCN-LABEL: name: shrink_subrev_vop3{{$}}
# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUBREV_I32_e64 %19, %17, 0, implicit $exec # GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUBREV_I32_e64 %19, %17, 0, implicit $exec
# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
%26 = V_ASHRREV_I32_e32 31, %3, implicit $exec %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%27 = REG_SEQUENCE %3, 1, %26, 2 %27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440 %10 = S_MOV_B32 61440
%11 = S_MOV_B32 0 %11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18 %13 = REG_SEQUENCE killed %5, 17, %12, 18
%28 = V_LSHL_B64 killed %27, 2, implicit $exec %28 = V_LSHL_B64 killed %27, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18 %16 = REG_SEQUENCE killed %4, 17, %12, 18
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, implicit $exec
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, implicit $exec
%29, %9 = V_SUBREV_I32_e64 %19, %17, 0, implicit $exec %29, %9 = V_SUBREV_I32_e64 %19, %17, 0, implicit $exec
%24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
BUFFER_STORE_DWORD_ADDR64 %29, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 %29, %28, killed %16, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: check_addc_src2_vop3{{$}} # GCN-LABEL: name: check_addc_src2_vop3{{$}}
# GCN: %29:vgpr_32, $vcc = V_ADDC_U32_e64 %19, %17, %9, 0, implicit $exec # GCN: %29:vgpr_32, $vcc = V_ADDC_U32_e64 %19, %17, %9, 0, implicit $exec
# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
name: check_addc_src2_vop3 name: check_addc_src2_vop3
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
%26 = V_ASHRREV_I32_e32 31, %3, implicit $exec %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%27 = REG_SEQUENCE %3, 1, %26, 2 %27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440 %10 = S_MOV_B32 61440
%11 = S_MOV_B32 0 %11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18 %13 = REG_SEQUENCE killed %5, 17, %12, 18
%28 = V_LSHL_B64 killed %27, 2, implicit $exec %28 = V_LSHL_B64 killed %27, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18 %16 = REG_SEQUENCE killed %4, 17, %12, 18
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, implicit $exec
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, implicit $exec
%9 = S_MOV_B64 0 %9 = S_MOV_B64 0
%29, $vcc = V_ADDC_U32_e64 %19, %17, %9, 0, implicit $exec %29, $vcc = V_ADDC_U32_e64 %19, %17, %9, 0, implicit $exec
%24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: shrink_addc_vop3{{$}} # GCN-LABEL: name: shrink_addc_vop3{{$}}
# GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit $vcc, implicit $exec # GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit $vcc, implicit $exec
# GCN %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec # GCN %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
%26 = V_ASHRREV_I32_e32 31, %3, implicit $exec %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%27 = REG_SEQUENCE %3, 1, %26, 2 %27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440 %10 = S_MOV_B32 61440
%11 = S_MOV_B32 0 %11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18 %13 = REG_SEQUENCE killed %5, 17, %12, 18
%28 = V_LSHL_B64 killed %27, 2, implicit $exec %28 = V_LSHL_B64 killed %27, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18 %16 = REG_SEQUENCE killed %4, 17, %12, 18
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, implicit $exec
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, implicit $exec
$vcc = S_MOV_B64 0 $vcc = S_MOV_B64 0
%29, $vcc = V_ADDC_U32_e64 %19, %17, $vcc, 0, implicit $exec %29, $vcc = V_ADDC_U32_e64 %19, %17, $vcc, 0, implicit $exec
%24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# GCN-LABEL: name: shrink_addc_undef_vcc{{$}} # GCN-LABEL: name: shrink_addc_undef_vcc{{$}}
# GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit undef $vcc, implicit $exec # GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit undef $vcc, implicit $exec
# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
%3 = COPY $vgpr0 %3 = COPY $vgpr0
%0 = COPY $sgpr0_sgpr1 %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
%26 = V_ASHRREV_I32_e32 31, %3, implicit $exec %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%27 = REG_SEQUENCE %3, 1, %26, 2 %27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440 %10 = S_MOV_B32 61440
%11 = S_MOV_B32 0 %11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18 %13 = REG_SEQUENCE killed %5, 17, %12, 18
%28 = V_LSHL_B64 killed %27, 2, implicit $exec %28 = V_LSHL_B64 killed %27, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18 %16 = REG_SEQUENCE killed %4, 17, %12, 18
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, implicit $exec
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, implicit $exec
%29, $vcc = V_ADDC_U32_e64 %19, %17, undef $vcc, 0, implicit $exec %29, $vcc = V_ADDC_U32_e64 %19, %17, undef $vcc, 0, implicit $exec
%24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/si-lower-control-flow.mir

Show All 9 Linesbody: |
bb.0: bb.0:
; GCN-LABEL: name: si-lower-control-flow ; GCN-LABEL: name: si-lower-control-flow
; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5 ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 16, 0 ; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 16, 0
; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[S_LOAD_DWORD_IMM]], 255, implicit-def $scc ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[S_LOAD_DWORD_IMM]], 255, implicit-def $scc
; GCN: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 65535, [[S_AND_B32_]], implicit-def $scc ; GCN: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 65535, [[S_AND_B32_]], implicit-def $scc
; GCN: S_ENDPGM 0 ; GCN: S_ENDPGM 0
%0:sgpr_64 = COPY $sgpr4_sgpr5 %0:sgpr_64 = COPY $sgpr4_sgpr5
%1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0 %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0, 0
%2:sreg_32_xm0 = S_AND_B32 %1, 255, implicit-def $scc %2:sreg_32_xm0 = S_AND_B32 %1, 255, implicit-def $scc
%3:sreg_32_xm0 = S_AND_B32 65535, %2, implicit-def $scc %3:sreg_32_xm0 = S_AND_B32 65535, %2, implicit-def $scc
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: preserve_undef_flag_si_if_src name: preserve_undef_flag_si_if_src
tracksRegLiveness: true tracksRegLiveness: true
Show All 27 Lines

llvm/trunk/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir

Show All 30 Lines bb.0:
%4:vgpr_32 = COPY $vgpr0 %4:vgpr_32 = COPY $vgpr0
%5:sgpr_32 = COPY $sgpr14 %5:sgpr_32 = COPY $sgpr14
%6:sgpr_32 = COPY $sgpr13 %6:sgpr_32 = COPY $sgpr13
%7:sreg_64_xexec = S_GETPC_B64 %7:sreg_64_xexec = S_GETPC_B64
%7.sub0:sreg_64_xexec = COPY %1 %7.sub0:sreg_64_xexec = COPY %1
%3.sub1:sgpr_128 = S_AND_B32 %2, 65535, implicit-def dead $scc %3.sub1:sgpr_128 = S_AND_B32 %2, 65535, implicit-def dead $scc
%3.sub3:sgpr_128 = S_MOV_B32 151468 %3.sub3:sgpr_128 = S_MOV_B32 151468
%3.sub2:sgpr_128 = S_MOV_B32 -1 %3.sub2:sgpr_128 = S_MOV_B32 -1
%7.sub0:sreg_64_xexec = S_LOAD_DWORD_IMM %7, 48, 0 :: (load 4 from `i8 addrspace(4)* undef`, addrspace 4) %7.sub0:sreg_64_xexec = S_LOAD_DWORD_IMM %7, 48, 0, 0 :: (load 4 from `i8 addrspace(4)* undef`, addrspace 4)
%8:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_IMM %3, 640, 0 :: (dereferenceable invariant load 8) %8:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_IMM %3, 640, 0, 0 :: (dereferenceable invariant load 8)
undef %9.sub0:vreg_128 = V_LSHL_ADD_U32 %6, 4, %4, implicit $exec undef %9.sub0:vreg_128 = V_LSHL_ADD_U32 %6, 4, %4, implicit $exec
%9.sub1:vreg_128 = V_LSHL_ADD_U32 %5, 4, %0, implicit $exec %9.sub1:vreg_128 = V_LSHL_ADD_U32 %5, 4, %0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/smrd-fold-offset.mir

Show All 13 Lines bb.0:
%2:sgpr_32 = COPY $sgpr2 %2:sgpr_32 = COPY $sgpr2
%1:sgpr_32 = COPY $sgpr1 %1:sgpr_32 = COPY $sgpr1
%0:sgpr_32 = COPY $sgpr0 %0:sgpr_32 = COPY $sgpr0
%5:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3 %5:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
%6:sreg_32_xm0 = S_MOV_B32 4095 %6:sreg_32_xm0 = S_MOV_B32 4095
%8:vgpr_32 = COPY %6 %8:vgpr_32 = COPY %6
%7:vgpr_32 = V_ADD_I32_e32 %4, killed %8, implicit-def dead $vcc, implicit $exec %7:vgpr_32 = V_ADD_I32_e32 %4, killed %8, implicit-def dead $vcc, implicit $exec
%10:sreg_32 = COPY %7 %10:sreg_32 = COPY %7
%9:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR killed %5, killed %10, 0 %9:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR killed %5, killed %10, 0, 0
$vgpr0 = COPY %9 $vgpr0 = COPY %9
SI_RETURN_TO_EPILOG $vgpr0 SI_RETURN_TO_EPILOG $vgpr0
... ...
# GCN-LABEL: name: smrd_vgpr_offset_imm_add_u32 # GCN-LABEL: name: smrd_vgpr_offset_imm_add_u32
# GCN: V_READFIRSTLANE_B32 # GCN: V_READFIRSTLANE_B32
# GCN: S_BUFFER_LOAD_DWORD_SGPR # GCN: S_BUFFER_LOAD_DWORD_SGPR
--- ---
name: smrd_vgpr_offset_imm_add_u32 name: smrd_vgpr_offset_imm_add_u32
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0
%4:vgpr_32 = COPY $vgpr0 %4:vgpr_32 = COPY $vgpr0
%3:sgpr_32 = COPY $sgpr3 %3:sgpr_32 = COPY $sgpr3
%2:sgpr_32 = COPY $sgpr2 %2:sgpr_32 = COPY $sgpr2
%1:sgpr_32 = COPY $sgpr1 %1:sgpr_32 = COPY $sgpr1
%0:sgpr_32 = COPY $sgpr0 %0:sgpr_32 = COPY $sgpr0
%5:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3 %5:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
%6:sreg_32_xm0 = S_MOV_B32 4095 %6:sreg_32_xm0 = S_MOV_B32 4095
%8:vgpr_32 = COPY %6 %8:vgpr_32 = COPY %6
%7:vgpr_32 = V_ADD_U32_e32 %4, killed %8, implicit $exec %7:vgpr_32 = V_ADD_U32_e32 %4, killed %8, implicit $exec
%10:sreg_32 = COPY %7 %10:sreg_32 = COPY %7
%9:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR killed %5, killed %10, 0 :: (dereferenceable invariant load 4) %9:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR killed %5, killed %10, 0, 0 :: (dereferenceable invariant load 4)
$vgpr0 = COPY %9 $vgpr0 = COPY %9
SI_RETURN_TO_EPILOG $vgpr0 SI_RETURN_TO_EPILOG $vgpr0
... ...

llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir

Show All 18 Lines
tracksRegLiveness: true tracksRegLiveness: true
machineFunctionInfo: machineFunctionInfo:
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3 scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
scratchWaveOffsetReg: $sgpr4 scratchWaveOffsetReg: $sgpr4
frameOffsetReg: $sgpr5 frameOffsetReg: $sgpr5
stackPtrOffsetReg: $sgpr32 stackPtrOffsetReg: $sgpr32
body: | body: |
bb.0: bb.0:
%0:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec %0:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, 0, implicit $flat_scr, implicit $exec
%2:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec %2:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, 0, implicit $flat_scr, implicit $exec
S_NOP 0, implicit %0 S_NOP 0, implicit %0
%1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0 %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0, 0
%3:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0 %3:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0, 0
S_NOP 0, implicit %1 S_NOP 0, implicit %1
... ...

llvm/trunk/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines bb.12:
%5:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec %5:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
S_BRANCH %bb.11 S_BRANCH %bb.11
bb.13: bb.13:
successors: %bb.15(0x40000000), %bb.14(0x40000000) successors: %bb.15(0x40000000), %bb.14(0x40000000)
%18:vgpr_32 = V_MAD_F32 0, %10.sub0, 0, target-flags(amdgpu-gotprel) 1073741824, 0, -1082130432, 0, 0, implicit $exec %18:vgpr_32 = V_MAD_F32 0, %10.sub0, 0, target-flags(amdgpu-gotprel) 1073741824, 0, -1082130432, 0, 0, implicit $exec
%19:vgpr_32 = V_MAD_F32 0, %12.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $exec %19:vgpr_32 = V_MAD_F32 0, %12.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $exec
%20:sreg_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %21:sreg_128, 1040, 0 :: (dereferenceable invariant load 16) %20:sreg_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %21:sreg_128, 1040, 0, 0 :: (dereferenceable invariant load 16)
%22:vgpr_32 = V_ADD_F32_e32 0, %19, implicit $exec %22:vgpr_32 = V_ADD_F32_e32 0, %19, implicit $exec
%23:vgpr_32 = V_MAD_F32 0, %18, 0, 0, 0, 0, 0, 0, implicit $exec %23:vgpr_32 = V_MAD_F32 0, %18, 0, 0, 0, 0, 0, 0, implicit $exec
%24:vgpr_32 = COPY %20.sub3 %24:vgpr_32 = COPY %20.sub3
%25:vgpr_32 = V_MUL_F32_e64 0, target-flags(amdgpu-gotprel32-lo) 0, 0, %20.sub1, 0, 0, implicit $exec %25:vgpr_32 = V_MUL_F32_e64 0, target-flags(amdgpu-gotprel32-lo) 0, 0, %20.sub1, 0, 0, implicit $exec
%26:sreg_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %27:sreg_128, 1056, 0 :: (dereferenceable invariant load 16) %26:sreg_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %27:sreg_128, 1056, 0, 0 :: (dereferenceable invariant load 16)
%28:vgpr_32 = V_MAD_F32 0, %18, 0, %26.sub0, 0, 0, 0, 0, implicit $exec %28:vgpr_32 = V_MAD_F32 0, %18, 0, %26.sub0, 0, 0, 0, 0, implicit $exec
%29:vgpr_32 = V_ADD_F32_e32 %28, %19, implicit $exec %29:vgpr_32 = V_ADD_F32_e32 %28, %19, implicit $exec
%30:vgpr_32 = V_RCP_F32_e32 %29, implicit $exec %30:vgpr_32 = V_RCP_F32_e32 %29, implicit $exec
%25:vgpr_32 = V_MAC_F32_e32 0, %18, %25, implicit $exec %25:vgpr_32 = V_MAC_F32_e32 0, %18, %25, implicit $exec
%31:vgpr_32 = V_MAD_F32 0, target-flags(amdgpu-gotprel) 0, 0, %12.sub0, 0, %24, 0, 0, implicit $exec %31:vgpr_32 = V_MAD_F32 0, target-flags(amdgpu-gotprel) 0, 0, %12.sub0, 0, %24, 0, 0, implicit $exec
%32:vgpr_32 = V_ADD_F32_e32 %25, %31, implicit $exec %32:vgpr_32 = V_ADD_F32_e32 %25, %31, implicit $exec
%33:vgpr_32 = V_MUL_F32_e32 %22, %30, implicit $exec %33:vgpr_32 = V_MUL_F32_e32 %22, %30, implicit $exec
%34:vgpr_32 = V_MUL_F32_e32 %23, %30, implicit $exec %34:vgpr_32 = V_MUL_F32_e32 %23, %30, implicit $exec
▲ Show 20 Lines • Show All 106 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -stop-after=si-insert-skips < %s | FileCheck --check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -stop-after=si-insert-skips < %s | FileCheck --check-prefix=GCN %s
; GCN-LABEL: name: syncscopes ; GCN-LABEL: name: syncscopes
; GCN: FLAT_STORE_DWORD killed renamable $vgpr1_vgpr2, killed renamable $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store syncscope("agent") seq_cst 4 into %ir.agent_out) ; GCN: FLAT_STORE_DWORD killed renamable $vgpr1_vgpr2, killed renamable $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store syncscope("agent") seq_cst 4 into %ir.agent_out)
; GCN: FLAT_STORE_DWORD killed renamable $vgpr4_vgpr5, killed renamable $vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out) ; GCN: FLAT_STORE_DWORD killed renamable $vgpr4_vgpr5, killed renamable $vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
; GCN: FLAT_STORE_DWORD killed renamable $vgpr7_vgpr8, killed renamable $vgpr6, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out) ; GCN: FLAT_STORE_DWORD killed renamable $vgpr7_vgpr8, killed renamable $vgpr6, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
define void @syncscopes( define void @syncscopes(
i32 %agent, i32 %agent,
i32* %agent_out, i32* %agent_out,
i32 %workgroup, i32 %workgroup,
i32* %workgroup_out, i32* %workgroup_out,
i32 %wavefront, i32 %wavefront,
i32* %wavefront_out) { i32* %wavefront_out) {
entry: entry:
store atomic i32 %agent, i32* %agent_out syncscope("agent") seq_cst, align 4 store atomic i32 %agent, i32* %agent_out syncscope("agent") seq_cst, align 4
store atomic i32 %workgroup, i32* %workgroup_out syncscope("workgroup") seq_cst, align 4 store atomic i32 %workgroup, i32* %workgroup_out syncscope("workgroup") seq_cst, align 4
store atomic i32 %wavefront, i32* %wavefront_out syncscope("wavefront") seq_cst, align 4 store atomic i32 %wavefront, i32* %wavefront_out syncscope("wavefront") seq_cst, align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir

Show All 38 Lines - { id: 0, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
debug-info-location: '' } debug-info-location: '' }
constants: constants:
body: | body: |
bb.0: bb.0:
successors: %bb.1, %bb.2 successors: %bb.1, %bb.2
liveins: $vgpr0, $sgpr4_sgpr5 liveins: $vgpr0, $sgpr4_sgpr5
$vgpr1_vgpr2 = COPY killed $sgpr4_sgpr5, implicit $exec $vgpr1_vgpr2 = COPY killed $sgpr4_sgpr5, implicit $exec
$vgpr1 = GLOBAL_LOAD_UBYTE killed $vgpr1_vgpr2, 0, 0, 0, implicit $exec :: (non-temporal dereferenceable invariant load 1 from `i1 addrspace(4)* undef`) $vgpr1 = GLOBAL_LOAD_UBYTE killed $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec :: (non-temporal dereferenceable invariant load 1 from `i1 addrspace(4)* undef`)
$vcc = V_CMP_NE_U32_e64 0, $vgpr0, implicit $exec $vcc = V_CMP_NE_U32_e64 0, $vgpr0, implicit $exec
$sgpr0_sgpr1 = V_CMP_EQ_U32_e64 1, killed $vgpr1, implicit $exec $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 1, killed $vgpr1, implicit $exec
$vgpr1 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed $sgpr0_sgpr1, implicit $exec $vgpr1 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed $sgpr0_sgpr1, implicit $exec
$sgpr0_sgpr1 = COPY $exec, implicit-def $exec $sgpr0_sgpr1 = COPY $exec, implicit-def $exec
SI_SPILL_S64_SAVE $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (store 8 into %stack.0, align 4, addrspace 5) SI_SPILL_S64_SAVE $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (store 8 into %stack.0, align 4, addrspace 5)
$sgpr2_sgpr3 = S_AND_B64 killed $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc $sgpr2_sgpr3 = S_AND_B64 killed $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
$exec = S_MOV_B64_term killed $sgpr2_sgpr3 $exec = S_MOV_B64_term killed $sgpr2_sgpr3
SI_MASK_BRANCH %bb.2, implicit $exec SI_MASK_BRANCH %bb.2, implicit $exec
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines - { id: 0, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
debug-info-location: '' } debug-info-location: '' }
constants: constants:
body: | body: |
bb.0: bb.0:
successors: %bb.1, %bb.2 successors: %bb.1, %bb.2
liveins: $vgpr0, $sgpr4_sgpr5 liveins: $vgpr0, $sgpr4_sgpr5
$vgpr1_vgpr2 = COPY killed $sgpr4_sgpr5, implicit $exec $vgpr1_vgpr2 = COPY killed $sgpr4_sgpr5, implicit $exec
$vgpr1 = GLOBAL_LOAD_UBYTE killed $vgpr1_vgpr2, 0, 0, 0, implicit $exec :: (non-temporal dereferenceable invariant load 1 from `i1 addrspace(4)* undef`) $vgpr1 = GLOBAL_LOAD_UBYTE killed $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec :: (non-temporal dereferenceable invariant load 1 from `i1 addrspace(4)* undef`)
$vcc = V_CMP_NE_U32_e64 0, $vgpr0, implicit $exec $vcc = V_CMP_NE_U32_e64 0, $vgpr0, implicit $exec
$sgpr0_sgpr1 = V_CMP_EQ_U32_e64 1, killed $vgpr1, implicit $exec $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 1, killed $vgpr1, implicit $exec
$vgpr1 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed $sgpr0_sgpr1, implicit $exec $vgpr1 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed $sgpr0_sgpr1, implicit $exec
$sgpr0_sgpr1 = COPY $exec, implicit-def $exec $sgpr0_sgpr1 = COPY $exec, implicit-def $exec
$sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
SI_SPILL_S64_SAVE killed $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (store 8 into %stack.0, align 4, addrspace 5) SI_SPILL_S64_SAVE killed $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (store 8 into %stack.0, align 4, addrspace 5)
$exec = S_MOV_B64_term killed $sgpr2_sgpr3 $exec = S_MOV_B64_term killed $sgpr2_sgpr3
SI_MASK_BRANCH %bb.2, implicit $exec SI_MASK_BRANCH %bb.2, implicit $exec
Show All 24 Lines

llvm/trunk/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 LinesframeInfo:
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $sgpr0_sgpr1, $vcc liveins: $sgpr0_sgpr1, $vcc
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 11, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
$vcc = V_CMP_EQ_F32_e64 0, 0, 0, undef $sgpr2, 0, implicit $exec $vcc = V_CMP_EQ_F32_e64 0, 0, 0, undef $sgpr2, 0, implicit $exec
S_CBRANCH_VCCZ %bb.1, implicit killed $vcc S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
bb.2.if: bb.2.if:
liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
$vgpr0 = V_MOV_B32_e32 9, implicit $exec $vgpr0 = V_MOV_B32_e32 9, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`) BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
$vgpr0 = V_MOV_B32_e32 0, implicit $exec $vgpr0 = V_MOV_B32_e32 0, implicit $exec
S_BRANCH %bb.3 S_BRANCH %bb.3
bb.1.else: bb.1.else:
liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
$vgpr0 = V_MOV_B32_e32 100, implicit $exec $vgpr0 = V_MOV_B32_e32 100, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`) BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
$vgpr0 = V_MOV_B32_e32 1, implicit $exec $vgpr0 = V_MOV_B32_e32 1, implicit $exec
bb.3.done: bb.3.done:
liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out) BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out)
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# CHECK-LABEL: name: vccz_corrupt_undef_vcc # CHECK-LABEL: name: vccz_corrupt_undef_vcc
# CHECK: S_WAITCNT 3855 # CHECK: S_WAITCNT 3855
# CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 # CHECK-NEXT: $vgpr0 = V_MOV_B32_e32
Show All 19 LinesframeInfo:
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 11, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
S_CBRANCH_VCCZ %bb.1, implicit undef $vcc S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
bb.2.if: bb.2.if:
liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
$vgpr0 = V_MOV_B32_e32 9, implicit $exec $vgpr0 = V_MOV_B32_e32 9, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`) BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
$vgpr0 = V_MOV_B32_e32 0, implicit $exec $vgpr0 = V_MOV_B32_e32 0, implicit $exec
S_BRANCH %bb.3 S_BRANCH %bb.3
bb.1.else: bb.1.else:
liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
$vgpr0 = V_MOV_B32_e32 100, implicit $exec $vgpr0 = V_MOV_B32_e32 100, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`) BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
$vgpr0 = V_MOV_B32_e32 1, implicit $exec $vgpr0 = V_MOV_B32_e32 1, implicit $exec
bb.3.done: bb.3.done:
liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
$sgpr3 = S_MOV_B32 61440 $sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1 $sgpr2 = S_MOV_B32 -1
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out) BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/vmem-vcc-hazard.mir

Show All 13 Linesbody: |
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
$vgpr0 = IMPLICIT_DEF $vgpr0 = IMPLICIT_DEF
$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
bb.1: bb.1:
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: name: vmem_vcc_branch_to_next # GCN-LABEL: name: vmem_vcc_branch_to_next
# GCN: bb.1: # GCN: bb.1:
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
--- ---
name: vmem_vcc_branch_to_next name: vmem_vcc_branch_to_next
body: | body: |
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
$vgpr0 = IMPLICIT_DEF $vgpr0 = IMPLICIT_DEF
$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: name: vmem_vcc_fallthrough_no_hazard_too_far # GCN-LABEL: name: vmem_vcc_fallthrough_no_hazard_too_far
# GCN: bb.1: # GCN: bb.1:
# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
--- ---
name: vmem_vcc_fallthrough_no_hazard_too_far name: vmem_vcc_fallthrough_no_hazard_too_far
body: | body: |
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
$vgpr0 = IMPLICIT_DEF $vgpr0 = IMPLICIT_DEF
$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
$sgpr0 = S_MOV_B32 0 $sgpr0 = S_MOV_B32 0
$sgpr0 = S_MOV_B32 0 $sgpr0 = S_MOV_B32 0
$sgpr0 = S_MOV_B32 0 $sgpr0 = S_MOV_B32 0
$sgpr0 = S_MOV_B32 0 $sgpr0 = S_MOV_B32 0
$sgpr0 = S_MOV_B32 0 $sgpr0 = S_MOV_B32 0
bb.1: bb.1:
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: name: vmem_vcc_fallthrough_no_hazard_nops # GCN-LABEL: name: vmem_vcc_fallthrough_no_hazard_nops
# GCN: bb.1: # GCN: bb.1:
# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
--- ---
name: vmem_vcc_fallthrough_no_hazard_nops name: vmem_vcc_fallthrough_no_hazard_nops
body: | body: |
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
$vgpr0 = IMPLICIT_DEF $vgpr0 = IMPLICIT_DEF
$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
S_NOP 4 S_NOP 4
bb.1: bb.1:
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: name: vmem_vcc_branch_around # GCN-LABEL: name: vmem_vcc_branch_around
# GCN: bb.2: # GCN: bb.2:
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
Show All 12 Lines bb.1:
successors: %bb.2 successors: %bb.2
S_NOP 0 S_NOP 0
S_NOP 0 S_NOP 0
S_NOP 0 S_NOP 0
S_NOP 0 S_NOP 0
bb.2: bb.2:
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: name: vmem_vcc_branch_backedge # GCN-LABEL: name: vmem_vcc_branch_backedge
# GCN: S_NOP # GCN: S_NOP
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
--- ---
name: vmem_vcc_branch_backedge name: vmem_vcc_branch_backedge
body: | body: |
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
$vgpr0 = IMPLICIT_DEF $vgpr0 = IMPLICIT_DEF
$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, implicit $exec
bb.1: bb.1:
$vgpr0 = IMPLICIT_DEF $vgpr0 = IMPLICIT_DEF
$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
S_BRANCH %bb.0 S_BRANCH %bb.0
... ...
# GCN-LABEL: name: vmem_vcc_min_of_two # GCN-LABEL: name: vmem_vcc_min_of_two
# GCN: bb.2: # GCN: bb.2:
Show All 16 Lines bb.0:
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.1: bb.1:
successors: %bb.2 successors: %bb.2
$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
bb.2: bb.2:
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, implicit $exec
... ...
# GCN-LABEL: name: vmem_vcc_self_loop # GCN-LABEL: name: vmem_vcc_self_loop
# GCN: S_NOP # GCN: S_NOP
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
--- ---
name: vmem_vcc_self_loop name: vmem_vcc_self_loop
body: | body: |
bb.0: bb.0:
successors: %bb.0 successors: %bb.0
$vgpr0 = IMPLICIT_DEF $vgpr0 = IMPLICIT_DEF
$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, implicit $exec
$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
S_BRANCH %bb.0 S_BRANCH %bb.0
... ...
# GCN-LABEL: name: vmem_vcc_min_of_two_self_loop1 # GCN-LABEL: name: vmem_vcc_min_of_two_self_loop1
# GCN: bb.1: # GCN: bb.1:
# GCN: $sgpr0 = S_MOV_B32 0 # GCN: $sgpr0 = S_MOV_B32 0
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
Show All 9 Lines bb.0:
$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
$vgpr0 = IMPLICIT_DEF $vgpr0 = IMPLICIT_DEF
$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
bb.1: bb.1:
successors: %bb.1 successors: %bb.1
$sgpr0 = S_MOV_B32 0 $sgpr0 = S_MOV_B32 0
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, implicit $exec
$vgpr1 = V_ADDC_U32_e32 $vgpr1, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec $vgpr1 = V_ADDC_U32_e32 $vgpr1, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
... ...
# GCN-LABEL: name: vmem_vcc_min_of_two_self_loop2 # GCN-LABEL: name: vmem_vcc_min_of_two_self_loop2
# GCN: bb.1: # GCN: bb.1:
# GCN: $sgpr0 = S_MOV_B32 0 # GCN: $sgpr0 = S_MOV_B32 0
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
# GCN-NEXT: S_NOP # GCN-NEXT: S_NOP
Show All 9 Lines bb.0:
$vgpr0 = IMPLICIT_DEF $vgpr0 = IMPLICIT_DEF
$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
S_NOP 0 S_NOP 0
bb.1: bb.1:
successors: %bb.1 successors: %bb.1
$sgpr0 = S_MOV_B32 0 $sgpr0 = S_MOV_B32 0
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, implicit $exec
$vgpr1 = V_ADDC_U32_e32 $vgpr1, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec $vgpr1 = V_ADDC_U32_e32 $vgpr1, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
... ...

llvm/trunk/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir

# RUN: llc -o - %s -march=amdgcn -mcpu=fiji -run-pass=si-insert-waitcnts -verify-machineinstrs | FileCheck -check-prefix=GCN %s # RUN: llc -o - %s -march=amdgcn -mcpu=fiji -run-pass=si-insert-waitcnts -verify-machineinstrs | FileCheck -check-prefix=GCN %s
# GCN-LABEL: waitcnt-back-edge-loop # GCN-LABEL: waitcnt-back-edge-loop
# GCN: bb.2 # GCN: bb.2
# GCN: S_WAITCNT 112 # GCN: S_WAITCNT 112
# GCN: $vgpr5 = V_CVT_I32_F32_e32 killed $vgpr5, implicit $exec # GCN: $vgpr5 = V_CVT_I32_F32_e32 killed $vgpr5, implicit $exec
--- ---
name: waitcnt-back-edge-loop name: waitcnt-back-edge-loop
body: | body: |
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
$vgpr1 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr1_vgpr2 $vgpr1 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr1_vgpr2
$vgpr2 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr1_vgpr2 $vgpr2 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr1_vgpr2
$vgpr4 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1) $vgpr4 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1)
$vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1) $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1)
$sgpr0_sgpr1 = V_CMP_EQ_U32_e64 3, killed $sgpr4, implicit $exec $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 3, killed $sgpr4, implicit $exec
$vgpr3 = V_CNDMASK_B32_e64 0, -1082130432, 0, 1065353216, killed $sgpr0_sgpr1, implicit $exec $vgpr3 = V_CNDMASK_B32_e64 0, -1082130432, 0, 1065353216, killed $sgpr0_sgpr1, implicit $exec
$vgpr5 = V_MOV_B32_e32 $vgpr0, implicit $exec, implicit $exec $vgpr5 = V_MOV_B32_e32 $vgpr0, implicit $exec, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.3: bb.3:
successors: %bb.1 successors: %bb.1
$vgpr5 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1) $vgpr5 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1)
bb.1: bb.1:
successors: %bb.5, %bb.2 successors: %bb.5, %bb.2
$vgpr5 = V_CVT_I32_F32_e32 killed $vgpr5, implicit $exec $vgpr5 = V_CVT_I32_F32_e32 killed $vgpr5, implicit $exec
V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec
$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
S_CBRANCH_VCCZ %bb.5, implicit killed $vcc S_CBRANCH_VCCZ %bb.5, implicit killed $vcc
bb.2: bb.2:
successors: %bb.4, %bb.3 successors: %bb.4, %bb.3
V_CMP_EQ_U32_e32 9, killed $vgpr5, implicit-def $vcc, implicit $exec V_CMP_EQ_U32_e32 9, killed $vgpr5, implicit-def $vcc, implicit $exec
$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
S_CBRANCH_VCCZ %bb.3, implicit killed $vcc S_CBRANCH_VCCZ %bb.3, implicit killed $vcc
bb.4: bb.4:
successors: %bb.3, %bb.1 successors: %bb.3, %bb.1
$vgpr5 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1) $vgpr5 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1)
$vgpr4 = V_CVT_I32_F32_e32 $vgpr5, implicit $exec $vgpr4 = V_CVT_I32_F32_e32 $vgpr5, implicit $exec
V_CMP_EQ_U32_e32 2, killed $vgpr4, implicit-def $vcc, implicit $exec V_CMP_EQ_U32_e32 2, killed $vgpr4, implicit-def $vcc, implicit $exec
$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
$vgpr4 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $exec $vgpr4 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $exec
S_CBRANCH_VCCZ %bb.1, implicit killed $vcc S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
S_BRANCH %bb.3 S_BRANCH %bb.3
bb.5: bb.5:
Show All 39 Lines

llvm/trunk/test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir

Show All 31 Linesbody: |
bb.1: bb.1:
successors: %bb.3, %bb.2 successors: %bb.3, %bb.2
S_CBRANCH_VCCNZ %bb.3, implicit $vcc S_CBRANCH_VCCNZ %bb.3, implicit $vcc
bb.2: bb.2:
successors: %bb.3 successors: %bb.3
renamable $sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM renamable $sgpr0_sgpr1, 0, 0 renamable $sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM renamable $sgpr0_sgpr1, 0, 0, 0
renamable $sgpr3 = S_BUFFER_LOAD_DWORD_IMM killed renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0 renamable $sgpr3 = S_BUFFER_LOAD_DWORD_IMM killed renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0
bb.3: bb.3:
successors: %bb.1, %bb.4 successors: %bb.1, %bb.4
S_CMP_GE_I32 renamable $sgpr2, renamable $sgpr3, implicit-def $scc S_CMP_GE_I32 renamable $sgpr2, renamable $sgpr3, implicit-def $scc
S_CBRANCH_SCC0 %bb.1, implicit killed $scc S_CBRANCH_SCC0 %bb.1, implicit killed $scc
bb.4: bb.4:
Show All 18 Lines
# GCN: S_WAITCNT 3952 # GCN: S_WAITCNT 3952
# GCN: FLAT_STORE_DWORD # GCN: FLAT_STORE_DWORD
# GCN: S_ENDPGM 0 # GCN: S_ENDPGM 0
name: irreducible_loop_extended name: irreducible_loop_extended
body: | body: |
bb.0: bb.0:
successors: %bb.1, %bb.2 successors: %bb.1, %bb.2
$sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM renamable $sgpr2_sgpr3, 0, 0 $sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM renamable $sgpr2_sgpr3, 0, 0, 0
S_CBRANCH_VCCZ %bb.2, implicit $vcc S_CBRANCH_VCCZ %bb.2, implicit $vcc
bb.1: bb.1:
successors: %bb.2 successors: %bb.2
BUFFER_STORE_DWORD_OFFEN_exact killed renamable $vgpr3, renamable $vgpr2, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFEN_exact killed renamable $vgpr3, renamable $vgpr2, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2: bb.2:
successors: %bb.3, %bb.6 successors: %bb.3, %bb.6
S_CBRANCH_VCCNZ %bb.6, implicit $vcc S_CBRANCH_VCCNZ %bb.6, implicit $vcc
bb.3: bb.3:
successors: %bb.4, %bb.5 successors: %bb.4, %bb.5
BUFFER_STORE_DWORD_OFFEN_exact killed renamable $vgpr3, killed renamable $vgpr2, killed renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFEN_exact killed renamable $vgpr3, killed renamable $vgpr2, killed renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
S_CBRANCH_VCCNZ %bb.5, implicit $vcc S_CBRANCH_VCCNZ %bb.5, implicit $vcc
bb.4: bb.4:
successors: %bb.5 successors: %bb.5
renamable $sgpr12_sgpr13_sgpr14_sgpr15 = S_LOAD_DWORDX4_IMM killed renamable $sgpr2_sgpr3, 64, 0 renamable $sgpr12_sgpr13_sgpr14_sgpr15 = S_LOAD_DWORDX4_IMM killed renamable $sgpr2_sgpr3, 64, 0, 0
renamable $vgpr2 = BUFFER_ATOMIC_ADD_OFFSET_RTN killed renamable $vgpr2, killed renamable $sgpr12_sgpr13_sgpr14_sgpr15, 0, 0, 0, implicit $exec renamable $vgpr2 = BUFFER_ATOMIC_ADD_OFFSET_RTN killed renamable $vgpr2, killed renamable $sgpr12_sgpr13_sgpr14_sgpr15, 0, 0, 0, implicit $exec
bb.5: bb.5:
successors: %bb.6 successors: %bb.6
bb.6: bb.6:
FLAT_STORE_DWORD $vgpr3_vgpr4, $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD $vgpr3_vgpr4, $vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/waitcnt-loop-single-basic-block.mir

Show All 9 Lines
# GCN-NEXT: GLOBAL_STORE_DWORD # GCN-NEXT: GLOBAL_STORE_DWORD
... ...
name: waitcnt-loop-single-basic-block name: waitcnt-loop-single-basic-block
body: | body: |
bb.0: bb.0:
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
GLOBAL_STORE_DWORD $vgpr7_vgpr8, $vgpr11, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORD $vgpr7_vgpr8, $vgpr11, 0, 0, 0, 0, implicit $exec
$vgpr21 = GLOBAL_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, implicit $exec $vgpr21 = GLOBAL_LOAD_DWORD $vgpr4_vgpr5, 0, 0, 0, 0, implicit $exec
$vgpr10 = GLOBAL_LOAD_DWORD $vgpr10_vgpr11, 0, 0, 0, implicit $exec $vgpr10 = GLOBAL_LOAD_DWORD $vgpr10_vgpr11, 0, 0, 0, 0, implicit $exec
GLOBAL_STORE_DWORD $vgpr14_vgpr15, $vgpr21, 0, 0, 0, implicit $exec GLOBAL_STORE_DWORD $vgpr14_vgpr15, $vgpr21, 0, 0, 0, 0, implicit $exec
$vgpr11 = GLOBAL_LOAD_DWORD $vgpr11_vgpr12, 0, 0, 0, implicit $exec $vgpr11 = GLOBAL_LOAD_DWORD $vgpr11_vgpr12, 0, 0, 0, 0, implicit $exec
S_CBRANCH_SCC1 %bb.1, implicit $scc S_CBRANCH_SCC1 %bb.1, implicit $scc
bb.2: bb.2:
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/waitcnt-preexisting.mir

Show All 14 Lines--- |
} }
... ...
--- ---
name: test name: test
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0 liveins: $sgpr0, $sgpr1, $vgpr0
renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 480, 0 renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX8_IMM renamable $sgpr0_sgpr1, 480, 0, 0
renamable $vgpr13 = V_LSHLREV_B32_e32 2, killed $vgpr0, implicit $exec renamable $vgpr13 = V_LSHLREV_B32_e32 2, killed $vgpr0, implicit $exec
S_WAITCNT -16257 S_WAITCNT -16257
renamable $vgpr0_vgpr1 = DS_READ2_B32 renamable $vgpr13, 0, 1, 0, implicit $m0, implicit $exec renamable $vgpr0_vgpr1 = DS_READ2_B32 renamable $vgpr13, 0, 1, 0, implicit $m0, implicit $exec
renamable $vgpr2_vgpr3 = DS_READ2_B32 renamable $vgpr13, 2, 3, 0, implicit $m0, implicit $exec renamable $vgpr2_vgpr3 = DS_READ2_B32 renamable $vgpr13, 2, 3, 0, implicit $m0, implicit $exec
renamable $vgpr1 = V_ADD_U32_e32 1, killed $vgpr1, implicit $exec renamable $vgpr1 = V_ADD_U32_e32 1, killed $vgpr1, implicit $exec
renamable $vgpr1 = V_MAX_U32_e32 killed $vgpr0, killed $vgpr1, implicit $exec renamable $vgpr1 = V_MAX_U32_e32 killed $vgpr0, killed $vgpr1, implicit $exec
renamable $vgpr1 = V_MAX_U32_e32 killed $vgpr2, killed $vgpr1, implicit $exec renamable $vgpr1 = V_MAX_U32_e32 killed $vgpr2, killed $vgpr1, implicit $exec
renamable $vgpr1 = V_MAX_U32_e32 killed $vgpr3, killed $vgpr1, implicit $exec renamable $vgpr1 = V_MAX_U32_e32 killed $vgpr3, killed $vgpr1, implicit $exec
$vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $exec $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $exec
$vgpr2 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $exec $vgpr2 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $exec
$vgpr3 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $exec $vgpr3 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $exec
IMAGE_STORE_V4_V2 killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, killed renamable $vgpr0_vgpr1, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, 15, -1, 1, 0, 0, 0, 0, 0, 0, implicit $exec IMAGE_STORE_V4_V2 killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, killed renamable $vgpr0_vgpr1, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, 15, -1, 1, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/AMDGPU/waitcnt.mir

Show All 38 Lines
# GFX89: S_WAITCNT 112 # GFX89: S_WAITCNT 112
# CHECK: FLAT_LOAD_DWORDX4 # CHECK: FLAT_LOAD_DWORDX4
name: flat_zero_waitcnt name: flat_zero_waitcnt
body: | body: |
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
$vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.global4) $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.global4)
$vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 $vgpr7_vgpr8, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16 from %ir.global16) $vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 $vgpr7_vgpr8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16 from %ir.global16)
$vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec
S_BRANCH %bb.1 S_BRANCH %bb.1
bb.1: bb.1:
successors: %bb.2 successors: %bb.2
$vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
$vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 $vgpr7_vgpr8, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16 from %ir.global16) $vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 $vgpr7_vgpr8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16 from %ir.global16)
$vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.2: bb.2:
$vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.flat4) $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.flat4)
$vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 $vgpr7_vgpr8, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16 from %ir.flat16) $vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 $vgpr7_vgpr8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16 from %ir.flat16)
$vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# There is only a single fallthrough successor block, so there's no # There is only a single fallthrough successor block, so there's no
# need to wait immediately. # need to wait immediately.
# CHECK-LABEL: name: single_fallthrough_successor_no_end_block_wait # CHECK-LABEL: name: single_fallthrough_successor_no_end_block_wait
# CHECK: $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2 # CHECK: $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2
# CHECK-NOT: S_WAITCNT # CHECK-NOT: S_WAITCNT
# CHECK: bb.1: # CHECK: bb.1:
# CHECK-NEXT: V_LSHLREV_B64 # CHECK-NEXT: V_LSHLREV_B64
# CHECK-NEXT: S_WAITCNT 112 # CHECK-NEXT: S_WAITCNT 112
# CHECK-NEXT: FLAT_STORE_DWORD # CHECK-NEXT: FLAT_STORE_DWORD
name: single_fallthrough_successor_no_end_block_wait name: single_fallthrough_successor_no_end_block_wait
body: | body: |
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
$vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
bb.1: bb.1:
$vgpr3_vgpr4 = V_LSHLREV_B64 4, $vgpr7_vgpr8, implicit $exec $vgpr3_vgpr4 = V_LSHLREV_B64 4, $vgpr7_vgpr8, implicit $exec
FLAT_STORE_DWORD $vgpr3_vgpr4, $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD $vgpr3_vgpr4, $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
# The block has a single predecessor with a single successor, but it # The block has a single predecessor with a single successor, but it
# is not the next block so it's non-obvious that the wait is not needed. # is not the next block so it's non-obvious that the wait is not needed.
# CHECK-LABEL: name: single_branch_successor_not_next_block # CHECK-LABEL: name: single_branch_successor_not_next_block
# CHECK: bb.1 # CHECK: bb.1
# CHECK-NEXT: FLAT_STORE_DWORD # CHECK-NEXT: FLAT_STORE_DWORD
# CHECK-NEXT: S_ENDPGM 0 # CHECK-NEXT: S_ENDPGM 0
# CHECK: bb.2: # CHECK: bb.2:
# CHECK-NEXT: V_LSHLREV_B64 # CHECK-NEXT: V_LSHLREV_B64
# CHECK-NEXT: S_WAITCNT 112 # CHECK-NEXT: S_WAITCNT 112
# CHECK-NEXT: FLAT_STORE_DWORD # CHECK-NEXT: FLAT_STORE_DWORD
name: single_branch_successor_not_next_block name: single_branch_successor_not_next_block
body: | body: |
bb.0: bb.0:
successors: %bb.2 successors: %bb.2
$vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_BRANCH %bb.2 S_BRANCH %bb.2
bb.1: bb.1:
FLAT_STORE_DWORD $vgpr8_vgpr9, $vgpr10, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD $vgpr8_vgpr9, $vgpr10, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
bb.2: bb.2:
$vgpr3_vgpr4 = V_LSHLREV_B64 4, $vgpr7_vgpr8, implicit $exec $vgpr3_vgpr4 = V_LSHLREV_B64 4, $vgpr7_vgpr8, implicit $exec
FLAT_STORE_DWORD $vgpr3_vgpr4, $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD $vgpr3_vgpr4, $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir

Show All 10 Lines bb.0:
%10:sreg_32_xm0 = S_MOV_B32 61440 %10:sreg_32_xm0 = S_MOV_B32 61440
%11:sreg_32_xm0 = S_MOV_B32 0 %11:sreg_32_xm0 = S_MOV_B32 0
%3:vgpr_32 = COPY $vgpr0 %3:vgpr_32 = COPY $vgpr0
%vreg123_0:vgpr_32 = COPY %3 %vreg123_0:vgpr_32 = COPY %3
%0:sgpr_64 = COPY $sgpr0_sgpr1 %0:sgpr_64 = COPY $sgpr0_sgpr1
%vreg123_1:vgpr_32 = COPY %11 %vreg123_1:vgpr_32 = COPY %11
%27:vreg_64 = REG_SEQUENCE %vreg123_0, %subreg.sub0, %vreg123_1, %subreg.sub1 %27:vreg_64 = REG_SEQUENCE %vreg123_0, %subreg.sub0, %vreg123_1, %subreg.sub1
%4:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 9, 0 %4:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
%vreg123_2:vgpr_32 = COPY %4 %vreg123_2:vgpr_32 = COPY %4
%5:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 11, 0 %5:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
%vreg123_3:vgpr_32 = COPY %5 %vreg123_3:vgpr_32 = COPY %5
%16:sgpr_128 = REG_SEQUENCE killed %vreg123_0, %subreg.sub0, %vreg123_1, %subreg.sub1, %vreg123_2, %subreg.sub2, %vreg123_3, %subreg.sub3 %16:sgpr_128 = REG_SEQUENCE killed %vreg123_0, %subreg.sub0, %vreg123_1, %subreg.sub1, %vreg123_2, %subreg.sub2, %vreg123_3, %subreg.sub3
BUFFER_STORE_DWORD_ADDR64 %vreg123_1, %27, killed %16, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_ADDR64 %vreg123_1, %27, killed %16, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir

# RUN: llc -march=amdgcn -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
# Previously getReservedRegs was called before parsing # Previously getReservedRegs was called before parsing
# machineFunctionInfo, but the AMDGPU implementation depends on # machineFunctionInfo, but the AMDGPU implementation depends on
# setting register fields to reserve there. $sgpr50 would then not be # setting register fields to reserve there. $sgpr50 would then not be
# reserved, resulting in a verifier error from an undefined register. # reserved, resulting in a verifier error from an undefined register.
--- ---
# CHECK: machineFunctionInfo: # CHECK: machineFunctionInfo:
# CHECK: isEntryFunction: true # CHECK: isEntryFunction: true
# CHECK: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' # CHECK: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
# CHECK: scratchWaveOffsetReg: '$sgpr50' # CHECK: scratchWaveOffsetReg: '$sgpr50'
# CHECK: frameOffsetReg: '$sgpr50' # CHECK: frameOffsetReg: '$sgpr50'
# CHECK: renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50, 4, 0, 0, 0, implicit $exec :: (load 4, addrspace 5) # CHECK: renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50, 4, 0, 0, 0, 0, implicit $exec :: (load 4, addrspace 5)
name: reserve_correct_register name: reserve_correct_register
tracksRegLiveness: true tracksRegLiveness: true
machineFunctionInfo: machineFunctionInfo:
isEntryFunction: true isEntryFunction: true
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
scratchWaveOffsetReg: '$sgpr50' scratchWaveOffsetReg: '$sgpr50'
frameOffsetReg: '$sgpr50' frameOffsetReg: '$sgpr50'
stack: stack:
- { id: 0, type: default, offset: 0, size: 4, alignment: 4 } - { id: 0, type: default, offset: 0, size: 4, alignment: 4 }
body: | body: |
bb.0: bb.0:
renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50, 4, 0, 0, 0, implicit $exec :: (load 4, addrspace 5) renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50, 4, 0, 0, 0, 0, implicit $exec :: (load 4, addrspace 5)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/MIR/AMDGPU/syncscopes.mir

Show All 36 Lines--- |
attributes #0 = { "target-cpu"="gfx803" } attributes #0 = { "target-cpu"="gfx803" }
attributes #1 = { convergent nounwind } attributes #1 = { convergent nounwind }
attributes #2 = { convergent nounwind readnone } attributes #2 = { convergent nounwind readnone }
!0 = !{i32 1} !0 = !{i32 1}
# GCN-LABEL: name: syncscopes # GCN-LABEL: name: syncscopes
# GCN: FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("agent") seq_cst 4 into %ir.agent_out, addrspace 4) # GCN: FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("agent") seq_cst 4 into %ir.agent_out, addrspace 4)
# GCN: FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out, addrspace 4) # GCN: FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out, addrspace 4)
# GCN: FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out, addrspace 4) # GCN: FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out, addrspace 4)
... ...
--- ---
name: syncscopes name: syncscopes
alignment: 0 alignment: 0
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 13 LinesframeInfo:
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $sgpr4_sgpr5 liveins: $sgpr4_sgpr5
S_WAITCNT 0 S_WAITCNT 0
$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr4_sgpr5, 8, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr4_sgpr5, 8, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
$sgpr6 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) $sgpr6 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
$sgpr2_sgpr3 = S_LOAD_DWORDX2_IMM $sgpr4_sgpr5, 24, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) $sgpr2_sgpr3 = S_LOAD_DWORDX2_IMM $sgpr4_sgpr5, 24, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
$sgpr7 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 16, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) $sgpr7 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 16, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
$sgpr8 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 32, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`) $sgpr8 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 32, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
S_WAITCNT 127 S_WAITCNT 127
$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
$sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr4_sgpr5, 40, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr4_sgpr5, 40, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit killed $sgpr0_sgpr1, implicit $sgpr0_sgpr1, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit killed $sgpr0_sgpr1, implicit $sgpr0_sgpr1, implicit $exec
$vgpr2 = V_MOV_B32_e32 killed $sgpr6, implicit $exec, implicit $exec $vgpr2 = V_MOV_B32_e32 killed $sgpr6, implicit $exec, implicit $exec
FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("agent") seq_cst 4 into %ir.agent_out) FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("agent") seq_cst 4 into %ir.agent_out)
S_WAITCNT 112 S_WAITCNT 112
$vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr2_sgpr3 $vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr2_sgpr3
$vgpr1 = V_MOV_B32_e32 killed $sgpr3, implicit $exec, implicit killed $sgpr2_sgpr3, implicit $sgpr2_sgpr3, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr3, implicit $exec, implicit killed $sgpr2_sgpr3, implicit $sgpr2_sgpr3, implicit $exec
$vgpr2 = V_MOV_B32_e32 killed $sgpr7, implicit $exec, implicit $exec $vgpr2 = V_MOV_B32_e32 killed $sgpr7, implicit $exec, implicit $exec
FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out) FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
S_WAITCNT 112 S_WAITCNT 112
$vgpr0 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr4_sgpr5 $vgpr0 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr4_sgpr5
$vgpr1 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit killed $sgpr4_sgpr5, implicit $sgpr4_sgpr5, implicit $exec $vgpr1 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit killed $sgpr4_sgpr5, implicit $sgpr4_sgpr5, implicit $exec
$vgpr2 = V_MOV_B32_e32 killed $sgpr8, implicit $exec, implicit $exec $vgpr2 = V_MOV_B32_e32 killed $sgpr8, implicit $exec, implicit $exec
FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out) FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir

Show All 34 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$sgpr2_sgpr3 = S_GETPC_B64 $sgpr2_sgpr3 = S_GETPC_B64
; CHECK: $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc ; CHECK: $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc
$sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc
$sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
$sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc
$sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11, 0 $sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11, 0, 0
$sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc
$sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc
$sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc
$sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
$sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
$sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
$sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0 $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0, 0
$sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9, 0 $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9, 0, 0
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...
--- ---
name: float2 name: float2
liveins: liveins:
- { reg: '$sgpr0_sgpr1' } - { reg: '$sgpr0_sgpr1' }
frameInfo: frameInfo:
maxAlignment: 8 maxAlignment: 8
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
$sgpr2_sgpr3 = S_GETPC_B64 $sgpr2_sgpr3 = S_GETPC_B64
; CHECK: $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc ; CHECK: $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc
$sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc
$sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
$sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc
$sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11, 0 $sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11, 0, 0
$sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc
$sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc
$sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc
$sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
$sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
$sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
$sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0 $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0, 0
$sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9, 0 $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9, 0, 0
$sgpr7 = S_MOV_B32 61440 $sgpr7 = S_MOV_B32 61440
$sgpr6 = S_MOV_B32 -1 $sgpr6 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM 0 S_ENDPGM 0
... ...

llvm/trunk/test/MC/AMDGPU/flat-gfx10.s

// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W32-ERR %s
flat_load_dword v1, v[3:4]
// GFX10: encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x7d,0x01]
flat_load_dword v1, v[3:4] offset:-1
// GFX10-ERR: error: invalid operand for instruction
flat_load_dword v1, v[3:4] offset:2047
// GFX10: encoding: [0xff,0x07,0x30,0xdc,0x03,0x00,0x7d,0x01]
flat_load_dword v1, v[3:4] offset:2048
// GFX10-ERR: error: invalid operand for instruction
flat_load_dword v1, v[3:4] offset:4 glc
// GFX10: encoding: [0x04,0x00,0x31,0xdc,0x03,0x00,0x7d,0x01]
flat_load_dword v1, v[3:4] offset:4 glc slc
// GFX10: encoding: [0x04,0x00,0x33,0xdc,0x03,0x00,0x7d,0x01]
flat_load_dword v1, v[3:4] offset:4 glc slc dlc
// GFX10: encoding: [0x04,0x10,0x33,0xdc,0x03,0x00,0x7d,0x01]
flat_atomic_add v[3:4], v5 offset:8 slc
// GFX10: encoding: [0x08,0x00,0xca,0xdc,0x03,0x05,0x7d,0x00]
flat_atomic_cmpswap v[1:2], v[3:4] offset:2047
// GFX10: encoding: [0xff,0x07,0xc4,0xdc,0x01,0x03,0x7d,0x00]
flat_atomic_cmpswap v[1:2], v[3:4] offset:2047 slc
// GFX10: encoding: [0xff,0x07,0xc6,0xdc,0x01,0x03,0x7d,0x00]
flat_atomic_cmpswap v[1:2], v[3:4]
// GFX10: encoding: [0x00,0x00,0xc4,0xdc,0x01,0x03,0x7d,0x00]
flat_atomic_cmpswap v[1:2], v[3:4] slc
// GFX10: encoding: [0x00,0x00,0xc6,0xdc,0x01,0x03,0x7d,0x00]
flat_atomic_cmpswap v[1:2], v[3:4] offset:2047 glc
// GFX10-ERR: error: invalid operand for instruction
flat_atomic_cmpswap v[1:2], v[3:4] glc
// GFX10-ERR: error: invalid operand for instruction
flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047 glc
// GFX10: encoding: [0xff,0x07,0xc5,0xdc,0x01,0x03,0x7d,0x00]
flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047 glc slc
// GFX10: encoding: [0xff,0x07,0xc7,0xdc,0x01,0x03,0x7d,0x00]
flat_atomic_cmpswap v0, v[1:2], v[3:4] glc
// GFX10: encoding: [0x00,0x00,0xc5,0xdc,0x01,0x03,0x7d,0x00]
flat_atomic_cmpswap v0, v[1:2], v[3:4] glc slc
// GFX10: encoding: [0x00,0x00,0xc7,0xdc,0x01,0x03,0x7d,0x00]
flat_atomic_cmpswap v0, v[1:2], v[3:4] glc
// GFX10: encoding: [0x00,0x00,0xc5,0xdc,0x01,0x03,0x7d,0x00]
flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047
// GFX10-ERR: error: too few operands for instruction
flat_atomic_cmpswap v0, v[1:2], v[3:4] slc
// GFX10-ERR: error: invalid operand for instruction
flat_atomic_swap v[3:4], v5 offset:16
// GFX10: encoding: [0x10,0x00,0xc0,0xdc,0x03,0x05,0x7d,0x00]
flat_store_dword v[3:4], v1 offset:16
// GFX10: encoding: [0x10,0x00,0x70,0xdc,0x03,0x01,0x7d,0x00]
flat_store_dword v[3:4], v1, off
// GFX10-ERR: error: invalid operand for instruction
flat_store_dword v[3:4], v1, s[0:1]
// GFX10-ERR: error: invalid operand for instruction
flat_store_dword v[3:4], v1, s0
// GFX10-ERR: error: invalid operand for instruction
flat_load_dword v1, v[3:4], off
// GFX10-ERR: error: invalid operand for instruction
flat_load_dword v1, v[3:4], s[0:1]
// GFX10-ERR: error: invalid operand for instruction
flat_load_dword v1, v[3:4], s0
// GFX10-ERR: error: invalid operand for instruction
flat_load_dword v1, v[3:4], exec_hi
// GFX10-ERR: error: invalid operand for instruction
flat_store_dword v[3:4], v1, exec_hi
// GFX10-ERR: error: invalid operand for instruction
flat_load_ubyte_d16 v1, v[3:4]
// GFX10: encoding: [0x00,0x00,0x80,0xdc,0x03,0x00,0x7d,0x01]
flat_load_ubyte_d16_hi v1, v[3:4]
// GFX10: encoding: [0x00,0x00,0x84,0xdc,0x03,0x00,0x7d,0x01]
flat_load_sbyte_d16 v1, v[3:4]
// GFX10: encoding: [0x00,0x00,0x88,0xdc,0x03,0x00,0x7d,0x01]
flat_load_sbyte_d16_hi v1, v[3:4]
// GFX10: encoding: [0x00,0x00,0x8c,0xdc,0x03,0x00,0x7d,0x01]
flat_load_short_d16 v1, v[3:4]
// GFX10: encoding: [0x00,0x00,0x90,0xdc,0x03,0x00,0x7d,0x01]
flat_load_short_d16_hi v1, v[3:4]
// GFX10: encoding: [0x00,0x00,0x94,0xdc,0x03,0x00,0x7d,0x01]
flat_store_byte_d16_hi v[3:4], v1
// GFX10: encoding: [0x00,0x00,0x64,0xdc,0x03,0x01,0x7d,0x00]
flat_store_short_d16_hi v[3:4], v1
// GFX10: encoding: [0x00,0x00,0x6c,0xdc,0x03,0x01,0x7d,0x00]

llvm/trunk/test/MC/AMDGPU/flat-global.s

// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding 2>&1 %s | FileCheck -check-prefix=GFX9-ERR -check-prefix=GCNERR %s // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding 2>&1 %s | FileCheck -check-prefix=GFX9-ERR -check-prefix=GCNERR %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding 2>&1 %s | FileCheck -check-prefix=VI-ERR -check-prefix=GCNERR %s // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding 2>&1 %s | FileCheck -check-prefix=VI-ERR -check-prefix=GCNERR %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GFX10 %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR %s
global_load_ubyte v1, v[3:4], off global_load_ubyte v1, v[3:4], off
// GFX10: encoding: [0x00,0x80,0x20,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_ubyte v1, v[3:4], off ; encoding: [0x00,0x80,0x40,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_ubyte v1, v[3:4], off ; encoding: [0x00,0x80,0x40,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_ubyte v1, v[3:4], off dlc
// GFX10: encoding: [0x00,0x90,0x20,0xdc,0x03,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
global_load_sbyte v1, v[3:4], off global_load_sbyte v1, v[3:4], off
// GFX10: encoding: [0x00,0x80,0x24,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_sbyte v1, v[3:4], off ; encoding: [0x00,0x80,0x44,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_sbyte v1, v[3:4], off ; encoding: [0x00,0x80,0x44,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_sbyte v1, v[3:4], off dlc
// GFX10: encoding: [0x00,0x90,0x24,0xdc,0x03,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
global_load_ushort v1, v[3:4], off global_load_ushort v1, v[3:4], off
// GFX10: encoding: [0x00,0x80,0x28,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_ushort v1, v[3:4], off ; encoding: [0x00,0x80,0x48,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_ushort v1, v[3:4], off ; encoding: [0x00,0x80,0x48,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_ushort v1, v[3:4], off dlc
// GFX10: encoding: [0x00,0x90,0x28,0xdc,0x03,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
global_load_sshort v1, v[3:4], off global_load_sshort v1, v[3:4], off
// GFX10: encoding: [0x00,0x80,0x2c,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_sshort v1, v[3:4], off ; encoding: [0x00,0x80,0x4c,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_sshort v1, v[3:4], off ; encoding: [0x00,0x80,0x4c,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_sshort v1, v[3:4], off dlc
// GFX10: encoding: [0x00,0x90,0x2c,0xdc,0x03,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
global_load_dword v1, v[3:4], off global_load_dword v1, v[3:4], off
// GFX10: encoding: [0x00,0x80,0x30,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_dword v1, v[3:4], off ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_dword v1, v[3:4], off ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_dword v1, v[3:4], off dlc
// GFX10: encoding: [0x00,0x90,0x30,0xdc,0x03,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
global_load_dwordx2 v[1:2], v[3:4], off global_load_dwordx2 v[1:2], v[3:4], off
// GFX10: encoding: [0x00,0x80,0x34,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_dwordx2 v[1:2], v[3:4], off ; encoding: [0x00,0x80,0x54,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_dwordx2 v[1:2], v[3:4], off ; encoding: [0x00,0x80,0x54,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_dwordx2 v[1:2], v[3:4], off dlc
// GFX10: encoding: [0x00,0x90,0x34,0xdc,0x03,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
global_load_dwordx3 v[1:3], v[3:4], off global_load_dwordx3 v[1:3], v[3:4], off
// GFX10: encoding: [0x00,0x80,0x3c,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_dwordx3 v[1:3], v[3:4], off ; encoding: [0x00,0x80,0x58,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_dwordx3 v[1:3], v[3:4], off ; encoding: [0x00,0x80,0x58,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_dwordx3 v[1:3], v[3:4], off dlc
// GFX10: encoding: [0x00,0x90,0x3c,0xdc,0x03,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
global_load_dwordx4 v[1:4], v[3:4], off global_load_dwordx4 v[1:4], v[3:4], off
// GFX10: encoding: [0x00,0x80,0x38,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_dwordx4 v[1:4], v[3:4], off ; encoding: [0x00,0x80,0x5c,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_dwordx4 v[1:4], v[3:4], off ; encoding: [0x00,0x80,0x5c,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_dwordx4 v[1:4], v[3:4], off dlc
// GFX10: encoding: [0x00,0x90,0x38,0xdc,0x03,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
// FIXME: VI error should be instruction nto supported // FIXME: VI error should be instruction nto supported
global_load_dword v1, v[3:4], off offset:0 global_load_dword v1, v[3:4], off offset:0
// GFX10: encoding: [0x00,0x80,0x30,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_dword v1, v[3:4], off ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_dword v1, v[3:4], off ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: :41: error: not a valid operand. // VI-ERR: :41: error: not a valid operand.
global_load_dword v1, v[3:4], off offset:4095 global_load_dword v1, v[3:4], off offset:4095
// GFX10-ERR: error: invalid operand for instruction
// GFX9: global_load_dword v1, v[3:4], off offset:4095 ; encoding: [0xff,0x8f,0x50,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_dword v1, v[3:4], off offset:4095 ; encoding: [0xff,0x8f,0x50,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: :41: error: not a valid operand. // VI-ERR: :41: error: not a valid operand.
global_load_dword v1, v[3:4], off offset:-1 global_load_dword v1, v[3:4], off offset:-1
// GFX10: encoding: [0xff,0x8f,0x30,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_dword v1, v[3:4], off offset:-1 ; encoding: [0xff,0x9f,0x50,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_dword v1, v[3:4], off offset:-1 ; encoding: [0xff,0x9f,0x50,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: :41: error: not a valid operand. // VI-ERR: :41: error: not a valid operand.
global_load_dword v1, v[3:4], off offset:-4096 global_load_dword v1, v[3:4], off offset:-4096
// GFX10-ERR: error: invalid operand for instruction
// GFX9: global_load_dword v1, v[3:4], off offset:-4096 ; encoding: [0x00,0x90,0x50,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_dword v1, v[3:4], off offset:-4096 ; encoding: [0x00,0x90,0x50,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: :41: error: not a valid operand. // VI-ERR: :41: error: not a valid operand.
global_load_dword v1, v[3:4], off offset:4096 global_load_dword v1, v[3:4], off offset:4096
// GFX10-ERR: error: invalid operand for instruction
// GFX9-ERR: :35: error: invalid operand for instruction // GFX9-ERR: :35: error: invalid operand for instruction
// VI-ERR: :41: error: not a valid operand. // VI-ERR: :41: error: not a valid operand.
global_load_dword v1, v[3:4] off, offset:-4097 global_load_dword v1, v[3:4] off, offset:-4097
// GFX10-ERR: error: invalid operand for instruction
// GFX9-ERR: :35: error: invalid operand for instruction // GFX9-ERR: :35: error: invalid operand for instruction
// VI-ERR: :41: error: not a valid operand. // VI-ERR: :41: error: not a valid operand.
global_store_byte v[3:4], v1, off global_store_byte v[3:4], v1, off
// GFX10: encoding: [0x00,0x80,0x60,0xdc,0x03,0x01,0x7d,0x00]
// GFX9: global_store_byte v[3:4], v1, off ; encoding: [0x00,0x80,0x60,0xdc,0x03,0x01,0x7f,0x00] // GFX9: global_store_byte v[3:4], v1, off ; encoding: [0x00,0x80,0x60,0xdc,0x03,0x01,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_store_byte v[3:4], v1, off dlc
// GFX10: encoding: [0x00,0x90,0x60,0xdc,0x03,0x01,0x7d,0x00]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
global_store_short v[3:4], v1, off global_store_short v[3:4], v1, off
// GFX10: encoding: [0x00,0x80,0x68,0xdc,0x03,0x01,0x7d,0x00]
// GFX9: global_store_short v[3:4], v1, off ; encoding: [0x00,0x80,0x68,0xdc,0x03,0x01,0x7f,0x00] // GFX9: global_store_short v[3:4], v1, off ; encoding: [0x00,0x80,0x68,0xdc,0x03,0x01,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_store_short v[3:4], v1, off dlc
// GFX10: encoding: [0x00,0x90,0x68,0xdc,0x03,0x01,0x7d,0x00]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
global_store_dword v[3:4], v1, off global_store_dword v[3:4], v1, off
// GFX10: encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7d,0x00]
// GFX9: global_store_dword v[3:4], v1, off ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7f,0x00] // GFX9: global_store_dword v[3:4], v1, off ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_store_dword v[3:4], v1, off dlc
// GFX10: encoding: [0x00,0x90,0x70,0xdc,0x03,0x01,0x7d,0x00]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
global_store_dwordx2 v[3:4], v[1:2], off global_store_dwordx2 v[3:4], v[1:2], off
// GFX10: encoding: [0x00,0x80,0x74,0xdc,0x03,0x01,0x7d,0x00]
// GFX9: global_store_dwordx2 v[3:4], v[1:2], off ; encoding: [0x00,0x80,0x74,0xdc,0x03,0x01,0x7f,0x00] // GFX9: global_store_dwordx2 v[3:4], v[1:2], off ; encoding: [0x00,0x80,0x74,0xdc,0x03,0x01,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_store_dwordx2 v[3:4], v[1:2], off dlc
// GFX10: encoding: [0x00,0x90,0x74,0xdc,0x03,0x01,0x7d,0x00]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
global_store_dwordx3 v[3:4], v[1:3], off global_store_dwordx3 v[3:4], v[1:3], off
// GFX10: encoding: [0x00,0x80,0x7c,0xdc,0x03,0x01,0x7d,0x00]
// GFX9: global_store_dwordx3 v[3:4], v[1:3], off ; encoding: [0x00,0x80,0x78,0xdc,0x03,0x01,0x7f,0x00] // GFX9: global_store_dwordx3 v[3:4], v[1:3], off ; encoding: [0x00,0x80,0x78,0xdc,0x03,0x01,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_store_dwordx3 v[3:4], v[1:3], off dlc
// GFX10: encoding: [0x00,0x90,0x7c,0xdc,0x03,0x01,0x7d,0x00]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
global_store_dwordx4 v[3:4], v[1:4], off global_store_dwordx4 v[3:4], v[1:4], off
// GFX10: encoding: [0x00,0x80,0x78,0xdc,0x03,0x01,0x7d,0x00]
// GFX9: global_store_dwordx4 v[3:4], v[1:4], off ; encoding: [0x00,0x80,0x7c,0xdc,0x03,0x01,0x7f,0x00] // GFX9: global_store_dwordx4 v[3:4], v[1:4], off ; encoding: [0x00,0x80,0x7c,0xdc,0x03,0x01,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_store_dwordx4 v[3:4], v[1:4], off dlc
// GFX10: encoding: [0x00,0x90,0x78,0xdc,0x03,0x01,0x7d,0x00]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
global_store_dword v[3:4], v1, off offset:12 global_store_dword v[3:4], v1, off offset:12
// GFX10: encoding: [0x0c,0x80,0x70,0xdc,0x03,0x01,0x7d,0x00]
// GFX9: global_store_dword v[3:4], v1, off offset:12 ; encoding: [0x0c,0x80,0x70,0xdc,0x03,0x01,0x7f,0x00] // GFX9: global_store_dword v[3:4], v1, off offset:12 ; encoding: [0x0c,0x80,0x70,0xdc,0x03,0x01,0x7f,0x00]
// VI-ERR: :42: error: not a valid operand // VI-ERR: :42: error: not a valid operand
global_load_dword v1, v[3:4], s[2:3] global_load_dword v1, v[3:4], s[2:3]
// GFX10: encoding: [0x00,0x80,0x30,0xdc,0x03,0x00,0x02,0x01]
// GFX9: global_load_dword v1, v[3:4], s[2:3] ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x02,0x01] // GFX9: global_load_dword v1, v[3:4], s[2:3] ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x02,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_dword v1, v[3:4], s[2:3] offset:24 global_load_dword v1, v[3:4], s[2:3] offset:24
// GFX10: encoding: [0x18,0x80,0x30,0xdc,0x03,0x00,0x02,0x01]
// GFX9: global_load_dword v1, v[3:4], s[2:3] offset:24 ; encoding: [0x18,0x80,0x50,0xdc,0x03,0x00,0x02,0x01] // GFX9: global_load_dword v1, v[3:4], s[2:3] offset:24 ; encoding: [0x18,0x80,0x50,0xdc,0x03,0x00,0x02,0x01]
// VI-ERR: :44: error: not a valid operand. // VI-ERR: :44: error: not a valid operand.
global_load_dword v1, v[3:4], s[2:3] offset:-8 global_load_dword v1, v[3:4], s[2:3] offset:-8
// GFX10: encoding: [0xf8,0x8f,0x30,0xdc,0x03,0x00,0x02,0x01]
// GFX9: global_load_dword v1, v[3:4], s[2:3] offset:-8 ; encoding: [0xf8,0x9f,0x50,0xdc,0x03,0x00,0x02,0x01] // GFX9: global_load_dword v1, v[3:4], s[2:3] offset:-8 ; encoding: [0xf8,0x9f,0x50,0xdc,0x03,0x00,0x02,0x01]
// VI-ERR: :44: error: not a valid operand. // VI-ERR: :44: error: not a valid operand.
global_store_dword v[3:4], v1, s[2:3] global_store_dword v[3:4], v1, s[2:3]
// GFX10: encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00]
// GFX9: global_store_dword v[3:4], v1, s[2:3] ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00] // GFX9: global_store_dword v[3:4], v1, s[2:3] ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_store_dword v[3:4], v1, s[2:3] offset:24 global_store_dword v[3:4], v1, s[2:3] offset:24
// GFX10: encoding: [0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00]
// GFX9: global_store_dword v[3:4], v1, s[2:3] offset:24 ; encoding: [0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00] // GFX9: global_store_dword v[3:4], v1, s[2:3] offset:24 ; encoding: [0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00]
// VI-ERR: :45: error: not a valid operand. // VI-ERR: :45: error: not a valid operand.
global_store_dword v[3:4], v1, s[2:3] offset:-8 global_store_dword v[3:4], v1, s[2:3] offset:-8
// GFX10: encoding: [0xf8,0x8f,0x70,0xdc,0x03,0x01,0x02,0x00]
// GFX9: global_store_dword v[3:4], v1, s[2:3] offset:-8 ; encoding: [0xf8,0x9f,0x70,0xdc,0x03,0x01,0x02,0x00] // GFX9: global_store_dword v[3:4], v1, s[2:3] offset:-8 ; encoding: [0xf8,0x9f,0x70,0xdc,0x03,0x01,0x02,0x00]
// VI-ERR: :45: error: not a valid operand. // VI-ERR: :45: error: not a valid operand.
// XXX: Is this valid? // XXX: Is this valid?
global_store_dword v[3:4], v1, exec global_store_dword v[3:4], v1, exec
// GFX10: encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00]
// GFX9: global_store_dword v[3:4], v1, exec ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00] // GFX9: global_store_dword v[3:4], v1, exec ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_dword v1, v[3:4], s2 global_load_dword v1, v[3:4], s2
// GFX10-ERR: error: invalid operand for instruction
// GFX9-ERR: :31: error: invalid operand for instruction // GFX9-ERR: :31: error: invalid operand for instruction
// VI-ERR: :31: error: invalid operand for instruction // VI-ERR: :31: error: invalid operand for instruction
global_load_dword v1, v[3:4], exec_hi global_load_dword v1, v[3:4], exec_hi
// GFX10-ERR: error: invalid operand for instruction
// GFX9-ERR: :31: error: invalid operand for instruction // GFX9-ERR: :31: error: invalid operand for instruction
// VI-ERR: :31: error: invalid operand for instruction // VI-ERR: :31: error: invalid operand for instruction
global_atomic_cmpswap v[3:4], v[5:6], off global_atomic_cmpswap v[3:4], v[5:6], off
// GFX10: encoding: [0x00,0x80,0xc4,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_cmpswap v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x04,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_cmpswap v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x04,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: error: instruction not supported on this GPU // VI-ERR: error: instruction not supported on this GPU
global_atomic_cmpswap_x2 v[3:4], v[5:8], off global_atomic_cmpswap_x2 v[3:4], v[5:8], off
// GFX10: encoding: [0x00,0x80,0x44,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_cmpswap_x2 v[3:4], v[5:8], off ; encoding: [0x00,0x80,0x84,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_cmpswap_x2 v[3:4], v[5:8], off ; encoding: [0x00,0x80,0x84,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: error: instruction not supported on this GPU // VI-ERR: error: instruction not supported on this GPU
global_atomic_swap v[3:4], v5, off global_atomic_swap v[3:4], v5, off
// GFX10: encoding: [0x00,0x80,0xc0,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_swap v[3:4], v5, off ; encoding: [0x00,0x80,0x00,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_swap v[3:4], v5, off ; encoding: [0x00,0x80,0x00,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: error: instruction not supported on this GPU // VI-ERR: error: instruction not supported on this GPU
global_atomic_swap_x2 v[3:4], v[5:6], off global_atomic_swap_x2 v[3:4], v[5:6], off
// GFX10: encoding: [0x00,0x80,0x40,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_swap_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x80,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_swap_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x80,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: error: instruction not supported on this GPU // VI-ERR: error: instruction not supported on this GPU
global_atomic_add v[3:4], v5, off global_atomic_add v[3:4], v5, off
// GFX10: encoding: [0x00,0x80,0xc8,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_add v[3:4], v5, off ; encoding: [0x00,0x80,0x08,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_add v[3:4], v5, off ; encoding: [0x00,0x80,0x08,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_sub v[3:4], v5, off global_atomic_sub v[3:4], v5, off
// GFX10: encoding: [0x00,0x80,0xcc,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_sub v[3:4], v5, off ; encoding: [0x00,0x80,0x0c,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_sub v[3:4], v5, off ; encoding: [0x00,0x80,0x0c,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_smin v[3:4], v5, off global_atomic_smin v[3:4], v5, off
// GFX10: encoding: [0x00,0x80,0xd4,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_smin v[3:4], v5, off ; encoding: [0x00,0x80,0x10,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_smin v[3:4], v5, off ; encoding: [0x00,0x80,0x10,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_umin v[3:4], v5, off global_atomic_umin v[3:4], v5, off
// GFX10: encoding: [0x00,0x80,0xd8,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_umin v[3:4], v5, off ; encoding: [0x00,0x80,0x14,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_umin v[3:4], v5, off ; encoding: [0x00,0x80,0x14,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_smax v[3:4], v5, off global_atomic_smax v[3:4], v5, off
// GFX10: encoding: [0x00,0x80,0xdc,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_smax v[3:4], v5, off ; encoding: [0x00,0x80,0x18,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_smax v[3:4], v5, off ; encoding: [0x00,0x80,0x18,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_umax v[3:4], v5, off global_atomic_umax v[3:4], v5, off
// GFX10: encoding: [0x00,0x80,0xe0,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_umax v[3:4], v5, off ; encoding: [0x00,0x80,0x1c,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_umax v[3:4], v5, off ; encoding: [0x00,0x80,0x1c,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_and v[3:4], v5, off global_atomic_and v[3:4], v5, off
// GFX10: encoding: [0x00,0x80,0xe4,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_and v[3:4], v5, off ; encoding: [0x00,0x80,0x20,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_and v[3:4], v5, off ; encoding: [0x00,0x80,0x20,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_or v[3:4], v5, off global_atomic_or v[3:4], v5, off
// GFX10: encoding: [0x00,0x80,0xe8,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_or v[3:4], v5, off ; encoding: [0x00,0x80,0x24,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_or v[3:4], v5, off ; encoding: [0x00,0x80,0x24,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_xor v[3:4], v5, off global_atomic_xor v[3:4], v5, off
// GFX10: encoding: [0x00,0x80,0xec,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_xor v[3:4], v5, off ; encoding: [0x00,0x80,0x28,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_xor v[3:4], v5, off ; encoding: [0x00,0x80,0x28,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_inc v[3:4], v5, off global_atomic_inc v[3:4], v5, off
// GFX10: encoding: [0x00,0x80,0xf0,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_inc v[3:4], v5, off ; encoding: [0x00,0x80,0x2c,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_inc v[3:4], v5, off ; encoding: [0x00,0x80,0x2c,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_dec v[3:4], v5, off global_atomic_dec v[3:4], v5, off
// GFX10: encoding: [0x00,0x80,0xf4,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_dec v[3:4], v5, off ; encoding: [0x00,0x80,0x30,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_dec v[3:4], v5, off ; encoding: [0x00,0x80,0x30,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_add_x2 v[3:4], v[5:6], off global_atomic_add_x2 v[3:4], v[5:6], off
// GFX10: encoding: [0x00,0x80,0x48,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_add_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x88,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_add_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x88,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_sub_x2 v[3:4], v[5:6], off global_atomic_sub_x2 v[3:4], v[5:6], off
// GFX10: encoding: [0x00,0x80,0x4c,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_sub_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x8c,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_sub_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x8c,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_smin_x2 v[3:4], v[5:6], off global_atomic_smin_x2 v[3:4], v[5:6], off
// GFX10: encoding: [0x00,0x80,0x54,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_smin_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x90,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_smin_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x90,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_umin_x2 v[3:4], v[5:6], off global_atomic_umin_x2 v[3:4], v[5:6], off
// GFX10: encoding: [0x00,0x80,0x58,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_umin_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x94,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_umin_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x94,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_smax_x2 v[3:4], v[5:6], off global_atomic_smax_x2 v[3:4], v[5:6], off
// GFX10: encoding: [0x00,0x80,0x5c,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_smax_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x98,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_smax_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x98,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_umax_x2 v[3:4], v[5:6], off global_atomic_umax_x2 v[3:4], v[5:6], off
// GFX10: encoding: [0x00,0x80,0x60,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_umax_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x9c,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_umax_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0x9c,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_and_x2 v[3:4], v[5:6], off global_atomic_and_x2 v[3:4], v[5:6], off
// GFX10: encoding: [0x00,0x80,0x64,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_and_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xa0,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_and_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xa0,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_or_x2 v[3:4], v[5:6], off global_atomic_or_x2 v[3:4], v[5:6], off
// GFX10: encoding: [0x00,0x80,0x68,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_or_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xa4,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_or_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xa4,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_xor_x2 v[3:4], v[5:6], off global_atomic_xor_x2 v[3:4], v[5:6], off
// GFX10: encoding: [0x00,0x80,0x6c,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_xor_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xa8,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_xor_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xa8,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_inc_x2 v[3:4], v[5:6], off global_atomic_inc_x2 v[3:4], v[5:6], off
// GFX10: encoding: [0x00,0x80,0x70,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_inc_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xac,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_inc_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xac,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_atomic_dec_x2 v[3:4], v[5:6], off global_atomic_dec_x2 v[3:4], v[5:6], off
// GFX10: encoding: [0x00,0x80,0x74,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_dec_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xb0,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_dec_x2 v[3:4], v[5:6], off ; encoding: [0x00,0x80,0xb0,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: error: instruction not supported on this GPU // VI-ERR: error: instruction not supported on this GPU
global_atomic_cmpswap v[3:4], v[5:6], off offset:-16 global_atomic_cmpswap v[3:4], v[5:6], off offset:-16
// GFX10: encoding: [0xf0,0x8f,0xc4,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_cmpswap v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x04,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_cmpswap v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x04,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :49: error: not a valid operand. // VI-ERR: :49: error: not a valid operand.
global_atomic_cmpswap_x2 v[3:4], v[5:8], off offset:-16 global_atomic_cmpswap_x2 v[3:4], v[5:8], off offset:-16
// GFX10: encoding: [0xf0,0x8f,0x44,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_cmpswap_x2 v[3:4], v[5:8], off offset:-16 ; encoding: [0xf0,0x9f,0x84,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_cmpswap_x2 v[3:4], v[5:8], off offset:-16 ; encoding: [0xf0,0x9f,0x84,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :52: error: not a valid operand. // VI-ERR: :52: error: not a valid operand.
global_atomic_swap v[3:4], v5, off offset:-16 global_atomic_swap v[3:4], v5, off offset:-16
// GFX10: encoding: [0xf0,0x8f,0xc0,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_swap v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x00,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_swap v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x00,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :42: error: not a valid operand // VI-ERR: :42: error: not a valid operand
global_atomic_swap_x2 v[3:4], v[5:6], off offset:-16 global_atomic_swap_x2 v[3:4], v[5:6], off offset:-16
// GFX10: encoding: [0xf0,0x8f,0x40,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_swap_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x80,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_swap_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x80,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :49: error: not a valid operand // VI-ERR: :49: error: not a valid operand
global_atomic_add v[3:4], v5, off offset:-16 global_atomic_add v[3:4], v5, off offset:-16
// GFX10: encoding: [0xf0,0x8f,0xc8,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_add v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x08,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_add v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x08,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :41: error: not a valid operand // VI-ERR: :41: error: not a valid operand
global_atomic_sub v[3:4], v5, off offset:-16 global_atomic_sub v[3:4], v5, off offset:-16
// GFX10: encoding: [0xf0,0x8f,0xcc,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_sub v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x0c,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_sub v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x0c,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :41: error: not a valid operand // VI-ERR: :41: error: not a valid operand
global_atomic_smin v[3:4], v5, off offset:-16 global_atomic_smin v[3:4], v5, off offset:-16
// GFX10: encoding: [0xf0,0x8f,0xd4,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_smin v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x10,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_smin v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x10,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :42: error: not a valid operand // VI-ERR: :42: error: not a valid operand
global_atomic_umin v[3:4], v5, off offset:-16 global_atomic_umin v[3:4], v5, off offset:-16
// GFX10: encoding: [0xf0,0x8f,0xd8,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_umin v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x14,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_umin v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x14,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :42: error: not a valid operand // VI-ERR: :42: error: not a valid operand
global_atomic_smax v[3:4], v5, off offset:-16 global_atomic_smax v[3:4], v5, off offset:-16
// GFX10: encoding: [0xf0,0x8f,0xdc,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_smax v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x18,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_smax v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x18,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :42: error: not a valid operand // VI-ERR: :42: error: not a valid operand
global_atomic_umax v[3:4], v5, off offset:-16 global_atomic_umax v[3:4], v5, off offset:-16
// GFX10: encoding: [0xf0,0x8f,0xe0,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_umax v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x1c,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_umax v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x1c,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :42: error: not a valid operand // VI-ERR: :42: error: not a valid operand
global_atomic_and v[3:4], v5, off offset:-16 global_atomic_and v[3:4], v5, off offset:-16
// GFX10: encoding: [0xf0,0x8f,0xe4,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_and v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x20,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_and v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x20,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :41: error: not a valid operand // VI-ERR: :41: error: not a valid operand
global_atomic_or v[3:4], v5, off offset:-16 global_atomic_or v[3:4], v5, off offset:-16
// GFX10: encoding: [0xf0,0x8f,0xe8,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_or v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x24,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_or v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x24,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :40: error: not a valid operand // VI-ERR: :40: error: not a valid operand
global_atomic_xor v[3:4], v5, off offset:-16 global_atomic_xor v[3:4], v5, off offset:-16
// GFX10: encoding: [0xf0,0x8f,0xec,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_xor v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x28,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_xor v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x28,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :41: error: not a valid operand // VI-ERR: :41: error: not a valid operand
global_atomic_inc v[3:4], v5, off offset:-16 global_atomic_inc v[3:4], v5, off offset:-16
// GFX10: encoding: [0xf0,0x8f,0xf0,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_inc v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x2c,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_inc v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x2c,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :41: error: not a valid operand // VI-ERR: :41: error: not a valid operand
global_atomic_dec v[3:4], v5, off offset:-16 global_atomic_dec v[3:4], v5, off offset:-16
// GFX10: encoding: [0xf0,0x8f,0xf4,0xdc,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_dec v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x30,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_dec v[3:4], v5, off offset:-16 ; encoding: [0xf0,0x9f,0x30,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :41: error: not a valid operand // VI-ERR: :41: error: not a valid operand
global_atomic_add_x2 v[3:4], v[5:6], off offset:-16 global_atomic_add_x2 v[3:4], v[5:6], off offset:-16
// GFX10: encoding: [0xf0,0x8f,0x48,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_add_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x88,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_add_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x88,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :48: error: not a valid operand // VI-ERR: :48: error: not a valid operand
global_atomic_sub_x2 v[3:4], v[5:6], off offset:-16 global_atomic_sub_x2 v[3:4], v[5:6], off offset:-16
// GFX10: encoding: [0xf0,0x8f,0x4c,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_sub_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x8c,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_sub_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x8c,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :48: error: not a valid operand // VI-ERR: :48: error: not a valid operand
global_atomic_smin_x2 v[3:4], v[5:6], off offset:-16 global_atomic_smin_x2 v[3:4], v[5:6], off offset:-16
// GFX10: encoding: [0xf0,0x8f,0x54,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_smin_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x90,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_smin_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x90,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :49: error: not a valid operand // VI-ERR: :49: error: not a valid operand
global_atomic_umin_x2 v[3:4], v[5:6], off offset:-16 global_atomic_umin_x2 v[3:4], v[5:6], off offset:-16
// GFX10: encoding: [0xf0,0x8f,0x58,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_umin_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x94,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_umin_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x94,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :49: error: not a valid operand // VI-ERR: :49: error: not a valid operand
global_atomic_smax_x2 v[3:4], v[5:6], off offset:-16 global_atomic_smax_x2 v[3:4], v[5:6], off offset:-16
// GFX10: encoding: [0xf0,0x8f,0x5c,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_smax_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x98,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_smax_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x98,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :49: error: not a valid operand // VI-ERR: :49: error: not a valid operand
global_atomic_umax_x2 v[3:4], v[5:6], off offset:-16 global_atomic_umax_x2 v[3:4], v[5:6], off offset:-16
// GFX10: encoding: [0xf0,0x8f,0x60,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_umax_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x9c,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_umax_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0x9c,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :49: error: not a valid operand // VI-ERR: :49: error: not a valid operand
global_atomic_and_x2 v[3:4], v[5:6], off offset:-16 global_atomic_and_x2 v[3:4], v[5:6], off offset:-16
// GFX10: encoding: [0xf0,0x8f,0x64,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_and_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xa0,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_and_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xa0,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :48: error: not a valid operand // VI-ERR: :48: error: not a valid operand
global_atomic_or_x2 v[3:4], v[5:6], off offset:-16 global_atomic_or_x2 v[3:4], v[5:6], off offset:-16
// GFX10: encoding: [0xf0,0x8f,0x68,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_or_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xa4,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_or_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xa4,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :47: error: not a valid operand // VI-ERR: :47: error: not a valid operand
global_atomic_xor_x2 v[3:4], v[5:6], off offset:-16 global_atomic_xor_x2 v[3:4], v[5:6], off offset:-16
// GFX10: encoding: [0xf0,0x8f,0x6c,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_xor_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xa8,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_xor_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xa8,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :48: error: not a valid operand // VI-ERR: :48: error: not a valid operand
global_atomic_inc_x2 v[3:4], v[5:6], off offset:-16 global_atomic_inc_x2 v[3:4], v[5:6], off offset:-16
// GFX10: encoding: [0xf0,0x8f,0x70,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_inc_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xac,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_inc_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xac,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :48: error: not a valid operand // VI-ERR: :48: error: not a valid operand
global_atomic_dec_x2 v[3:4], v[5:6], off offset:-16 global_atomic_dec_x2 v[3:4], v[5:6], off offset:-16
// GFX10: encoding: [0xf0,0x8f,0x74,0xdd,0x03,0x05,0x7d,0x00]
// GFX9: global_atomic_dec_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xb0,0xdd,0x03,0x05,0x7f,0x00] // GFX9: global_atomic_dec_x2 v[3:4], v[5:6], off offset:-16 ; encoding: [0xf0,0x9f,0xb0,0xdd,0x03,0x05,0x7f,0x00]
// VI-ERR: :48: error: not a valid operand // VI-ERR: :48: error: not a valid operand
global_load_ubyte_d16 v1, v[3:4], off global_load_ubyte_d16 v1, v[3:4], off
// GFX10: encoding: [0x00,0x80,0x80,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_ubyte_d16 v1, v[3:4], off ; encoding: [0x00,0x80,0x80,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_ubyte_d16 v1, v[3:4], off ; encoding: [0x00,0x80,0x80,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_ubyte_d16_hi v1, v[3:4], off global_load_ubyte_d16_hi v1, v[3:4], off
// GFX10: encoding: [0x00,0x80,0x84,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_ubyte_d16_hi v1, v[3:4], off ; encoding: [0x00,0x80,0x84,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_ubyte_d16_hi v1, v[3:4], off ; encoding: [0x00,0x80,0x84,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_sbyte_d16 v1, v[3:4], off global_load_sbyte_d16 v1, v[3:4], off
// GFX10: encoding: [0x00,0x80,0x88,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_sbyte_d16 v1, v[3:4], off ; encoding: [0x00,0x80,0x88,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_sbyte_d16 v1, v[3:4], off ; encoding: [0x00,0x80,0x88,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_sbyte_d16_hi v1, v[3:4], off global_load_sbyte_d16_hi v1, v[3:4], off
// GFX10: encoding: [0x00,0x80,0x8c,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_sbyte_d16_hi v1, v[3:4], off ; encoding: [0x00,0x80,0x8c,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_sbyte_d16_hi v1, v[3:4], off ; encoding: [0x00,0x80,0x8c,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_short_d16 v1, v[3:4], off global_load_short_d16 v1, v[3:4], off
// GFX10: encoding: [0x00,0x80,0x90,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_short_d16 v1, v[3:4], off ; encoding: [0x00,0x80,0x90,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_short_d16 v1, v[3:4], off ; encoding: [0x00,0x80,0x90,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_load_short_d16_hi v1, v[3:4], off global_load_short_d16_hi v1, v[3:4], off
// GFX10: encoding: [0x00,0x80,0x94,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: global_load_short_d16_hi v1, v[3:4], off ; encoding: [0x00,0x80,0x94,0xdc,0x03,0x00,0x7f,0x01] // GFX9: global_load_short_d16_hi v1, v[3:4], off ; encoding: [0x00,0x80,0x94,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_store_byte_d16_hi v[3:4], v1, off global_store_byte_d16_hi v[3:4], v1, off
// GFX10: encoding: [0x00,0x80,0x64,0xdc,0x03,0x01,0x7d,0x00]
// GFX9: global_store_byte_d16_hi v[3:4], v1, off ; encoding: [0x00,0x80,0x64,0xdc,0x03,0x01,0x7f,0x00] // GFX9: global_store_byte_d16_hi v[3:4], v1, off ; encoding: [0x00,0x80,0x64,0xdc,0x03,0x01,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
global_store_short_d16_hi v[3:4], v1, off global_store_short_d16_hi v[3:4], v1, off
// GFX10: encoding: [0x00,0x80,0x6c,0xdc,0x03,0x01,0x7d,0x00]
// GFX9: global_store_short_d16_hi v[3:4], v1, off ; encoding: [0x00,0x80,0x6c,0xdc,0x03,0x01,0x7f,0x00] // GFX9: global_store_short_d16_hi v[3:4], v1, off ; encoding: [0x00,0x80,0x6c,0xdc,0x03,0x01,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU

llvm/trunk/test/MC/AMDGPU/flat-scratch-instructions.s

// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding 2>&1 %s | FileCheck -check-prefix=GFX9-ERR -check-prefix=GCNERR %s // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding 2>&1 %s | FileCheck -check-prefix=GFX9-ERR -check-prefix=GCNERR %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding 2>&1 %s | FileCheck -check-prefix=VI-ERR -check-prefix=GCNERR %s // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding 2>&1 %s | FileCheck -check-prefix=VI-ERR -check-prefix=GCNERR %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W32-ERR %s
scratch_load_ubyte v1, v2, off scratch_load_ubyte v1, v2, off
// GFX10: encoding: [0x00,0x40,0x20,0xdc,0x02,0x00,0x7d,0x01]
// GFX9: scratch_load_ubyte v1, v2, off ; encoding: [0x00,0x40,0x40,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_ubyte v1, v2, off ; encoding: [0x00,0x40,0x40,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_ubyte v1, v2, off dlc
// GFX10: encoding: [0x00,0x50,0x20,0xdc,0x02,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
scratch_load_sbyte v1, v2, off scratch_load_sbyte v1, v2, off
// GFX10: encoding: [0x00,0x40,0x24,0xdc,0x02,0x00,0x7d,0x01]
// GFX9: scratch_load_sbyte v1, v2, off ; encoding: [0x00,0x40,0x44,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_sbyte v1, v2, off ; encoding: [0x00,0x40,0x44,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_sbyte v1, v2, off dlc
// GFX10: encoding: [0x00,0x50,0x24,0xdc,0x02,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
scratch_load_ushort v1, v2, off scratch_load_ushort v1, v2, off
// GFX10: encoding: [0x00,0x40,0x28,0xdc,0x02,0x00,0x7d,0x01]
// GFX9: scratch_load_ushort v1, v2, off ; encoding: [0x00,0x40,0x48,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_ushort v1, v2, off ; encoding: [0x00,0x40,0x48,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_ushort v1, v2, off dlc
// GFX10: encoding: [0x00,0x50,0x28,0xdc,0x02,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
scratch_load_sshort v1, v2, off scratch_load_sshort v1, v2, off
// GFX10: encoding: [0x00,0x40,0x2c,0xdc,0x02,0x00,0x7d,0x01]
// GFX9: scratch_load_sshort v1, v2, off ; encoding: [0x00,0x40,0x4c,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_sshort v1, v2, off ; encoding: [0x00,0x40,0x4c,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_sshort v1, v2, off dlc
// GFX10: encoding: [0x00,0x50,0x2c,0xdc,0x02,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
scratch_load_dword v1, v2, off scratch_load_dword v1, v2, off
// GFX10: encoding: [0x00,0x40,0x30,0xdc,0x02,0x00,0x7d,0x01]
// GFX9: scratch_load_dword v1, v2, off ; encoding: [0x00,0x40,0x50,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_dword v1, v2, off ; encoding: [0x00,0x40,0x50,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_dword v1, v2, off dlc
// GFX10: encoding: [0x00,0x50,0x30,0xdc,0x02,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
scratch_load_dwordx2 v[1:2], v3, off scratch_load_dwordx2 v[1:2], v3, off
// GFX10: encoding: [0x00,0x40,0x34,0xdc,0x03,0x00,0x7d,0x01]
// GFX9: scratch_load_dwordx2 v[1:2], v3, off ; encoding: [0x00,0x40,0x54,0xdc,0x03,0x00,0x7f,0x01] // GFX9: scratch_load_dwordx2 v[1:2], v3, off ; encoding: [0x00,0x40,0x54,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_dwordx2 v[1:2], v3, off dlc
// GFX10: encoding: [0x00,0x50,0x34,0xdc,0x03,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
scratch_load_dwordx3 v[1:3], v4, off scratch_load_dwordx3 v[1:3], v4, off
// GFX10: encoding: [0x00,0x40,0x3c,0xdc,0x04,0x00,0x7d,0x01]
// GFX9: scratch_load_dwordx3 v[1:3], v4, off ; encoding: [0x00,0x40,0x58,0xdc,0x04,0x00,0x7f,0x01] // GFX9: scratch_load_dwordx3 v[1:3], v4, off ; encoding: [0x00,0x40,0x58,0xdc,0x04,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_dwordx3 v[1:3], v4, off dlc
// GFX10: encoding: [0x00,0x50,0x3c,0xdc,0x04,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
scratch_load_dwordx4 v[1:4], v5, off scratch_load_dwordx4 v[1:4], v5, off
// GFX10: encoding: [0x00,0x40,0x38,0xdc,0x05,0x00,0x7d,0x01]
// GFX9: scratch_load_dwordx4 v[1:4], v5, off ; encoding: [0x00,0x40,0x5c,0xdc,0x05,0x00,0x7f,0x01] // GFX9: scratch_load_dwordx4 v[1:4], v5, off ; encoding: [0x00,0x40,0x5c,0xdc,0x05,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
// FIXME: VI error should be instruction nto supported
scratch_load_dwordx4 v[1:4], v5, off dlc
// GFX10: encoding: [0x00,0x50,0x38,0xdc,0x05,0x00,0x7d,0x01]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
scratch_load_dword v1, v2, off offset:0 scratch_load_dword v1, v2, off offset:0
// GFX10: encoding: [0x00,0x40,0x30,0xdc,0x02,0x00,0x7d,0x01]
// GFX9: scratch_load_dword v1, v2, off ; encoding: [0x00,0x40,0x50,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_dword v1, v2, off ; encoding: [0x00,0x40,0x50,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: error: not a valid operand. // VI-ERR: error: not a valid operand.
scratch_load_dword v1, v2, off offset:4095 scratch_load_dword v1, v2, off offset:4095
// GFX10-ERR: error: invalid operand for instruction
// GFX9: scratch_load_dword v1, v2, off offset:4095 ; encoding: [0xff,0x4f,0x50,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_dword v1, v2, off offset:4095 ; encoding: [0xff,0x4f,0x50,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: error: not a valid operand. // VI-ERR: error: not a valid operand.
scratch_load_dword v1, v2, off offset:-1 scratch_load_dword v1, v2, off offset:-1
// GFX10: encoding: [0xff,0x4f,0x30,0xdc,0x02,0x00,0x7d,0x01]
// GFX9: scratch_load_dword v1, v2, off offset:-1 ; encoding: [0xff,0x5f,0x50,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_dword v1, v2, off offset:-1 ; encoding: [0xff,0x5f,0x50,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: error: not a valid operand. // VI-ERR: error: not a valid operand.
scratch_load_dword v1, v2, off offset:-4096 scratch_load_dword v1, v2, off offset:-4096
// GFX10-ERR: error: invalid operand for instruction
// GFX9: scratch_load_dword v1, v2, off offset:-4096 ; encoding: [0x00,0x50,0x50,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_dword v1, v2, off offset:-4096 ; encoding: [0x00,0x50,0x50,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: error: not a valid operand. // VI-ERR: error: not a valid operand.
scratch_load_dword v1, v2, off offset:4096 scratch_load_dword v1, v2, off offset:4096
// GFX10-ERR: error: invalid operand for instruction
// GFX9-ERR: error: invalid operand for instruction // GFX9-ERR: error: invalid operand for instruction
// VI-ERR: error: not a valid operand. // VI-ERR: error: not a valid operand.
scratch_load_dword v1, v2, off offset:-4097 scratch_load_dword v1, v2, off offset:-4097
// GFX10-ERR: error: invalid operand for instruction
// GFX9-ERR: error: invalid operand for instruction // GFX9-ERR: error: invalid operand for instruction
// VI-ERR: error: not a valid operand. // VI-ERR: error: not a valid operand.
scratch_store_byte v1, v2, off scratch_store_byte v1, v2, off
// GFX10: encoding: [0x00,0x40,0x60,0xdc,0x01,0x02,0x7d,0x00]
// GFX9: scratch_store_byte v1, v2, off ; encoding: [0x00,0x40,0x60,0xdc,0x01,0x02,0x7f,0x00] // GFX9: scratch_store_byte v1, v2, off ; encoding: [0x00,0x40,0x60,0xdc,0x01,0x02,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_store_byte v1, v2, off dlc
// GFX10: encoding: [0x00,0x50,0x60,0xdc,0x01,0x02,0x7d,0x00]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
scratch_store_short v1, v2, off scratch_store_short v1, v2, off
// GFX10: encoding: [0x00,0x40,0x68,0xdc,0x01,0x02,0x7d,0x00]
// GFX9: scratch_store_short v1, v2, off ; encoding: [0x00,0x40,0x68,0xdc,0x01,0x02,0x7f,0x00] // GFX9: scratch_store_short v1, v2, off ; encoding: [0x00,0x40,0x68,0xdc,0x01,0x02,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_store_short v1, v2, off dlc
// GFX10: encoding: [0x00,0x50,0x68,0xdc,0x01,0x02,0x7d,0x00]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
scratch_store_dword v1, v2, off scratch_store_dword v1, v2, off
// GFX10: encoding: [0x00,0x40,0x70,0xdc,0x01,0x02,0x7d,0x00]
// GFX9: scratch_store_dword v1, v2, off ; encoding: [0x00,0x40,0x70,0xdc,0x01,0x02,0x7f,0x00] // GFX9: scratch_store_dword v1, v2, off ; encoding: [0x00,0x40,0x70,0xdc,0x01,0x02,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_store_dword v1, v2, off dlc
// GFX10: encoding: [0x00,0x50,0x70,0xdc,0x01,0x02,0x7d,0x00]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
scratch_store_dwordx2 v1, v[2:3], off scratch_store_dwordx2 v1, v[2:3], off
// GFX10: encoding: [0x00,0x40,0x74,0xdc,0x01,0x02,0x7d,0x00]
// GFX9: scratch_store_dwordx2 v1, v[2:3], off ; encoding: [0x00,0x40,0x74,0xdc,0x01,0x02,0x7f,0x00] // GFX9: scratch_store_dwordx2 v1, v[2:3], off ; encoding: [0x00,0x40,0x74,0xdc,0x01,0x02,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_store_dwordx2 v1, v[2:3], off dlc
// GFX10: encoding: [0x00,0x50,0x74,0xdc,0x01,0x02,0x7d,0x00]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
scratch_store_dwordx3 v1, v[2:4], off scratch_store_dwordx3 v1, v[2:4], off
// GFX10: encoding: [0x00,0x40,0x7c,0xdc,0x01,0x02,0x7d,0x00]
// GFX9: scratch_store_dwordx3 v1, v[2:4], off ; encoding: [0x00,0x40,0x78,0xdc,0x01,0x02,0x7f,0x00] // GFX9: scratch_store_dwordx3 v1, v[2:4], off ; encoding: [0x00,0x40,0x78,0xdc,0x01,0x02,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_store_dwordx3 v1, v[2:4], off dlc
// GFX10: encoding: [0x00,0x50,0x7c,0xdc,0x01,0x02,0x7d,0x00]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
scratch_store_dwordx4 v1, v[2:5], off scratch_store_dwordx4 v1, v[2:5], off
// GFX10: encoding: [0x00,0x40,0x78,0xdc,0x01,0x02,0x7d,0x00]
// GFX9: scratch_store_dwordx4 v1, v[2:5], off ; encoding: [0x00,0x40,0x7c,0xdc,0x01,0x02,0x7f,0x00] // GFX9: scratch_store_dwordx4 v1, v[2:5], off ; encoding: [0x00,0x40,0x7c,0xdc,0x01,0x02,0x7f,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_store_dwordx4 v1, v[2:5], off dlc
// GFX10: encoding: [0x00,0x50,0x78,0xdc,0x01,0x02,0x7d,0x00]
// GFX9-ERR: error: failed parsing operand
// VI-ERR: error: invalid operand for instruction
scratch_store_dword v1, v2, off offset:12 scratch_store_dword v1, v2, off offset:12
// GFX10: encoding: [0x0c,0x40,0x70,0xdc,0x01,0x02,0x7d,0x00]
// GFX9: scratch_store_dword v1, v2, off offset:12 ; encoding: [0x0c,0x40,0x70,0xdc,0x01,0x02,0x7f,0x00] // GFX9: scratch_store_dword v1, v2, off offset:12 ; encoding: [0x0c,0x40,0x70,0xdc,0x01,0x02,0x7f,0x00]
// VI-ERR: error: not a valid operand // VI-ERR: error: not a valid operand
scratch_load_dword v1, off, s1 scratch_load_dword v1, off, s1
// GFX10: encoding: [0x00,0x40,0x30,0xdc,0x00,0x00,0x01,0x01]
// GFX9: scratch_load_dword v1, off, s1 ; encoding: [0x00,0x40,0x50,0xdc,0x00,0x00,0x01,0x01] // GFX9: scratch_load_dword v1, off, s1 ; encoding: [0x00,0x40,0x50,0xdc,0x00,0x00,0x01,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_dword v1, off, s1 offset:32 scratch_load_dword v1, off, s1 offset:32
// GFX10: encoding: [0x20,0x40,0x30,0xdc,0x00,0x00,0x01,0x01]
// GFX9: scratch_load_dword v1, off, s1 offset:32 ; encoding: [0x20,0x40,0x50,0xdc,0x00,0x00,0x01,0x01] // GFX9: scratch_load_dword v1, off, s1 offset:32 ; encoding: [0x20,0x40,0x50,0xdc,0x00,0x00,0x01,0x01]
// VI-ERR: error: not a valid operand // VI-ERR: error: not a valid operand
scratch_store_dword off, v2, s1 scratch_store_dword off, v2, s1
// GFX10: encoding: [0x00,0x40,0x70,0xdc,0x00,0x02,0x01,0x00]
// GFX9: scratch_store_dword off, v2, s1 ; encoding: [0x00,0x40,0x70,0xdc,0x00,0x02,0x01,0x00] // GFX9: scratch_store_dword off, v2, s1 ; encoding: [0x00,0x40,0x70,0xdc,0x00,0x02,0x01,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_store_dword off, v2, s1 offset:12 scratch_store_dword off, v2, s1 offset:12
// GFX10: encoding: [0x0c,0x40,0x70,0xdc,0x00,0x02,0x01,0x00]
// GFX9: scratch_store_dword off, v2, s1 offset:12 ; encoding: [0x0c,0x40,0x70,0xdc,0x00,0x02,0x01,0x00] // GFX9: scratch_store_dword off, v2, s1 offset:12 ; encoding: [0x0c,0x40,0x70,0xdc,0x00,0x02,0x01,0x00]
// VI-ERR: error: not a valid operand // VI-ERR: error: not a valid operand
// FIXME: Should error about multiple offsets // FIXME: Should error about multiple offsets
scratch_load_dword v1, v2, s1 scratch_load_dword v1, v2, s1
// GFX10-ERR: error: invalid operand for instruction
// GFX9-ERR: error: invalid operand for instruction // GFX9-ERR: error: invalid operand for instruction
// VI-ERR: error: invalid operand for instruction // VI-ERR: error: invalid operand for instruction
scratch_load_dword v1, v2, s1 offset:32 scratch_load_dword v1, v2, s1 offset:32
// GFX10-ERR: error: invalid operand for instruction
// GFX9-ERR: error: invalid operand for instruction // GFX9-ERR: error: invalid operand for instruction
// VI-ERR: error: not a valid operand // VI-ERR: error: not a valid operand
scratch_store_dword v1, v2, s1 scratch_store_dword v1, v2, s1
// GFX10-ERR: error: invalid operand for instruction
// GFX9-ERR: error: invalid operand for instruction // GFX9-ERR: error: invalid operand for instruction
// VI-ERR: error: invalid operand for instruction // VI-ERR: error: invalid operand for instruction
scratch_store_dword v1, v2, s1 offset:32 scratch_store_dword v1, v2, s1 offset:32
// GFX10-ERR: error: invalid operand for instruction
// GFX9-ERR: error: invalid operand for instruction // GFX9-ERR: error: invalid operand for instruction
// VI-ERR: error: not a valid operand // VI-ERR: error: not a valid operand
scratch_load_dword v1, off, exec_hi scratch_load_dword v1, off, exec_hi
// GFX10-ERR: error: invalid operand for instruction
// GFX9-ERR: error: invalid operand for instruction // GFX9-ERR: error: invalid operand for instruction
// VI-ERR: error: invalid operand for instruction // VI-ERR: error: invalid operand for instruction
scratch_store_dword off, v2, exec_hi scratch_store_dword off, v2, exec_hi
// GFX10-ERR: error: invalid operand for instruction
// GFX9-ERR: error: invalid operand for instruction // GFX9-ERR: error: invalid operand for instruction
// VI-ERR: error: invalid operand for instruction // VI-ERR: error: invalid operand for instruction
scratch_load_dword v1, off, exec_lo scratch_load_dword v1, off, exec_lo
// GFX10: encoding: [0x00,0x40,0x30,0xdc,0x00,0x00,0x7e,0x01]
// GFX9: scratch_load_dword v1, off, exec_lo ; encoding: [0x00,0x40,0x50,0xdc,0x00,0x00,0x7e,0x01] // GFX9: scratch_load_dword v1, off, exec_lo ; encoding: [0x00,0x40,0x50,0xdc,0x00,0x00,0x7e,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_store_dword off, v2, exec_lo scratch_store_dword off, v2, exec_lo
// GFX10: encoding: [0x00,0x40,0x70,0xdc,0x00,0x02,0x7e,0x00]
// GFX9: scratch_store_dword off, v2, exec_lo ; encoding: [0x00,0x40,0x70,0xdc,0x00,0x02,0x7e,0x00] // GFX9: scratch_store_dword off, v2, exec_lo ; encoding: [0x00,0x40,0x70,0xdc,0x00,0x02,0x7e,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_dword v1, off, m0 scratch_load_dword v1, off, m0
// GFX10: encoding: [0x00,0x40,0x30,0xdc,0x00,0x00,0x7c,0x01]
// GFX9: scratch_load_dword v1, off, m0 ; encoding: [0x00,0x40,0x50,0xdc,0x00,0x00,0x7c,0x01] // GFX9: scratch_load_dword v1, off, m0 ; encoding: [0x00,0x40,0x50,0xdc,0x00,0x00,0x7c,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_store_dword off, v2, m0 scratch_store_dword off, v2, m0
// GFX10: encoding: [0x00,0x40,0x70,0xdc,0x00,0x02,0x7c,0x00]
// GFX9: scratch_store_dword off, v2, m0 ; encoding: [0x00,0x40,0x70,0xdc,0x00,0x02,0x7c,0x00] // GFX9: scratch_store_dword off, v2, m0 ; encoding: [0x00,0x40,0x70,0xdc,0x00,0x02,0x7c,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_ubyte_d16 v1, v2, off scratch_load_ubyte_d16 v1, v2, off
// GFX10: encoding: [0x00,0x40,0x80,0xdc,0x02,0x00,0x7d,0x01]
// GFX9: scratch_load_ubyte_d16 v1, v2, off ; encoding: [0x00,0x40,0x80,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_ubyte_d16 v1, v2, off ; encoding: [0x00,0x40,0x80,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_ubyte_d16_hi v1, v2, off scratch_load_ubyte_d16_hi v1, v2, off
// GFX10: encoding: [0x00,0x40,0x84,0xdc,0x02,0x00,0x7d,0x01]
// GFX9: scratch_load_ubyte_d16_hi v1, v2, off ; encoding: [0x00,0x40,0x84,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_ubyte_d16_hi v1, v2, off ; encoding: [0x00,0x40,0x84,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_sbyte_d16 v1, v2, off scratch_load_sbyte_d16 v1, v2, off
// GFX10: encoding: [0x00,0x40,0x88,0xdc,0x02,0x00,0x7d,0x01]
// GFX9: scratch_load_sbyte_d16 v1, v2, off ; encoding: [0x00,0x40,0x88,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_sbyte_d16 v1, v2, off ; encoding: [0x00,0x40,0x88,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_sbyte_d16_hi v1, v2, off scratch_load_sbyte_d16_hi v1, v2, off
// GFX10: encoding: [0x00,0x40,0x8c,0xdc,0x02,0x00,0x7d,0x01]
// GFX9: scratch_load_sbyte_d16_hi v1, v2, off ; encoding: [0x00,0x40,0x8c,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_sbyte_d16_hi v1, v2, off ; encoding: [0x00,0x40,0x8c,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_short_d16 v1, v2, off scratch_load_short_d16 v1, v2, off
// GFX10: encoding: [0x00,0x40,0x90,0xdc,0x02,0x00,0x7d,0x01]
// GFX9: scratch_load_short_d16 v1, v2, off ; encoding: [0x00,0x40,0x90,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_short_d16 v1, v2, off ; encoding: [0x00,0x40,0x90,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_load_short_d16_hi v1, v2, off scratch_load_short_d16_hi v1, v2, off
// GFX10: encoding: [0x00,0x40,0x94,0xdc,0x02,0x00,0x7d,0x01]
// GFX9: scratch_load_short_d16_hi v1, v2, off ; encoding: [0x00,0x40,0x94,0xdc,0x02,0x00,0x7f,0x01] // GFX9: scratch_load_short_d16_hi v1, v2, off ; encoding: [0x00,0x40,0x94,0xdc,0x02,0x00,0x7f,0x01]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_store_byte_d16_hi off, v2, s1 scratch_store_byte_d16_hi off, v2, s1
// GFX10: encoding: [0x00,0x40,0x64,0xdc,0x00,0x02,0x01,0x00]
// GFX9: scratch_store_byte_d16_hi off, v2, s1 ; encoding: [0x00,0x40,0x64,0xdc,0x00,0x02,0x01,0x00] // GFX9: scratch_store_byte_d16_hi off, v2, s1 ; encoding: [0x00,0x40,0x64,0xdc,0x00,0x02,0x01,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU
scratch_store_short_d16_hi off, v2, s1 scratch_store_short_d16_hi off, v2, s1
// GFX10: encoding: [0x00,0x40,0x6c,0xdc,0x00,0x02,0x01,0x00]
// GFX9: scratch_store_short_d16_hi off, v2, s1 ; encoding: [0x00,0x40,0x6c,0xdc,0x00,0x02,0x01,0x00] // GFX9: scratch_store_short_d16_hi off, v2, s1 ; encoding: [0x00,0x40,0x6c,0xdc,0x00,0x02,0x01,0x00]
// VI-ERR: instruction not supported on this GPU // VI-ERR: instruction not supported on this GPU