[DAG] Refactor DAGCombiner::ReassociateOps

[bjope]

Summary

Extract the logic for doing reassociations
from DAGCombiner::reassociateOps into a helper
function DAGCombiner::reassociateOpsCommutative,
and use that helper to trigger reassociation
on the original operand order, or the commuted
operand order.

Codegen is not identical since the operand order will
be different when doing the reassociations for the
commuted case. That causes some unfortunate churn in
some test cases. Apart from that this should be NFC.

[bjope]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

1022 ↗

(On Diff #196872)

An alternative to avoid churn in test cases is to provide some bool indicating that we are handling the commuted scenario, and then swap the operand order here (and also on line 1028). I think that would result in the same operand ordering as in the past (but since the opcodes handled here are commutative it shouldn't matter for correctness).

[spatel]

I don't mind the test churn, but is there a motivating test that shows that we missed an optimization? If not (and this patch is virtually NFC), then let's include that in the description/commit message.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

461 ↗

(On Diff #196872)

ReassociateOpsCommutative -> reassociateOpsCommutative (lowerCamelCase)

Please fix the existing "ReassociateOps" as part of this patch or as a preliminary cleanup too. If we keep using the wrong formatting based on existing code, we'll never converge on the right formatting. :)

1005 ↗

(On Diff #196872)

Trying -> Try

1039–1041 ↗

(On Diff #196872)

I'm not sure if we have a utility function to enforce this, but it would be nice to assert that Opc is actually a commutative opcode.

[bjope]

Address review comments from @spatel (thanks!).

[spatel]

LGTM

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

private:
     SDValue visitFP16_TO_FP(SDNode *N);
     SDValue visitVECREDUCE(SDNode *N);
 
     SDValue visitFADDForFMACombine(SDNode *N);
     SDValue visitFSUBForFMACombine(SDNode *N);
     SDValue visitFMULForFMADistributiveCombine(SDNode *N);
 
     SDValue XformToShuffleWithZero(SDNode *N);
-    SDValue ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
+    SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0,
+                                      SDValue N1);
+    SDValue reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
                            SDValue N1, SDNodeFlags Flags);
 
     SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
 
     SDValue foldSelectOfConstants(SDNode *N);
     SDValue foldVSelectOfConstants(SDNode *N);
     SDValue foldBinOpIntoSelect(SDNode *BO);
     bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);

 // undef's.
 static bool isAnyConstantBuildVector(SDValue V, bool NoOpaques = false) {
   if (V.getOpcode() != ISD::BUILD_VECTOR)
     return false;
   return isConstantOrConstantVector(V, NoOpaques) ||
          ISD::isBuildVectorOfConstantFPSDNodes(V.getNode());
 }
 
-SDValue DAGCombiner::ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
-                                    SDValue N1, SDNodeFlags Flags) {
+// Helper for DAGCombiner::reassociateOps. Try to reassociate an expression
+// such as (Opc N0, N1), if \p N0 is the same kind of operation as \p Opc.
+SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL,
+                                               SDValue N0, SDValue N1) {
+  EVT VT = N0.getValueType();
+
+  if (N0.getOpcode() != Opc)
+    return SDValue();
+
   // Don't reassociate reductions.
-  if (Flags.hasVectorReduction())
+  if (N0->getFlags().hasVectorReduction())
     return SDValue();
 
-  EVT VT = N0.getValueType();
-  if (N0.getOpcode() == Opc && !N0->getFlags().hasVectorReduction()) {
-    if (SDNode *L = DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
-      if (SDNode *R = DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
-        // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
-        if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, L, R))
-          return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
-        return SDValue();
-      }
-      if (N0.hasOneUse()) {
-        // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one
-        // use
-        SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
-        if (!OpNode.getNode())
-          return SDValue();
-        AddToWorklist(OpNode.getNode());
-        return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
-      }
-    }
-  }
-
-  if (N1.getOpcode() == Opc && !N1->getFlags().hasVectorReduction()) {
-    if (SDNode *R = DAG.isConstantIntBuildVectorOrConstantInt(N1.getOperand(1))) {
-      if (SDNode *L = DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
-        // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
-        if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, R, L))
-          return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
-        return SDValue();
-      }
-      if (N1.hasOneUse()) {
-        // reassoc. (op x, (op y, c1)) -> (op (op x, y), c1) iff x+c1 has one
-        // use
-        SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0, N1.getOperand(0));
-        if (!OpNode.getNode())
-          return SDValue();
-        AddToWorklist(OpNode.getNode());
-        return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
-      }
-    }
-  }
+  if (SDNode *C1 = DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
+    if (SDNode *C2 = DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
+      // Reassociate: (op (op x, c1), c2) -> (op x, (op c1, c2))
+      if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, C1, C2))
+      // Reassociate: (op (op x, c1), y) -> (op (op x, y), c1)
+      //              iff (op x, c1) has one use
 
+// Try to reassociate commutative binops.
+SDValue DAGCombiner::reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
+                                    SDValue N1, SDNodeFlags Flags) {
+  assert(TLI.isCommutativeBinOp(Opc) && "Operation not commutative.");
+  // Don't reassociate reductions.
+  if (Flags.hasVectorReduction())
+    return SDValue();
+  if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N0, N1))
+    return Combined;
+  if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N1, N0))
+    return Combined;
   return SDValue();
 }
 
 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
                                bool AddTo) {
   assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
   ++NodesCombined;
   LLVM_DEBUG(dbgs() << "\nReplacing.1 "; N->dump(&DAG); dbgs() << "\nWith: ";
if (N0.getOpcode() == ISD::OR &&
       return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Add0);
     }
   }
 
   if (SDValue NewSel = foldBinOpIntoSelect(N))
     return NewSel;
 
   // reassociate add
-  if (SDValue RADD = ReassociateOps(ISD::ADD, DL, N0, N1, N->getFlags()))
+  if (SDValue RADD = reassociateOps(ISD::ADD, DL, N0, N1, N->getFlags()))
     return RADD;
 
   // fold ((0-A) + B) -> B-A
   if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0)))
     return DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
 
   // fold (A + (0-B)) -> A-B
   if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
if (DAG.isConstantIntBuildVectorOrConstantInt(N1) &&
       isMulAddWithConstProfitable(N, N0, N1))
       return DAG.getNode(ISD::ADD, SDLoc(N), VT,
                          DAG.getNode(ISD::MUL, SDLoc(N0), VT,
                                      N0.getOperand(0), N1),
                          DAG.getNode(ISD::MUL, SDLoc(N1), VT,
                                      N0.getOperand(1), N1));
 
   // reassociate mul
-  if (SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1, N->getFlags()))
+  if (SDValue RMUL = reassociateOps(ISD::MUL, SDLoc(N), N0, N1, N->getFlags()))
     return RMUL;
 
   return SDValue();
 }
 
 /// Return true if divmod libcall is available.
 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
                                      const TargetLowering &TLI) {
SDValue DAGCombiner::visitAND(SDNode *N) {
   if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
                                    APInt::getAllOnesValue(BitWidth)))
     return DAG.getConstant(0, SDLoc(N), VT);
 
   if (SDValue NewSel = foldBinOpIntoSelect(N))
     return NewSel;
 
   // reassociate and
-  if (SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1, N->getFlags()))
+  if (SDValue RAND = reassociateOps(ISD::AND, SDLoc(N), N0, N1, N->getFlags()))
     return RAND;
 
   // Try to convert a constant mask AND into a shuffle clear mask.
   if (VT.isVector())
     if (SDValue Shuffle = XformToShuffleWithZero(N))
       return Shuffle;
 
   // fold (and (or x, C), D) -> D if (C & D) == D
SDValue DAGCombiner::visitOR(SDNode *N) {
 
   // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
   if (SDValue BSwap = MatchBSwapHWord(N, N0, N1))
     return BSwap;
   if (SDValue BSwap = MatchBSwapHWordLow(N, N0, N1))
     return BSwap;
 
   // reassociate or
-  if (SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1, N->getFlags()))
+  if (SDValue ROR = reassociateOps(ISD::OR, SDLoc(N), N0, N1, N->getFlags()))
     return ROR;
 
   // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
   // iff (c1 & c2) != 0 or c1/c2 are undef.
   auto MatchIntersect = [](ConstantSDNode *C1, ConstantSDNode *C2) {
     return !C1 || !C2 || C1->getAPIntValue().intersects(C2->getAPIntValue());
   };
   if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
SDValue DAGCombiner::visitXOR(SDNode *N) {
   // fold (xor x, 0) -> x
   if (isNullConstant(N1))
     return N0;
 
   if (SDValue NewSel = foldBinOpIntoSelect(N))
     return NewSel;
 
   // reassociate xor
-  if (SDValue RXOR = ReassociateOps(ISD::XOR, DL, N0, N1, N->getFlags()))
+  if (SDValue RXOR = reassociateOps(ISD::XOR, DL, N0, N1, N->getFlags()))
     return RXOR;
 
   // fold !(x cc y) -> (x !cc y)
   unsigned N0Opcode = N0.getOpcode();
   SDValue LHS, RHS, CC;
   if (TLI.isConstTrueVal(N1.getNode()) && isSetCCEquivalent(N0, LHS, RHS, CC)) {
     ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
                                                LHS.getValueType().isInteger());

llvm/trunk/test/CodeGen/AArch64/arm64-addr-type-promotion.ll

 ; CHECK: sxtw [[I2:x[0-9]+]], w1
 ; CHECK-NEXT: ldr [[BLOCKBASE:x[0-9]+]], {{\[}}[[ADDR]]]
 ; CHECK-NEXT: ldrb [[BLOCKVAL1:w[0-9]+]], {{\[}}[[BLOCKBASE]], [[I1]]]
 ; CHECK-NEXT: ldrb [[BLOCKVAL2:w[0-9]+]], {{\[}}[[BLOCKBASE]], [[I2]]]
 
 ; CHECK-NEXT: cmp [[BLOCKVAL1]], [[BLOCKVAL2]]
 ; CHECK-NEXT: b.ne
 ; Next BB
-; CHECK: add [[BLOCKBASE2:x[0-9]+]], [[BLOCKBASE]], [[I2]]
-; CHECK-NEXT: add [[BLOCKBASE1:x[0-9]+]], [[BLOCKBASE]], [[I1]]
+; CHECK: add [[BLOCKBASE1:x[0-9]+]], [[I1]], [[BLOCKBASE]]
+; CHECK-NEXT: add [[BLOCKBASE2:x[0-9]+]], [[I2]], [[BLOCKBASE]]
 ; CHECK-NEXT: ldrb [[LOADEDVAL1:w[0-9]+]], {{\[}}[[BLOCKBASE1]], #1]
 ; CHECK-NEXT: ldrb [[LOADEDVAL2:w[0-9]+]], {{\[}}[[BLOCKBASE2]], #1]
 ; CHECK-NEXT: cmp [[LOADEDVAL1]], [[LOADEDVAL2]]
 ; CHECK-NEXT: b.ne
 ; Next BB
 ; CHECK: ldrb [[LOADEDVAL3:w[0-9]+]], {{\[}}[[BLOCKBASE1]], #2]
 ; CHECK-NEXT: ldrb [[LOADEDVAL4:w[0-9]+]], {{\[}}[[BLOCKBASE2]], #2]
 ; CHECK-NEXT: cmp [[LOADEDVAL3]], [[LOADEDVAL4]]

llvm/trunk/test/CodeGen/AMDGPU/calling-conventions.ll

define amdgpu_ps void @ps_mesa_v2i16(<2 x i16> %arg0) {
   store <2 x i16> %add, <2 x i16> addrspace(1)* undef
   ret void
 }
 
 ; GCN-LABEL: {{^}}ps_mesa_inreg_v2i16:
 ; VI: s_and_b32 s1, s0, 0xffff0000
 ; VI: s_add_i32 s0, s0, 1
 ; VI: s_and_b32 s0, s0, 0xffff
-; VI: s_or_b32 s0, s0, s1
+; VI: s_or_b32 s0, s1, s0
 ; VI: s_add_i32 s0, s0, 0x10000
 ; VI: v_mov_b32_e32 v0, s0
 
 ; SI: s_lshl_b32 s1, s1, 16
 ; SI: s_add_i32 s0, s0, 1
 ; SI: s_and_b32 s0, s0, 0xffff
-; SI: s_or_b32 s0, s0, s1
+; SI: s_or_b32 s0, s1, s0
 ; SI: s_add_i32 s0, s0, 0x10000
 define amdgpu_ps void @ps_mesa_inreg_v2i16(<2 x i16> inreg %arg0) {
   %add = add <2 x i16> %arg0, <i16 1, i16 1>
   store <2 x i16> %add, <2 x i16> addrspace(1)* undef
   ret void
 }
 
 ; GCN-LABEL: {{^}}ps_mesa_inreg_v3i32:

llvm/trunk/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll

 ; SI-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
 ; SI-NEXT:    v_add_i32_e32 v7, vcc, 9, v1
 ; SI-NEXT:    v_and_b32_e32 v6, 0xff00, v1
 ; SI-NEXT:    v_lshrrev_b32_e32 v5, 24, v1
 ; SI-NEXT:    v_cvt_f32_ubyte3_e32 v3, v1
 ; SI-NEXT:    v_cvt_f32_ubyte2_e32 v2, v1
 ; SI-NEXT:    v_cvt_f32_ubyte0_e32 v0, v1
 ; SI-NEXT:    v_cvt_f32_ubyte1_e32 v1, v6
-; SI-NEXT:    v_add_i32_e32 v4, vcc, 9, v4
 ; SI-NEXT:    v_and_b32_e32 v7, s12, v7
+; SI-NEXT:    v_add_i32_e32 v4, vcc, 9, v4
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
 ; SI-NEXT:    s_waitcnt expcnt(0)
-; SI-NEXT:    v_or_b32_e32 v1, v7, v6
+; SI-NEXT:    v_or_b32_e32 v0, v6, v7
 ; SI-NEXT:    v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT:    v_and_b32_e32 v0, s12, v4
-; SI-NEXT:    v_or_b32_e32 v0, v0, v5
-; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x900, v1
-; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT:    v_and_b32_e32 v1, s12, v4
+; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x900, v0
+; SI-NEXT:    v_or_b32_e32 v1, v5, v1
+; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
 ; SI-NEXT:    v_or_b32_e32 v0, v1, v0
 ; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x9000000, v0
 ; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: load_v4i8_to_v4f32_2_uses:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34

 ; VI-NEXT:    v_cvt_f32_ubyte2_e32 v2, v5
 ; VI-NEXT:    v_cvt_f32_ubyte1_e32 v1, v5
 ; VI-NEXT:    v_cvt_f32_ubyte0_e32 v0, v5
 ; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; VI-NEXT:    v_and_b32_e32 v8, 0xffffff00, v5
 ; VI-NEXT:    v_add_u16_e32 v9, 9, v5
 ; VI-NEXT:    v_add_u16_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v7
-; VI-NEXT:    v_or_b32_sdwa v0, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v0, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; VI-NEXT:    v_add_u16_e32 v0, s8, v0
 ; VI-NEXT:    v_add_u16_sdwa v1, v1, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v1
 ; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
   %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
   %in.ptr = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
   %load = load <4 x i8>, <4 x i8> addrspace(1)* %in.ptr, align 4

llvm/trunk/test/CodeGen/AMDGPU/shl_add_constant.ll

define amdgpu_kernel void @test_add_shl_add_constant(i32 addrspace(1)* %out, [8 x i32], i32 %x, i32 %y) #0 {
   %add.1 = add i32 %shl, %y
    store i32 %add.1, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; FUNC-LABEL: {{^}}test_add_shl_add_constant_inv:
 ; SI-DAG: s_load_dwordx2 s{{\[}}[[X:[0-9]+]]:[[Y:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x13
 ; SI: s_lshl_b32 [[SHL3:s[0-9]+]], s[[X]], 3
-; SI: s_add_i32 [[TMP:s[0-9]+]], s[[Y]], [[SHL3]]
+; SI: s_add_i32 [[TMP:s[0-9]+]], [[SHL3]], s[[Y]]
 ; SI: s_addk_i32 [[TMP]], 0x3d8
 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[TMP]]
 ; SI: buffer_store_dword [[VRESULT]]
 
 define amdgpu_kernel void @test_add_shl_add_constant_inv(i32 addrspace(1)* %out, [8 x i32], i32 %x, i32 %y) #0 {
   %add.0 = add i32 %x, 123
   %shl = shl i32 %add.0, 3
   %add.1 = add i32 %y, %shl
   store i32 %add.1, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone }

llvm/trunk/test/CodeGen/AMDGPU/widen-smrd-loads.ll

 ; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
 ; SI-NEXT:    s_load_dword s0, s[0:1], 0x0
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
 ; SI-NEXT:    s_and_b32 s1, s0, 0xff00
 ; SI-NEXT:    s_add_i32 s0, s0, 12
 ; SI-NEXT:    s_or_b32 s0, s0, 4
 ; SI-NEXT:    s_and_b32 s0, s0, 0xff
-; SI-NEXT:    s_or_b32 s0, s0, s1
+; SI-NEXT:    s_or_b32 s0, s1, s0
 ; SI-NEXT:    s_addk_i32 s0, 0x2c00
 ; SI-NEXT:    s_or_b32 s0, s0, 0x300
 ; SI-NEXT:    v_mov_b32_e32 v0, s0
 ; SI-NEXT:    buffer_store_short v0, off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: widen_v2i8_constant_load:
 ; VI:       ; %bb.0:

llvm/trunk/test/CodeGen/ARM/and-load-combine.ll

entry:
   %2 = and i16 %and3, %1
   %cmp = icmp eq i16 %2, 0
   ret i1 %cmp
 }
 
 define arm_aapcscc zeroext i1 @cmp_and8_short_int(i16* nocapture readonly %a, i32* nocapture readonly %b) {
 ; ARM-LABEL: cmp_and8_short_int:
 ; ARM:       @ %bb.0: @ %entry
-; ARM-NEXT:    ldrb r0, [r0]
 ; ARM-NEXT:    ldrb r1, [r1]
-; ARM-NEXT:    and r0, r1, r0
+; ARM-NEXT:    ldrb r0, [r0]
+; ARM-NEXT:    and r0, r0, r1
 ; ARM-NEXT:    clz r0, r0
 ; ARM-NEXT:    lsr r0, r0, #5
 ; ARM-NEXT:    bx lr
 ;
 ; ARMEB-LABEL: cmp_and8_short_int:
 ; ARMEB:       @ %bb.0: @ %entry
-; ARMEB-NEXT:    ldrb r0, [r0, #1]
 ; ARMEB-NEXT:    ldrb r1, [r1, #3]
-; ARMEB-NEXT:    and r0, r1, r0
+; ARMEB-NEXT:    ldrb r0, [r0, #1]
+; ARMEB-NEXT:    and r0, r0, r1
 ; ARMEB-NEXT:    clz r0, r0
 ; ARMEB-NEXT:    lsr r0, r0, #5
 ; ARMEB-NEXT:    bx lr
 ;
 ; THUMB1-LABEL: cmp_and8_short_int:
 ; THUMB1:       @ %bb.0: @ %entry
-; THUMB1-NEXT:    ldrb r0, [r0]
 ; THUMB1-NEXT:    ldrb r1, [r1]
-; THUMB1-NEXT:    ands r1, r0
-; THUMB1-NEXT:    rsbs r0, r1, #0
-; THUMB1-NEXT:    adcs r0, r1
+; THUMB1-NEXT:    ldrb r2, [r0]
+; THUMB1-NEXT:    ands r2, r1
+; THUMB1-NEXT:    rsbs r0, r2, #0
+; THUMB1-NEXT:    adcs r0, r2
 ; THUMB1-NEXT:    bx lr
 ;
 ; THUMB2-LABEL: cmp_and8_short_int:
 ; THUMB2:       @ %bb.0: @ %entry
-; THUMB2-NEXT:    ldrb r0, [r0]
 ; THUMB2-NEXT:    ldrb r1, [r1]
+; THUMB2-NEXT:    ldrb r0, [r0]
 ; THUMB2-NEXT:    ands r0, r1
 ; THUMB2-NEXT:    clz r0, r0
 ; THUMB2-NEXT:    lsrs r0, r0, #5
 ; THUMB2-NEXT:    bx lr
 entry:
   %0 = load i16, i16* %a, align 2
   %1 = load i32, i32* %b, align 4
   %2 = and i16 %0, 255
entry:
   %and = and i32 %or, 65535
   ret i32 %and
 }
 
 define arm_aapcscc i1 @test6(i8* %x, i8 %y, i8 %z) {
 ; ARM-LABEL: test6:
 ; ARM:       @ %bb.0: @ %entry
 ; ARM-NEXT:    ldrb r0, [r0]
-; ARM-NEXT:    and r0, r0, r1
+; ARM-NEXT:    and r0, r1, r0
 ; ARM-NEXT:    uxtb r1, r2
 ; ARM-NEXT:    sub r0, r0, r1
 ; ARM-NEXT:    clz r0, r0
 ; ARM-NEXT:    lsr r0, r0, #5
 ; ARM-NEXT:    bx lr
 ;
 ; ARMEB-LABEL: test6:
 ; ARMEB:       @ %bb.0: @ %entry
 ; ARMEB-NEXT:    ldrb r0, [r0]
-; ARMEB-NEXT:    and r0, r0, r1
+; ARMEB-NEXT:    and r0, r1, r0
 ; ARMEB-NEXT:    uxtb r1, r2
 ; ARMEB-NEXT:    sub r0, r0, r1
 ; ARMEB-NEXT:    clz r0, r0
 ; ARMEB-NEXT:    lsr r0, r0, #5
 ; ARMEB-NEXT:    bx lr
 ;
 ; THUMB1-LABEL: test6:
 ; THUMB1:       @ %bb.0: @ %entry
entry:
   %2 = icmp eq i8 %1, %z
   ret i1 %2
 }
 
 define arm_aapcscc i1 @test7(i16* %x, i16 %y, i8 %z) {
 ; ARM-LABEL: test7:
 ; ARM:       @ %bb.0: @ %entry
 ; ARM-NEXT:    ldrb r0, [r0]
-; ARM-NEXT:    and r0, r0, r1
+; ARM-NEXT:    and r0, r1, r0
 ; ARM-NEXT:    uxtb r1, r2
 ; ARM-NEXT:    sub r0, r0, r1
 ; ARM-NEXT:    clz r0, r0
 ; ARM-NEXT:    lsr r0, r0, #5
 ; ARM-NEXT:    bx lr
 ;
 ; ARMEB-LABEL: test7:
 ; ARMEB:       @ %bb.0: @ %entry
 ; ARMEB-NEXT:    ldrb r0, [r0, #1]
-; ARMEB-NEXT:    and r0, r0, r1
+; ARMEB-NEXT:    and r0, r1, r0
 ; ARMEB-NEXT:    uxtb r1, r2
 ; ARMEB-NEXT:    sub r0, r0, r1
 ; ARMEB-NEXT:    clz r0, r0
 ; ARMEB-NEXT:    lsr r0, r0, #5
 ; ARMEB-NEXT:    bx lr
 ;
 ; THUMB1-LABEL: test7:
 ; THUMB1:       @ %bb.0: @ %entry

 ; THUMB2-NEXT:    lsls r1, r0, #16
 ; THUMB2-NEXT:    movs r0, #0
 ; THUMB2-NEXT:    bx lr
   %1 = load i64, i64* %p, align 8
   %and = and i64 %1, -281474976710656
   ret i64 %and
 }
 
+define void @test27(i32* nocapture %ptr) {
 ; ARM-LABEL: test27:
-; ARM:       @ %bb.0:
+; ARM:       @ %bb.0: @ %entry
 ; ARM-NEXT:    ldrb r1, [r0, #1]
 ; ARM-NEXT:    lsl r1, r1, #16
 ; ARM-NEXT:    str r1, [r0]
 ; ARM-NEXT:    bx lr
 ;
 ; ARMEB-LABEL: test27:
-; ARMEB:     @ %bb.0:
-; ARMEB-NEXT:  ldrb r1, [r0, #2]
-; ARMEB-NEXT:  lsl r1, r1, #16
-; ARMEB-NEXT:  str r1, [r0]
-; ARMEB-NEXT:  bx lr
+; ARMEB:       @ %bb.0: @ %entry
+; ARMEB-NEXT:    ldrb r1, [r0, #2]
+; ARMEB-NEXT:    lsl r1, r1, #16
+; ARMEB-NEXT:    str r1, [r0]
+; ARMEB-NEXT:    bx lr
 ;
 ; THUMB1-LABEL: test27:
-; THUMB1:     @ %bb.0:
-; THUMB1-NEXT:  ldrb r1, [r0, #1]
-; THUMB1-NEXT:  lsls r1, r1, #16
-; THUMB1-NEXT:  str r1, [r0]
-; THUMB1-NEXT:  bx lr
+; THUMB1:       @ %bb.0: @ %entry
+; THUMB1-NEXT:    ldrb r1, [r0, #1]
+; THUMB1-NEXT:    lsls r1, r1, #16
+; THUMB1-NEXT:    str r1, [r0]
+; THUMB1-NEXT:    bx lr
 ;
 ; THUMB2-LABEL: test27:
-; THUMB2:       @ %bb.0:
+; THUMB2:       @ %bb.0: @ %entry
 ; THUMB2-NEXT:    ldrb r1, [r0, #1]
 ; THUMB2-NEXT:    lsls r1, r1, #16
 ; THUMB2-NEXT:    str r1, [r0]
 ; THUMB2-NEXT:    bx lr
-define void @test27(i32* nocapture %ptr) {
 entry:
   %0 = load i32, i32* %ptr, align 4
   %and = and i32 %0, 65280
   %shl = shl i32 %and, 8
   store i32 %shl, i32* %ptr, align 4
   ret void
 }

llvm/trunk/test/CodeGen/ARM/load-combine-big-endian.ll

; CHECK-ARMv6-NEXT: bx  lr
   ret i32 %tmp26
 }
 
 ; i8* arg; i32 i;
 ; p = arg + 12;
 ; (i32) p[i + 1] | ((i32) p[i + 2] << 8) | ((i32) p[i + 3] << 16) | ((i32) p[i + 4] << 24)
 define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
 ; CHECK-LABEL: load_i32_by_i8_base_offset_index_2:
-; CHECK: add r0, r0, r1
+; CHECK: add r0, r1, r0
 ; CHECK-NEXT: mov r1, #65280
 ; CHECK-NEXT: mov r2, #16711680
 ; CHECK-NEXT: ldr r0, [r0, #13]
 ; CHECK-NEXT: and r1, r1, r0, lsr #8
 ; CHECK-NEXT: and r2, r2, r0, lsl #8
 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
 ; CHECK-NEXT: orr r0, r2, r0, lsl #24
 ; CHECK-NEXT: orr r0, r0, r1
 ; CHECK-NEXT: mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index_2:
-; CHECK-ARMv6: add r0, r0, r1
+; CHECK-ARMv6: add r0, r1, r0
 ; CHECK-ARMv6-NEXT: ldr r0, [r0, #13]
 ; CHECK-ARMv6-NEXT: rev r0, r0
 ; CHECK-ARMv6-NEXT: bx  lr
 
   %tmp = add nuw nsw i32 %i, 4
   %tmp2 = add nuw nsw i32 %i, 3
   %tmp3 = add nuw nsw i32 %i, 2
   %tmp4 = getelementptr inbounds i8, i8* %arg, i64 12

llvm/trunk/test/CodeGen/ARM/load-combine.ll

; CHECK-ARMv6-NEXT: bx  lr
   ret i32 %tmp26
 }
 
 ; i8* arg; i32 i;
 ; p = arg + 12;
 ; (i32) p[i + 1] | ((i32) p[i + 2] << 8) | ((i32) p[i + 3] << 16) | ((i32) p[i + 4] << 24)
 define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
 ; CHECK-LABEL: load_i32_by_i8_base_offset_index_2:
-; CHECK: add r0, r0, r1
+; CHECK: add r0, r1, r0
 ; CHECK-NEXT: ldr r0, [r0, #13]
 ; CHECK-NEXT: mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index_2:
-; CHECK-ARMv6: add r0, r0, r1
+; CHECK-ARMv6: add r0, r1, r0
 ; CHECK-ARMv6-NEXT: ldr r0, [r0, #13]
 ; CHECK-ARMv6-NEXT: bx  lr
   %tmp = add nuw nsw i32 %i, 4
   %tmp2 = add nuw nsw i32 %i, 3
   %tmp3 = add nuw nsw i32 %i, 2
   %tmp4 = getelementptr inbounds i8, i8* %arg, i64 12
   %tmp5 = add nuw nsw i32 %i, 1
   %tmp27 = zext i32 %tmp5 to i64

llvm/trunk/test/CodeGen/SystemZ/buildvector-00.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 ; Test that the dag combiner can understand that some vector operands are
 ; all-zeros and then optimize the logical operations.
 
 define void @f1(<2 x i64> %a0) {
 ; CHECK-LABEL: f1:
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    vlrepg %v0, 0(%r1)
 ; CHECK-NEXT:    vgbm %v1, 0
 ; CHECK-NEXT:    vceqg %v2, %v24, %v1
 ; CHECK-NEXT:    vn %v0, %v0, %v0
 ; CHECK-NEXT:    vno %v2, %v2, %v2
 ; CHECK-NEXT:    vceqg %v0, %v0, %v1
-; CHECK-NEXT:    vx %v0, %v2, %v0
+; CHECK-NEXT:    vx %v0, %v0, %v2
 ; CHECK-NEXT:    vnc %v0, %v2, %v0
 ; CHECK-NEXT:    vlgvf %r0, %v0, 1
 ; CHECK-NEXT:    tmll %r0, 1
 ; CHECK-NEXT:  # %bb.1: # %bb15
 
 bb:
   %tmp = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> zeroinitializer
   br label %bb1

llvm/trunk/test/CodeGen/Thumb2/constant-hoisting.ll

 ; CHECK-V6M-NEXT:    beq .LBB0_7
 ; CHECK-V6M-NEXT:    cmp r2, #30
 ; CHECK-V6M-NEXT:    beq .LBB0_8
 ; CHECK-V6M-NEXT:    cmp r2, #0
 ; CHECK-V6M-NEXT:    bne .LBB0_6
 ; CHECK-V6M-NEXT:    adds r0, r1, r0
 ; CHECK-V6M-NEXT:    bx lr
 ; CHECK-V6M-NEXT:  .LBB0_5:
-; CHECK-V6M-NEXT:    adds r0, r1, r0
+; CHECK-V6M-NEXT:    adds r0, r0, r1
 ; CHECK-V6M-NEXT:    adds r0, r0, #4
 ; CHECK-V6M-NEXT:  .LBB0_6:
 ; CHECK-V6M-NEXT:    bx lr
 ; CHECK-V6M-NEXT:  .LBB0_7:
-; CHECK-V6M-NEXT:    adds r0, r1, r0
+; CHECK-V6M-NEXT:    adds r0, r0, r1
 ; CHECK-V6M-NEXT:    adds r0, r0, #1
 ; CHECK-V6M-NEXT:    bx lr
 ; CHECK-V6M-NEXT:  .LBB0_8:
-; CHECK-V6M-NEXT:    adds r0, r1, r0
+; CHECK-V6M-NEXT:    adds r0, r0, r1
 ; CHECK-V6M-NEXT:    adds r0, r0, #2
 ; CHECK-V6M-NEXT:    bx lr
 ; CHECK-V6M-NEXT:    .p2align 2
 ; CHECK-V6M-NEXT:  .LCPI0_0:
 ; CHECK-V6M-NEXT:    .long 537923600
 ;
 ; CHECK-V7M-LABEL: test_values:
 ; CHECK-V7M:         mov r2, r0

llvm/trunk/test/CodeGen/WebAssembly/address-offsets.ll

 ; CHECK-NEXT: .functype load_test10 (i32) -> (i32){{$}}
 ; NON-PIC-NEXT:  i32.const $push0=, 2{{$}}
 ; NON-PIC-NEXT:  i32.shl   $push1=, $0, $pop0{{$}}
 ; NON-PIC-NEXT:  i32.const $push2=, g-40{{$}}
 ; NON-PIC-NEXT:  i32.add   $push3=, $pop1, $pop2{{$}}
 ; NON-PIC-NEXT:  i32.load  $push4=, 0($pop3){{$}}
 ; NON-PIC-NEXT:  return    $pop4{{$}}
 
-; PIC-NEXT:   global.get $push2=, g@GOT{{$}}
 ; PIC-NEXT:   i32.const $push0=, 2{{$}}
 ; PIC-NEXT:   i32.shl   $push1=, $0, $pop0{{$}}
-; PIC-NEXT:   i32.add   $push3=, $pop2, $pop1{{$}}
+; PIC-NEXT:   global.get $push2=, g@GOT{{$}}
+; PIC-NEXT:   i32.add   $push3=, $pop1, $pop2{{$}}
 ; PIC-NEXT:   i32.const $push4=, -40{{$}}
 ; PIC-NEXT:   i32.add   $push5=, $pop3, $pop4{{$}}
 ; PIC-NEXT:   i32.load  $push6=, 0($pop5){{$}}
 ; PIC-NEXT:   return    $pop6{{$}}
 define i32 @load_test10(i32 %n) {
   %add = add nsw i32 %n, -10
   %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add
   %t = load i32, i32* %arrayidx, align 4
define i32 @load_test11_noinbounds(i32* %p) {
   %t = load i32, i32* %arrayidx, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test12:
 ; CHECK-NEXT: .functype load_test12 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
-; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
+; CHECK-NEXT: i32.add   $push2=, $pop1, $0{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.load  $push5=, 0($pop4){{$}}
 ; CHECK-NEXT: return    $pop5{{$}}
 define i32 @load_test12(i32* %p, i32 %n) {
   %add = add nsw i32 %n, 10
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 %add
   %t = load i32, i32* %arrayidx, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test13:
 ; CHECK-NEXT: .functype load_test13 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
-; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
+; CHECK-NEXT: i32.add   $push2=, $pop1, $0{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.load  $push5=, 0($pop4){{$}}
 ; CHECK-NEXT: return    $pop5{{$}}
 define i32 @load_test13(i32* %p, i32 %n) {
   %add = add nsw i32 10, %n
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 %add
   %t = load i32, i32* %arrayidx, align 4
define i32 @load_test16(i32* %p, i32 %n) {
   %t = load i32, i32* %add.ptr1, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test17:
 ; CHECK-NEXT: .functype load_test17 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
-; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
+; CHECK-NEXT: i32.add   $push2=, $pop1, $0{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.load  $push5=, 0($pop4){{$}}
 ; CHECK-NEXT: return    $pop5{{$}}
 define i32 @load_test17(i32* %p, i32 %n) {
   %add = add nsw i32 %n, 10
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %add
   %t = load i32, i32* %add.ptr, align 4
define i32 @load_test18(i32* %p, i32 %n) {
   %t = load i32, i32* %add.ptr1, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test19:
 ; CHECK-NEXT: .functype load_test19 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
-; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
+; CHECK-NEXT: i32.add   $push2=, $pop1, $0{{$}}
 ; CHECK-NEXT: i32.const $push3=, 40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.load  $push5=, 0($pop4){{$}}
 ; CHECK-NEXT: return    $pop5{{$}}
 define i32 @load_test19(i32* %p, i32 %n) {
   %add = add nsw i32 10, %n
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %add
   %t = load i32, i32* %add.ptr, align 4
define i32 @load_test20(i32* %p) {
   %t = load i32, i32* %arrayidx, align 4
   ret i32 %t
 }
 
 ; CHECK-LABEL: load_test21:
 ; CHECK-NEXT: .functype load_test21 (i32, i32) -> (i32){{$}}
 ; CHECK-NEXT: i32.const $push0=, 2{{$}}
 ; CHECK-NEXT: i32.shl   $push1=, $1, $pop0{{$}}
-; CHECK-NEXT: i32.add   $push2=, $0, $pop1{{$}}
+; CHECK-NEXT: i32.add   $push2=, $pop1, $0{{$}}
 ; CHECK-NEXT: i32.const $push3=, -40{{$}}
 ; CHECK-NEXT: i32.add   $push4=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.load  $push5=, 0($pop4){{$}}
 ; CHECK-NEXT: return    $pop5{{$}}
 define i32 @load_test21(i32* %p, i32 %n) {
   %add = add nsw i32 %n, -10
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 %add
   %t = load i32, i32* %arrayidx, align 4

 
 ; CHECK-LABEL: store_test10:
 ; CHECK-NEXT: .functype store_test10 (i32, i32) -> (){{$}}
 ; NON-PIC-NEXT:  i32.const $push0=, 2{{$}}
 ; NON-PIC-NEXT:  i32.shl   $push1=, $0, $pop0{{$}}
 ; NON-PIC-NEXT:  i32.const $push2=, g-40{{$}}
 ; NON-PIC-NEXT:  i32.add   $push3=, $pop1, $pop2{{$}}
 ; NON-PIC-NEXT:  i32.store 0($pop3), $1{{$}}
-; PIC-NEXT: global.get $push2=, g@GOT{{$}}
 ; PIC-NEXT: i32.const  $push0=, 2{{$}}
 ; PIC-NEXT: i32.shl    $push1=, $0, $pop0{{$}}
-; PIC-NEXT: i32.add    $push3=, $pop2, $pop1{{$}}
+; PIC-NEXT: global.get $push2=, g@GOT{{$}}
+; PIC-NEXT: i32.add    $push3=, $pop1, $pop2{{$}}
 ; PIC-NEXT: i32.const  $push4=, -40{{$}}
 ; PIC-NEXT: i32.add    $push5=, $pop3, $pop4{{$}}
 ; PIC-NEXT: i32.store  0($pop5), $1{{$}}
 ; CHECK-NEXT:  return{{$}}
 define void @store_test10(i32 %n, i32 %i) {
   %add = add nsw i32 %n, -10
   %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @g, i32 0, i32 %add
   store i32 %i, i32* %arrayidx, align 4
define void @store_test11_noinbounds(i32* %p, i32 %i) {
   store i32 %i, i32* %arrayidx, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test12:
 ; CHECK-NEXT: .functype store_test12 (i32, i32, i32) -> (){{$}}
 ; NON-PIC-NEXT:  i32.const $push0=, 2{{$}}
 ; NON-PIC-NEXT:  i32.shl   $push1=, $1, $pop0{{$}}
-; NON-PIC-NEXT:  i32.add   $push2=, $0, $pop1{{$}}
+; NON-PIC-NEXT:  i32.add   $push2=, $pop1, $0{{$}}
 ; NON-PIC-NEXT:  i32.const $push3=, 40{{$}}
 ; NON-PIC-NEXT:  i32.add   $push4=, $pop2, $pop3{{$}}
 ; NON-PIC-NEXT:  i32.store 0($pop4), $2{{$}}
 ; NON-PIC-NEXT:  return{{$}}
 define void @store_test12(i32* %p, i32 %n, i32 %i) {
   %add = add nsw i32 %n, 10
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 %add
   store i32 %i, i32* %arrayidx, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test13:
 ; CHECK-NEXT: .functype store_test13 (i32, i32, i32) -> (){{$}}
 ; NON-PIC-NEXT:  i32.const $push0=, 2{{$}}
 ; NON-PIC-NEXT:  i32.shl   $push1=, $1, $pop0{{$}}
-; NON-PIC-NEXT:  i32.add   $push2=, $0, $pop1{{$}}
+; NON-PIC-NEXT:  i32.add   $push2=, $pop1, $0{{$}}
 ; NON-PIC-NEXT:  i32.const $push3=, 40{{$}}
 ; NON-PIC-NEXT:  i32.add   $push4=, $pop2, $pop3{{$}}
 ; NON-PIC-NEXT:  i32.store 0($pop4), $2{{$}}
 ; NON-PIC-NEXT:  return{{$}}
 define void @store_test13(i32* %p, i32 %n, i32 %i) {
   %add = add nsw i32 10, %n
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 %add
   store i32 %i, i32* %arrayidx, align 4
define void @store_test16(i32* %p, i32 %n, i32 %i) {
   store i32 %i, i32* %add.ptr1, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test17:
 ; CHECK-NEXT: .functype store_test17 (i32, i32, i32) -> (){{$}}
 ; NON-PIC-NEXT:  i32.const $push0=, 2{{$}}
 ; NON-PIC-NEXT:  i32.shl   $push1=, $1, $pop0{{$}}
-; NON-PIC-NEXT:  i32.add   $push2=, $0, $pop1{{$}}
+; NON-PIC-NEXT:  i32.add   $push2=, $pop1, $0{{$}}
 ; NON-PIC-NEXT:  i32.const $push3=, 40{{$}}
 ; NON-PIC-NEXT:  i32.add   $push4=, $pop2, $pop3{{$}}
 ; NON-PIC-NEXT:  i32.store 0($pop4), $2{{$}}
 ; NON-PIC-NEXT:  return{{$}}
 define void @store_test17(i32* %p, i32 %n, i32 %i) {
   %add = add nsw i32 %n, 10
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %add
   store i32 %i, i32* %add.ptr, align 4
define void @store_test18(i32* %p, i32 %n, i32 %i) {
   store i32 %i, i32* %add.ptr1, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test19:
 ; CHECK-NEXT: .functype store_test19 (i32, i32, i32) -> (){{$}}
 ; NON-PIC-NEXT:  i32.const $push0=, 2{{$}}
 ; NON-PIC-NEXT:  i32.shl   $push1=, $1, $pop0{{$}}
-; NON-PIC-NEXT:  i32.add   $push2=, $0, $pop1{{$}}
+; NON-PIC-NEXT:  i32.add   $push2=, $pop1, $0{{$}}
 ; NON-PIC-NEXT:  i32.const $push3=, 40{{$}}
 ; NON-PIC-NEXT:  i32.add   $push4=, $pop2, $pop3{{$}}
 ; NON-PIC-NEXT:  i32.store 0($pop4), $2{{$}}
 ; NON-PIC-NEXT:  return{{$}}
 define void @store_test19(i32* %p, i32 %n, i32 %i) {
   %add = add nsw i32 10, %n
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %add
   store i32 %i, i32* %add.ptr, align 4
define void @store_test20(i32* %p, i32 %i) {
   store i32 %i, i32* %arrayidx, align 4
   ret void
 }
 
 ; CHECK-LABEL: store_test21:
 ; CHECK-NEXT: .functype store_test21 (i32, i32, i32) -> (){{$}}
 ; NON-PIC-NEXT:  i32.const $push0=, 2{{$}}
 ; NON-PIC-NEXT:  i32.shl   $push1=, $1, $pop0{{$}}
-; NON-PIC-NEXT:  i32.add   $push2=, $0, $pop1{{$}}
+; NON-PIC-NEXT:  i32.add   $push2=, $pop1, $0{{$}}
 ; NON-PIC-NEXT:  i32.const $push3=, -40{{$}}
 ; NON-PIC-NEXT:  i32.add   $push4=, $pop2, $pop3{{$}}
 ; NON-PIC-NEXT:  i32.store 0($pop4), $2{{$}}
 ; NON-PIC-NEXT:  return{{$}}
 define void @store_test21(i32* %p, i32 %n, i32 %i) {
   %add = add nsw i32 %n, -10
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 %add
   store i32 %i, i32* %arrayidx, align 4
   ret void
 }

llvm/trunk/test/CodeGen/X86/add-ext.ll

 
 ; An x86 bonus: If we promote the sext ahead of the 'add nsw',
 ; we allow LEA formation and eliminate an add instruction.
 
 define i64 @add_nsw_sext_add(i32 %i, i64 %x) {
 ; CHECK-LABEL: add_nsw_sext_add:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movslq %edi, %rax
-; CHECK-NEXT:    leaq 5(%rsi,%rax), %rax
+; CHECK-NEXT:    leaq 5(%rax,%rsi), %rax
 ; CHECK-NEXT:    retq
 
   %add = add nsw i32 %i, 5
   %ext = sext i32 %add to i64
   %idx = add i64 %x, %ext
   ret i64 %idx
 }
 

 }
 
 ; The typical use case: a 64-bit system where an 'int' is used as an index into an array.
 
 define i8* @gep8(i32 %i, i8* %x) {
 ; CHECK-LABEL: gep8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movslq %edi, %rax
-; CHECK-NEXT:    leaq 5(%rsi,%rax), %rax
+; CHECK-NEXT:    leaq 5(%rax,%rsi), %rax
 ; CHECK-NEXT:    retq
 
   %add = add nsw i32 %i, 5
   %ext = sext i32 %add to i64
   %idx = getelementptr i8, i8* %x, i64 %ext
   ret i8* %idx
 }
 

 
 ; LEA can't scale by 16, but the adds can still be combined into an LEA.
 
 define i128* @gep128(i32 %i, i128* %x) {
 ; CHECK-LABEL: gep128:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movslq %edi, %rax
 ; CHECK-NEXT:    shlq $4, %rax
-; CHECK-NEXT:    leaq 80(%rsi,%rax), %rax
+; CHECK-NEXT:    leaq 80(%rax,%rsi), %rax
 ; CHECK-NEXT:    retq
 
   %add = add nsw i32 %i, 5
   %ext = sext i32 %add to i64
   %idx = getelementptr i128, i128* %x, i64 %ext
   ret i128* %idx
 }
 
; CHECK-NEXT:    retq
   %idx3 = sext i32 %i to i64
   %gep3 = getelementptr i32, i32* %a, i64 %idx3
   store i32 %add3, i32* %gep3, align 4
   ret void
 }
 
 ; The same as @PR20134 but sign extension is replaced with zero extension
 define void @PR20134_zext(i32* %a, i32 %i) {
-; CHECK: # %bb.0:
-; CHECK-NEXT: movl %esi, %eax
-; CHECK-NEXT: movl 4(%rdi,%rax,4), %ecx
-; CHECK-NEXT: addl 8(%rdi,%rax,4), %ecx
-; CHECK-NEXT: movl %ecx, (%rdi,%rax,4)
-; CHECK-NEXT: retq
+; CHECK-LABEL: PR20134_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    movl 4(%rdi,%rax,4), %ecx
+; CHECK-NEXT:    addl 8(%rdi,%rax,4), %ecx
+; CHECK-NEXT:    movl %ecx, (%rdi,%rax,4)
+; CHECK-NEXT:    retq
 
   %add1 = add nuw i32 %i, 1
   %idx1 = zext i32 %add1 to i64
   %gep1 = getelementptr i32, i32* %a, i64 %idx1
   %load1 = load i32, i32* %gep1, align 4
 
   %add2 = add nuw i32 %i, 2
   %idx2 = zext i32 %add2 to i64

llvm/trunk/test/CodeGen/X86/combine-multiplies.ll

 ; Function Attrs: nounwind
 define void @testCombineMultiplies([100 x i32]* nocapture %a, i32 %lll) nounwind {
 ; CHECK-LABEL: testCombineMultiplies:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %esi
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    imull $400, %ecx, %edx # imm = 0x190
-; CHECK-NEXT:    leal (%eax,%edx), %esi
+; CHECK-NEXT:    leal (%edx,%eax), %esi
 ; CHECK-NEXT:    movl $11, 2020(%esi,%ecx,4)
-; CHECK-NEXT:    movl $22, 2080(%eax,%edx)
-; CHECK-NEXT:    movl $33, 10080(%eax,%edx)
+; CHECK-NEXT:    movl $22, 2080(%edx,%eax)
+; CHECK-NEXT:    movl $33, 10080(%edx,%eax)
 ; CHECK-NEXT:    popl %esi
 ; CHECK-NEXT:    retl
 entry:
   %add = add nsw i32 %lll, 5
   %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* %a, i32 %add, i32 %add
   store i32 11, i32* %arrayidx1, align 4
   %arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* %a, i32 %add, i32 20
   store i32 22, i32* %arrayidx3, align 4

llvm/trunk/test/CodeGen/X86/load-combine.ll

 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    movl 13(%eax,%ecx), %eax
 ; CHECK-NEXT:    retl
 ;
 ; CHECK64-LABEL: load_i32_by_i8_base_offset_index_2:
 ; CHECK64:       # %bb.0:
 ; CHECK64-NEXT:    movl %esi, %eax
-; CHECK64-NEXT:    movl 13(%rdi,%rax), %eax
+; CHECK64-NEXT:    movl 13(%rax,%rdi), %eax
 ; CHECK64-NEXT:    retq
   %tmp = add nuw nsw i32 %i, 4
   %tmp2 = add nuw nsw i32 %i, 3
   %tmp3 = add nuw nsw i32 %i, 2
   %tmp4 = getelementptr inbounds i8, i8* %arg, i64 12
   %tmp5 = add nuw nsw i32 %i, 1
   %tmp27 = zext i32 %tmp5 to i64
   %tmp28 = getelementptr inbounds i8, i8* %tmp4, i64 %tmp27

 ; In order to fold the pattern above we need to reassociate the address computation
 ; first. By the time the address computation is reassociated loads are combined to
 ; to zext and aext loads.
 define i32 @load_i32_by_i8_zaext_loads(i8* %arg, i32 %arg1) {
 ; CHECK-LABEL: load_i32_by_i8_zaext_loads:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK-NEXT:    movl 12(%eax,%ecx), %eax
+; CHECK-NEXT:    movl 12(%ecx,%eax), %eax
 ; CHECK-NEXT:    retl
 ;
 ; CHECK64-LABEL: load_i32_by_i8_zaext_loads:
 ; CHECK64:       # %bb.0:
 ; CHECK64-NEXT:    movl %esi, %eax
 ; CHECK64-NEXT:    movl 12(%rdi,%rax), %eax
 ; CHECK64-NEXT:    retq
   %tmp = add nuw nsw i32 %arg1, 3

 ; p3 = arg + i + 3;
 ;
 ; (i32) p0[12] | ((i32) p1[12] << 8) | ((i32) p2[12] << 16) | ((i32) p3[12] << 24)
 define i32 @load_i32_by_i8_zsext_loads(i8* %arg, i32 %arg1) {
 ; CHECK-LABEL: load_i32_by_i8_zsext_loads:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK-NEXT:    movl 12(%eax,%ecx), %eax
+; CHECK-NEXT:    movl 12(%ecx,%eax), %eax
 ; CHECK-NEXT:    retl
 ;
 ; CHECK64-LABEL: load_i32_by_i8_zsext_loads:
 ; CHECK64:       # %bb.0:
 ; CHECK64-NEXT:    movl %esi, %eax
 ; CHECK64-NEXT:    movl 12(%rdi,%rax), %eax
 ; CHECK64-NEXT:    retq
   %tmp = add nuw nsw i32 %arg1, 3

llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll

 ; GENERIC-NEXT:    shlq $4, %rcx
 ; GENERIC-NEXT:    andl $-16777216, %eax ## imm = 0xFF000000
 ; GENERIC-NEXT:    movl %edi, %ebx
 ; GENERIC-NEXT:    shrl $16, %ebx
 ; GENERIC-NEXT:    movzbl %bl, %ebx
 ; GENERIC-NEXT:    movzbl 2(%r8,%rbx,4), %ebx
 ; GENERIC-NEXT:    shll $16, %ebx
 ; GENERIC-NEXT:    orl %eax, %ebx
-; GENERIC-NEXT:    xorl 16(%rdx,%rcx), %ebx
+; GENERIC-NEXT:    xorl 16(%rcx,%rdx), %ebx
 ; GENERIC-NEXT:    shrl $8, %edi
 ; GENERIC-NEXT:    movzbl 3(%r9,%rdi,4), %eax
 ; GENERIC-NEXT:    shll $24, %eax
 ; GENERIC-NEXT:    movzbl %bpl, %edi
 ; GENERIC-NEXT:    movzbl 2(%r8,%rdi,4), %edi
 ; GENERIC-NEXT:    shll $16, %edi
 ; GENERIC-NEXT:    orl %eax, %edi
-; GENERIC-NEXT:    xorl 20(%rdx,%rcx), %edi
+; GENERIC-NEXT:    xorl 20(%rcx,%rdx), %edi
 ; GENERIC-NEXT:    movl %ebx, %eax
 ; GENERIC-NEXT:    shrl $24, %eax
 ; GENERIC-NEXT:    movb %al, (%rsi)
 ; GENERIC-NEXT:    shrl $16, %ebx
 ; GENERIC-NEXT:    movb %bl, 1(%rsi)
 ; GENERIC-NEXT:    movl %edi, %eax
 ; GENERIC-NEXT:    shrl $24, %eax
 ; GENERIC-NEXT:    movb %al, 4(%rsi)

 ; ATOM-NEXT:    movzbl 3(%r9,%rdi,4), %edi
 ; ATOM-NEXT:    movzbl 2(%r8,%rbp,4), %ebp
 ; ATOM-NEXT:    movzbl 2(%r8,%rax,4), %eax
 ; ATOM-NEXT:    shll $24, %edi
 ; ATOM-NEXT:    shll $16, %ebp
 ; ATOM-NEXT:    shll $16, %eax
 ; ATOM-NEXT:    orl %edi, %ebp
 ; ATOM-NEXT:    orl %r15d, %eax
-; ATOM-NEXT:    xorl 20(%rdx,%rcx), %ebp
-; ATOM-NEXT:    xorl 16(%rdx,%rcx), %eax
+; ATOM-NEXT:    xorl 20(%rcx,%rdx), %ebp
+; ATOM-NEXT:    xorl 16(%rcx,%rdx), %eax
 ; ATOM-NEXT:    movl %eax, %edi
 ; ATOM-NEXT:    shrl $16, %eax
 ; ATOM-NEXT:    shrl $24, %edi
 ; ATOM-NEXT:    movb %dil, (%rsi)
 ; ATOM-NEXT:    movb %al, 1(%rsi)
 ; ATOM-NEXT:    movl %ebp, %eax
 ; ATOM-NEXT:    shrl $16, %ebp
 ; ATOM-NEXT:    shrl $24, %eax

llvm/trunk/test/CodeGen/X86/merge_store.ll

entry:
 
   for.end:
   ret void
 }
 
 define void @indexed_store_merge(i64 %p, i8* %v) {
 ; CHECK-LABEL: indexed_store_merge:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movl $0, 2(%rsi,%rdi)
+; CHECK-NEXT:    movl $0, 2(%rdi,%rsi)
 ; CHECK-NEXT:    movb $0, (%rsi)
 ; CHECK-NEXT:    retq
 entry:
   %p2 = add nsw i64 %p, 2
   %v2 = getelementptr i8, i8* %v, i64 %p2
   store i8 0, i8* %v2, align 2
   %p3 = add nsw i64 %p, 3
   %v3 = getelementptr i8, i8* %v, i64 %p3

llvm/trunk/test/CodeGen/X86/sad.ll

 ; This contains an unrolled sad loop with a non-zero initial value.
 ; DAGCombiner reassociation previously rewrote the adds to move the constant vector further down the tree. This resulted in the vector-reduction flag being lost.
 define i32 @sad_unroll_nonzero_initial(<16 x i8>* %arg, <16 x i8>* %arg1, <16 x i8>* %arg2, <16 x i8>* %arg3) {
 ; SSE2-LABEL: sad_unroll_nonzero_initial:
 ; SSE2:       # %bb.0: # %bb
 ; SSE2-NEXT:    movdqu (%rdi), %xmm0
 ; SSE2-NEXT:    movdqu (%rsi), %xmm1
 ; SSE2-NEXT:    psadbw %xmm0, %xmm1
+; SSE2-NEXT:    movdqu (%rdx), %xmm0
+; SSE2-NEXT:    movdqu (%rcx), %xmm2
+; SSE2-NEXT:    psadbw %xmm0, %xmm2
 ; SSE2-NEXT:    movl $1, %eax
 ; SSE2-NEXT:    movd %eax, %xmm0
-; SSE2-NEXT:    paddd %xmm1, %xmm0
-; SSE2-NEXT:    movdqu (%rdx), %xmm1
-; SSE2-NEXT:    movdqu (%rcx), %xmm2
-; SSE2-NEXT:    psadbw %xmm1, %xmm2
-; SSE2-NEXT:    paddd %xmm0, %xmm2
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[2,3,0,1]
 ; SSE2-NEXT:    paddd %xmm2, %xmm0
-; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
+; SSE2-NEXT:    paddd %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
 ; SSE2-NEXT:    paddd %xmm0, %xmm1
-; SSE2-NEXT:    movd %xmm1, %eax
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,2,3]
+; SSE2-NEXT:    paddd %xmm1, %xmm0
+; SSE2-NEXT:    movd %xmm0, %eax
 ; SSE2-NEXT:    retq
 ;
 ; AVX1-LABEL: sad_unroll_nonzero_initial:
 ; AVX1:       # %bb.0: # %bb
 ; AVX1-NEXT:    vmovdqu (%rdi), %xmm0
 ; AVX1-NEXT:    vpsadbw (%rsi), %xmm0, %xmm0
 ; AVX1-NEXT:    vmovdqu (%rdx), %xmm1
 ; AVX1-NEXT:    vpsadbw (%rcx), %xmm1, %xmm1
 ; AVX1-NEXT:    movl $1, %eax
 ; AVX1-NEXT:    vmovd %eax, %xmm2
-; AVX1-NEXT:    vpaddd %xmm2, %xmm0, %xmm0
-; AVX1-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
+; AVX1-NEXT:    vpaddd %xmm2, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
 ; AVX1-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
 ; AVX1-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    vmovd %xmm0, %eax
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: sad_unroll_nonzero_initial:
 ; AVX2:       # %bb.0: # %bb
 ; AVX2-NEXT:    vmovdqu (%rdi), %xmm0
 ; AVX2-NEXT:    vpsadbw (%rsi), %xmm0, %xmm0
-; AVX2-NEXT:    movl $1, %eax
-; AVX2-NEXT:    vmovd %eax, %xmm1
-; AVX2-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
 ; AVX2-NEXT:    vmovdqu (%rdx), %xmm1
 ; AVX2-NEXT:    vpsadbw (%rcx), %xmm1, %xmm1
-; AVX2-NEXT:    vpaddd %ymm0, %ymm1, %ymm0
+; AVX2-NEXT:    movl $1, %eax
+; AVX2-NEXT:    vmovd %eax, %xmm2
+; AVX2-NEXT:    vpaddd %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; AVX2-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
 ; AVX2-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
 ; AVX2-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX2-NEXT:    vmovd %xmm0, %eax
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: sad_unroll_nonzero_initial:
 ; AVX512:       # %bb.0: # %bb
 ; AVX512-NEXT:    vmovdqu (%rdi), %xmm0
 ; AVX512-NEXT:    vpsadbw (%rsi), %xmm0, %xmm0
-; AVX512-NEXT:    movl $1, %eax
-; AVX512-NEXT:    vmovd %eax, %xmm1
-; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
 ; AVX512-NEXT:    vmovdqu (%rdx), %xmm1
 ; AVX512-NEXT:    vpsadbw (%rcx), %xmm1, %xmm1
-; AVX512-NEXT:    vpaddd %zmm0, %zmm1, %zmm0
+; AVX512-NEXT:    movl $1, %eax
+; AVX512-NEXT:    vmovd %eax, %xmm2
+; AVX512-NEXT:    vpaddd %zmm2, %zmm1, %zmm1
+; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
 ; AVX512-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
 ; AVX512-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
 ; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
 ; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0

llvm/trunk/test/CodeGen/X86/vector-ext-logic.ll

 ; SSE2-LABEL: zext_and_v8i16:
 ; SSE2:       # %bb.0:
 ; SSE2-NEXT:    andps %xmm1, %xmm0
 ; SSE2-NEXT:    andps {{.*}}(%rip), %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; AVX2-LABEL: zext_and_v8i16:
 ; AVX2:       # %bb.0:
-; AVX2-NEXT:    vandps %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vandps %xmm0, %xmm1, %xmm0
 ; AVX2-NEXT:    vandps {{.*}}(%rip), %xmm0, %xmm0
 ; AVX2-NEXT:    retq
   %xz = zext <8 x i8> %x to <8 x i16>
   %yz = zext <8 x i8> %y to <8 x i16>
   %r = and <8 x i16> %xz, %yz
   ret <8 x i16> %r
 }