[AArch64][MC] Reject "add x0, x1, w2, lsl #1" etc.

[efriedma]

Summary

Looks like just a minor oversight in the parsing code.

Fixes https://bugs.llvm.org/show_bug.cgi?id=41504.

[srhines]

Thanks for taking a look at this.

llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

return (ET == AArch64_AM::UXTB || ET == AArch64_AM::SXTB ||
             ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX ||
             ET == AArch64_AM::LSL) &&
            getShiftExtendAmount() <= 4;
   }
 
   bool isExtend64() const {
     if (!isExtend())
       return false;
-    // UXTX and SXTX require a 64-bit source register (the ExtendLSL64 class).
+    // Make sure the extend expects a 32-bit source register.
     AArch64_AM::ShiftExtendType ET = getShiftExtendType();
-    return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX;
+    return ET == AArch64_AM::UXTB || ET == AArch64_AM::SXTB ||
+           ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH ||
+           ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW;
   }
 
   bool isExtendLSL64() const {
     if (!isExtend())
       return false;
     AArch64_AM::ShiftExtendType ET = getShiftExtendType();
     return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX ||
             ET == AArch64_AM::LSL) &&
bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_InvalidOperand:
     return Error(Loc, "invalid operand for instruction");
   case Match_InvalidSuffix:
     return Error(Loc, "invalid type suffix for instruction");
   case Match_InvalidCondCode:
     return Error(Loc, "expected AArch64 condition code");
   case Match_AddSubRegExtendSmall:
     return Error(Loc,
-      "expected '[su]xt[bhw]' or 'lsl' with optional integer in range [0, 4]");
+      "expected '[su]xt[bhw]' with optional integer in range [0, 4]");
   case Match_AddSubRegExtendLarge:
     return Error(Loc,
       "expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]");
   case Match_AddSubSecondSource:
     return Error(Loc,
       "expected compatible register, symbol or integer in range [0, 4095]");
   case Match_LogicalSecondSource:
     return Error(Loc, "expected compatible register or logical immediate");

llvm/trunk/test/MC/AArch64/basic-a64-diagnostics.s

 // RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-ERROR --check-prefix=CHECK-ERROR-ARM64 < %t %s
 
 //------------------------------------------------------------------------------
 // Add/sub (extended register)
 //------------------------------------------------------------------------------
 
         // Mismatched final register and extend
         add x2, x3, x5, sxtb
         add x2, x4, w2, uxtx
+        add x2, x4, w2, lsl #3
         add w5, w7, x9, sxtx
 // CHECK-ERROR: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
 // CHECK-ERROR:         add x2, x3, x5, sxtb
 // CHECK-ERROR:                         ^
-// CHECK-ERROR: error: expected '[su]xt[bhw]' or 'lsl' with optional integer in range [0, 4]
+// CHECK-ERROR: error: expected '[su]xt[bhw]' with optional integer in range [0, 4]
 // CHECK-ERROR:         add x2, x4, w2, uxtx
 // CHECK-ERROR:                         ^
+// CHECK-ERROR: error: expected '[su]xt[bhw]' with optional integer in range [0, 4]
+// CHECK-ERROR:         add x2, x4, w2, lsl #3
+// CHECK-ERROR:                         ^
 // CHECK-ERROR: error: expected compatible register, symbol or integer in range [0, 4095]
 // CHECK-ERROR:         add w5, w7, x9, sxtx
 // CHECK-ERROR:                     ^
 
         // Out of range extends
         add x9, x10, w11, uxtb #-1
         add x3, x5, w7, uxtb #5
         sub x9, x15, x2, uxth #5
 // CHECK-ERROR: error: expected integer shift amount
 // CHECK-ERROR:         add x9, x10, w11, uxtb #-1
 // CHECK-ERROR:                                 ^
-// CHECK-ERROR: error: expected '[su]xt[bhw]' or 'lsl' with optional integer in range [0, 4]
+// CHECK-ERROR: error: expected '[su]xt[bhw]' with optional integer in range [0, 4]
 // CHECK-ERROR:         add x3, x5, w7, uxtb #5
 // CHECK-ERROR:                         ^
 // CHECK-ERROR: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
 // CHECK-ERROR:         sub x9, x15, x2, uxth #5
 // CHECK-ERROR:                          ^
 
         // Wrong registers on normal variants
         add xzr, x3, x5, uxtx