[AsmPrinter] defer %c to base class for ARM, PPC, and Hexagon. NFC

[nickdesaulniers]

Summary

None of these derived classes do anything that the base class cannot.
If we remove these case statements, then the base class can handle them
just fine.

[nickdesaulniers]

Note to Peter: the %a case is the same between Aarch64 and ARM (and should be basic enough to hoist up to the base case). That's going in next patch.

llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp

case '$': {
         // other point while processing. It's an error if so.
         if (OpNo >= MI->getNumOperands() ||
             MI->getOperand(OpNo).isMetadata()) {
           Error = true;
         } else {
           unsigned OpFlags = MI->getOperand(OpNo).getImm();
           ++OpNo;  // Skip over the ID number.
 
+          // FIXME: Shouldn't arch-independant output template handling go into
+          // PrintAsmOperand?
           if (Modifier[0] == 'l') { // Labels are target independent.
             if (MI->getOperand(OpNo).isBlockAddress()) {
               const BlockAddress *BA = MI->getOperand(OpNo).getBlockAddress();
               MCSymbol *Sym = AP->GetBlockAddressSymbol(BA);
               Sym->print(OS, AP->MAI);
             } else if (MI->getOperand(OpNo).isMBB()) {
               const MCSymbol *Sym = MI->getOperand(OpNo).getMBB()->getSymbol();
               Sym->print(OS, AP->MAI);

 /// instruction, using the specified assembler variant.  Targets should
 /// override this to format as appropriate.
 bool AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                  const char *ExtraCode, raw_ostream &O) {
   // Does this asm operand have a single letter operand modifier?
   if (ExtraCode && ExtraCode[0]) {
     if (ExtraCode[1] != 0) return true; // Unknown modifier.
 
+    // https://gcc.gnu.org/onlinedocs/gccint/Output-Template.html
     const MachineOperand &MO = MI->getOperand(OpNo);
     switch (ExtraCode[0]) {
     default:
       return true;  // Unknown modifier.
     case 'c': // Substitute immediate value without immediate syntax
       if (MO.getType() != MachineOperand::MO_Immediate)
         return true;
       O << MO.getImm();

llvm/lib/Target/ARM/ARMAsmPrinter.cpp

default:
       // See if this is a generic print operand
       return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
     case 'a': // Print as a memory address.
       if (MI->getOperand(OpNum).isReg()) {
         O << "["
           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
           << "]";
         return false;
-      }
-      LLVM_FALLTHROUGH;
-    case 'c': // Don't print "#" before an immediate operand.
-      if (!MI->getOperand(OpNum).isImm())
-        return true;
+      } else if (MI->getOperand(OpNum).isImm()) {
         O << MI->getOperand(OpNum).getImm();
         return false;
+      }
+      return true;
     case 'P': // Print a VFP double precision register.
     case 'q': // Print a NEON quad precision register.
       printOperand(MI, OpNum, O);
       return false;
     case 'y': // Print a VFP single precision register as indexed double.
       if (MI->getOperand(OpNum).isReg()) {
         unsigned Reg = MI->getOperand(OpNum).getReg();
         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();

llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp

bool HexagonAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
   if (ExtraCode && ExtraCode[0]) {
     if (ExtraCode[1] != 0)
       return true; // Unknown modifier.
 
     switch (ExtraCode[0]) {
     default:
       // See if this is a generic print operand
       return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
-    case 'c': // Don't print "$" before a global var name or constant.
-      // Hexagon never has a prefix.
-      printOperand(MI, OpNo, OS);
-      return false;
     case 'L':
     case 'H': { // The highest-numbered register of a pair.
       const MachineOperand &MO = MI->getOperand(OpNo);
       const MachineFunction &MF = *MI->getParent()->getParent();
       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
       if (!MO.isReg())
         return true;
       unsigned RegNumber = MO.getReg();

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

bool PPCAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
   // Does this asm operand have a single letter operand modifier?
   if (ExtraCode && ExtraCode[0]) {
     if (ExtraCode[1] != 0) return true; // Unknown modifier.
 
     switch (ExtraCode[0]) {
     default:
       // See if this is a generic print operand
       return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
-    case 'c': // Don't print "$" before a global var name or constant.
-      break; // PPC never has a prefix.
     case 'L': // Write second word of DImode reference.
       // Verify that this operand has two consecutive registers.
       if (!MI->getOperand(OpNo).isReg() ||
           OpNo+1 == MI->getNumOperands() ||
           !MI->getOperand(OpNo+1).isReg())
         return true;
       ++OpNo;   // Return the high-part.
       break;

llvm/test/CodeGen/ARM/inlineasm-output-template.ll

+; RUN: llc -mtriple=armv7-linux-gnueabi < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: @TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+  tail call void asm sideeffect "@TEST ${0:c}", "i"(i32 42)
+  ret i32 42
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: @TEST -42
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect "@TEST ${0:n}", "i"(i32 42)
+  ret i32 42
+}

llvm/test/CodeGen/Hexagon/inlineasm-output-template.ll

+; RUN: llc -mtriple=hexagon < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: //TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+  tail call void asm sideeffect "//TEST ${0:c}", "i"(i32 42)
+  ret i32 42
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: //TEST -42
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect "//TEST ${0:n}", "i"(i32 42)
+  ret i32 42
+}

llvm/test/CodeGen/PowerPC/inlineasm-output-template.ll

+; RUN: llc -mtriple=ppc32-- < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: #TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+  tail call void asm sideeffect "#TEST ${0:c}", "i"(i32 42)
+  ret i32 42
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: #TEST -42
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect "#TEST ${0:n}", "i"(i32 42)
+  ret i32 42
+}