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Differential D60731

[AMDGPU] Flag new raw/struct atomic ops as source of divergence
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Authored by tpr on Apr 15 2019, 2:26 PM.

Details

Reviewers
nhaehnle
arsenm
Commits
rG59e8bd3093dc: [AMDGPU] Flag new raw/struct atomic ops as source of divergence
rL358579: [AMDGPU] Flag new raw/struct atomic ops as source of divergence
Summary

Change-Id: I821d93dec8b9cdd247b8172d92fb5e15340a9e7d

Diff Detail

Event Timeline

tpr created this revision.Apr 15 2019, 2:26 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 15 2019, 2:26 PM
Herald added subscribers: llvm-commits, jfb, t-tye and 7 others. · View Herald Transcript
tpr added a reviewer: nhaehnle.Apr 15 2019, 2:28 PM
Harbormaster completed remote builds in B30581: Diff 195247.Apr 15 2019, 2:30 PM
arsenm added a comment.Apr 15 2019, 2:43 PM

The test should go with the rest in test/Analysis/DivergenceAnalysis

tpr updated this revision to Diff 195523.Apr 17 2019, 2:16 AM

V2: Addressed review comment: moved tests.

Harbormaster completed remote builds in B30670: Diff 195523.Apr 17 2019, 2:17 AM
arsenm accepted this revision.Apr 17 2019, 2:25 AM

LGTM

This revision is now accepted and ready to land.Apr 17 2019, 2:25 AM
Closed by commit rL358579: [AMDGPU] Flag new raw/struct atomic ops as source of divergence (authored by tpr). · Explain WhyApr 17 2019, 7:02 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
22 lines
test/
CodeGen/
AMDGPU/
226 lines

Diff 195247

lib/Target/AMDGPU/AMDGPUSearchableTables.td

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
def : SourceOfDivergence<int_amdgcn_buffer_atomic_smin>; def : SourceOfDivergence<int_amdgcn_buffer_atomic_smin>;
def : SourceOfDivergence<int_amdgcn_buffer_atomic_umin>; def : SourceOfDivergence<int_amdgcn_buffer_atomic_umin>;
def : SourceOfDivergence<int_amdgcn_buffer_atomic_smax>; def : SourceOfDivergence<int_amdgcn_buffer_atomic_smax>;
def : SourceOfDivergence<int_amdgcn_buffer_atomic_umax>; def : SourceOfDivergence<int_amdgcn_buffer_atomic_umax>;
def : SourceOfDivergence<int_amdgcn_buffer_atomic_and>; def : SourceOfDivergence<int_amdgcn_buffer_atomic_and>;
def : SourceOfDivergence<int_amdgcn_buffer_atomic_or>; def : SourceOfDivergence<int_amdgcn_buffer_atomic_or>;
def : SourceOfDivergence<int_amdgcn_buffer_atomic_xor>; def : SourceOfDivergence<int_amdgcn_buffer_atomic_xor>;
def : SourceOfDivergence<int_amdgcn_buffer_atomic_cmpswap>; def : SourceOfDivergence<int_amdgcn_buffer_atomic_cmpswap>;
def : SourceOfDivergence<int_amdgcn_raw_buffer_atomic_swap>;
def : SourceOfDivergence<int_amdgcn_raw_buffer_atomic_add>;
def : SourceOfDivergence<int_amdgcn_raw_buffer_atomic_sub>;
def : SourceOfDivergence<int_amdgcn_raw_buffer_atomic_smin>;
def : SourceOfDivergence<int_amdgcn_raw_buffer_atomic_umin>;
def : SourceOfDivergence<int_amdgcn_raw_buffer_atomic_smax>;
def : SourceOfDivergence<int_amdgcn_raw_buffer_atomic_umax>;
def : SourceOfDivergence<int_amdgcn_raw_buffer_atomic_and>;
def : SourceOfDivergence<int_amdgcn_raw_buffer_atomic_or>;
def : SourceOfDivergence<int_amdgcn_raw_buffer_atomic_xor>;
def : SourceOfDivergence<int_amdgcn_raw_buffer_atomic_cmpswap>;
def : SourceOfDivergence<int_amdgcn_struct_buffer_atomic_swap>;
def : SourceOfDivergence<int_amdgcn_struct_buffer_atomic_add>;
def : SourceOfDivergence<int_amdgcn_struct_buffer_atomic_sub>;
def : SourceOfDivergence<int_amdgcn_struct_buffer_atomic_smin>;
def : SourceOfDivergence<int_amdgcn_struct_buffer_atomic_umin>;
def : SourceOfDivergence<int_amdgcn_struct_buffer_atomic_smax>;
def : SourceOfDivergence<int_amdgcn_struct_buffer_atomic_umax>;
def : SourceOfDivergence<int_amdgcn_struct_buffer_atomic_and>;
def : SourceOfDivergence<int_amdgcn_struct_buffer_atomic_or>;
def : SourceOfDivergence<int_amdgcn_struct_buffer_atomic_xor>;
def : SourceOfDivergence<int_amdgcn_struct_buffer_atomic_cmpswap>;
def : SourceOfDivergence<int_amdgcn_ps_live>; def : SourceOfDivergence<int_amdgcn_ps_live>;
def : SourceOfDivergence<int_amdgcn_ds_swizzle>; def : SourceOfDivergence<int_amdgcn_ds_swizzle>;
def : SourceOfDivergence<int_amdgcn_ds_ordered_add>; def : SourceOfDivergence<int_amdgcn_ds_ordered_add>;
def : SourceOfDivergence<int_amdgcn_ds_ordered_swap>; def : SourceOfDivergence<int_amdgcn_ds_ordered_swap>;
foreach intr = AMDGPUImageDimAtomicIntrinsics in foreach intr = AMDGPUImageDimAtomicIntrinsics in
def : SourceOfDivergence<intr>; def : SourceOfDivergence<intr>;

test/CodeGen/AMDGPU/source_of_divergence.ll

  • This file was added.
; RUN: llc -march=amdgcn -mcpu=gfx900 <%s | FileCheck -check-prefix=GCN %s
; Ensure that all the raw and struct atomic intrinsics are a source of divergence.
; GCN-LABEL: raw_buffer_atomic_swap:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @raw_buffer_atomic_swap(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: raw_buffer_atomic_add:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @raw_buffer_atomic_add(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: raw_buffer_atomic_sub:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @raw_buffer_atomic_sub(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.raw.buffer.atomic.sub.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: raw_buffer_atomic_smin:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @raw_buffer_atomic_smin(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.raw.buffer.atomic.smin.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: raw_buffer_atomic_umin:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @raw_buffer_atomic_umin(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.raw.buffer.atomic.umin.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: raw_buffer_atomic_smax:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @raw_buffer_atomic_smax(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.raw.buffer.atomic.smax.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: raw_buffer_atomic_umax:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @raw_buffer_atomic_umax(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.raw.buffer.atomic.umax.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: raw_buffer_atomic_and:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @raw_buffer_atomic_and(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.raw.buffer.atomic.and.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: raw_buffer_atomic_or:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @raw_buffer_atomic_or(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.raw.buffer.atomic.or.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: raw_buffer_atomic_xor:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @raw_buffer_atomic_xor(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.raw.buffer.atomic.xor.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: raw_buffer_atomic_cmpswap:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @raw_buffer_atomic_cmpswap(i32 inreg %val, i32 inreg %cmp, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %desc, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: struct_buffer_atomic_swap:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @struct_buffer_atomic_swap(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.struct.buffer.atomic.swap.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: struct_buffer_atomic_add:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @struct_buffer_atomic_add(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: struct_buffer_atomic_sub:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @struct_buffer_atomic_sub(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: struct_buffer_atomic_smin:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @struct_buffer_atomic_smin(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.struct.buffer.atomic.smin.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: struct_buffer_atomic_umin:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @struct_buffer_atomic_umin(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.struct.buffer.atomic.umin.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: struct_buffer_atomic_smax:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @struct_buffer_atomic_smax(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.struct.buffer.atomic.smax.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: struct_buffer_atomic_umax:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @struct_buffer_atomic_umax(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.struct.buffer.atomic.umax.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: struct_buffer_atomic_and:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @struct_buffer_atomic_and(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.struct.buffer.atomic.and.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: struct_buffer_atomic_or:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @struct_buffer_atomic_or(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.struct.buffer.atomic.or.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: struct_buffer_atomic_xor:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @struct_buffer_atomic_xor(i32 inreg %val, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 %val, <4 x i32> %desc, i32 0, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
; GCN-LABEL: struct_buffer_atomic_cmpswap:
; GCN: buffer_load_dword v{{[0-9]+}},
define amdgpu_ps void @struct_buffer_atomic_cmpswap(i32 inreg %val, i32 inreg %cmp, <4 x i32> inreg %desc, i32 addrspace(4)* inreg %ptr) {
%res = call i32 @llvm.amdgcn.struct.buffer.atomic.cmpswap.i32(i32 %val, i32 %cmp, <4 x i32> %desc, i32 0, i32 0, i32 0, i32 0)
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %res, i32 0)
store i32 %load, i32 addrspace(5)* undef
ret void
}
declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32)
declare i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32, <4 x i32>, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.raw.buffer.atomic.sub.i32(i32, <4 x i32>, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.raw.buffer.atomic.smin.i32(i32, <4 x i32>, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.raw.buffer.atomic.umin.i32(i32, <4 x i32>, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.raw.buffer.atomic.smax.i32(i32, <4 x i32>, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.raw.buffer.atomic.umax.i32(i32, <4 x i32>, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.raw.buffer.atomic.and.i32(i32, <4 x i32>, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.raw.buffer.atomic.or.i32(i32, <4 x i32>, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.raw.buffer.atomic.xor.i32(i32, <4 x i32>, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i32(i32, i32, <4 x i32>, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.struct.buffer.atomic.swap.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.struct.buffer.atomic.smin.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.struct.buffer.atomic.umin.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.struct.buffer.atomic.smax.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.struct.buffer.atomic.umax.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.struct.buffer.atomic.and.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.struct.buffer.atomic.or.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.struct.buffer.atomic.cmpswap.i32(i32, i32, <4 x i32>, i32, i32, i32, i32 immarg)